[PATCH] drm/ast: Fix incorrect register check for DRAM width

2016-03-02 Thread Dave Airlie
On 2 March 2016 at 04:58, Timothy Pearson wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > On 02/26/2016 03:29 PM, Timothy Pearson wrote: >> During DRAM initialization on certain ASpeed devices, an incorrect >> bit (bit 10) was checked in the "SDRAM Bus Width Status" register >> to det

[PATCH] drm/ast: Fix incorrect register check for DRAM width

2016-03-01 Thread Timothy Pearson
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 02/26/2016 03:29 PM, Timothy Pearson wrote: > During DRAM initialization on certain ASpeed devices, an incorrect > bit (bit 10) was checked in the "SDRAM Bus Width Status" register > to determine DRAM width. > > Query bit 6 instead in accordance wi

[PATCH] drm/ast: Fix incorrect register check for DRAM width

2016-02-26 Thread Timothy Pearson
During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Signed-off-by: Timothy Pearson --- drivers/gpu/drm/ast/ast_mai

[PATCH] drm/ast: Fix incorrect register check for DRAM width

2016-02-25 Thread Timothy Pearson
During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Signed-off-by: Timothy Pearson --- drivers/gpu/drm/ast/ast_mai