[PATCH] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines

Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache line can contain two instruction cache lines (64B), or four data cache lines (32B). Hardware prefetch Cache detects stream access, and prefetches ahead of processor access. Add support to inavalidate BMIPS5000 cpu zephyr se

Re: [PATCH] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines

On 2/6/2020 11:30 AM, Kamal Dasu wrote: > Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache > line can contain two instruction cache lines (64B), or four data cache > lines (32B). Hardware prefetch Cache detects stream access, and prefetches > ahead of processor access.