On Tue, Mar 19, 2019 at 02:26:01PM +0100, Marek Szyprowski wrote:
> ACLK400_DISP1 bus feeds some internal buses of the display subsystem, some
> of which are also related to TV/Mixer hardware modules. When that bus
> is set to 120MHz, Exynos Mixer is not able to properly handle two XRGB
> display p
ACLK400_DISP1 bus feeds some internal buses of the display subsystem, some
of which are also related to TV/Mixer hardware modules. When that bus
is set to 120MHz, Exynos Mixer is not able to properly handle two XRGB
display planes at FullHD-60MHz. DMA underrun happens, which in turn might
result in
