On Thu, Mar 24, 2022 at 01:40:37AM +0200, Chery, Nanley G wrote:
> > [...]
> > Capturing all the above would you be ok with the following?:
> >
> > Intel color control surfaces (CCS) for DG2 render compression.
> >
> > The main surface is Tile 4 and at plane index 0. The CCS data is stored
> > ou
> -Original Message-
> From: Deak, Imre
> Sent: Friday, March 18, 2022 10:40 AM
> To: Chery, Nanley G
> Cc: juhapekka.heikk...@gmail.com; Nanley Chery ; C,
> Ramalingam ; intel-gfx g...@lists.freedesktop.org>; Auld, Matthew ;
> dri-devel
> Subject: Re:
On Thu, Feb 17, 2022 at 05:15:15PM +, Chery, Nanley G wrote:
> > >> [...]
> > >> --- a/include/uapi/drm/drm_fourcc.h
> > >> +++ b/include/uapi/drm/drm_fourcc.h
> > >> @@ -583,6 +583,28 @@ extern "C" {
> > >>*/
> > >> #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
> > >>
> -Original Message-
> From: Juha-Pekka Heikkila
> Sent: Tuesday, February 15, 2022 6:54 AM
> To: Nanley Chery ; C, Ramalingam
>
> Cc: intel-gfx ; Chery, Nanley G
> ; Auld, Matthew ; dri-
> devel
> Subject: Re: [Intel-gfx] [PATCH v5 15/19] drm/i915/dg2: Ad
On 12.2.2022 3.17, Nanley Chery wrote:
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
From: Matt Roper
DG2 unifies render compression and media compression into a single
format for the first time. The programming and buffer layout is
supposed to match compression on older gen12 platform
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
>
> From: Matt Roper
>
> DG2 unifies render compression and media compression into a single
> format for the first time. The programming and buffer layout is
> supposed to match compression on older gen12 platforms, but the actual
> compression
