On 5/26/2023 1:43 AM, Dmitry Baryshkov wrote:
On Fri, 26 May 2023 at 01:42, Abhinav Kumar wrote:
On 5/25/2023 3:30 PM, Dmitry Baryshkov wrote:
On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
wrote:
On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
There is no point in having a single enum (a
On Fri, 26 May 2023 at 01:42, Abhinav Kumar wrote:
> On 5/25/2023 3:30 PM, Dmitry Baryshkov wrote:
> > On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
> > wrote:
> >> On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
> >>> There is no point in having a single enum (and a single array) for both
> >>>
On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.
Signed-off-by: Dmitry Baryshkov
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.../msm/disp/dpu1/catalog/dpu_7_0
On 5/25/2023 3:30 PM, Dmitry Baryshkov wrote:
On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
wrote:
On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
wrote:
>
>
>
> On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
> > There is no point in having a single enum (and a single array) for both
> > DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
> > enum and two IRQ address arrays.
>
