; Subject: Re: "Fixes" for page flipping under PRIME on AMD & nouveau
>
> On 27/08/16 04:57 AM, Mario Kleiner wrote:
> > On 08/18/2016 04:23 AM, Michel Dänzer wrote:
> >> On 18/08/16 01:12 AM, Mario Kleiner wrote:
> >
> > One thing that confuses
On 27/08/16 04:57 AM, Mario Kleiner wrote:
> On 08/18/2016 04:23 AM, Michel Dänzer wrote:
>> On 18/08/16 01:12 AM, Mario Kleiner wrote:
>
> One thing that confuses me so far is that visual results and measurment
> suggest it works nicely, properly serializing the rendering/detiling
> blit and the
On 27/08/16 05:07 AM, Mario Kleiner wrote:
> On 08/18/2016 04:32 AM, Michel Dänzer wrote:
>> On 18/08/16 08:51 AM, Mario Kleiner wrote:
>>>
>>> and the offload gpu imports those and renders into them. That saves
>>> one extra copy, so should be somewhat more efficient.
>>
>> Using two shared buffe
On 08/18/2016 09:21 PM, Marek Olšák wrote:
> On Thu, Aug 18, 2016 at 4:23 AM, Michel Dänzer wrote:
>> Maybe the rasterization as two triangles results in bad PCIe bandwidth
>> utilization. Using the asynchronous DMA engine for these transfers would
>> probably be ideal, but having the 3D engine
On 08/18/2016 04:32 AM, Michel Dänzer wrote:
> On 18/08/16 08:51 AM, Mario Kleiner wrote:
>>
>> That's what the ati-ddx/amdgpu-ddx does at the moment, as it detects the
>> mismatch in tiling flags and uses the DRI3/Present copy path instead of
>> the pageflip path. The problem is that the servers
To pick this up again after a week of manic testing :)
On 08/18/2016 04:23 AM, Michel Dänzer wrote:
> On 18/08/16 01:12 AM, Mario Kleiner wrote:
>>
>> Intel as display gpu + nouveau for render offload worked nicely
>> on intel-ddx with page flipping, proper timing, dmabuf fence sync
>> and all.
>
On Fri, Aug 26, 2016 at 4:10 PM, Mario Kleiner
wrote:
> On 08/18/2016 09:21 PM, Marek Olšák wrote:
>>
>> On Thu, Aug 18, 2016 at 4:23 AM, Michel Dänzer
>> wrote:
>>>
>>> Maybe the rasterization as two triangles results in bad PCIe bandwidth
>>> utilization. Using the asynchronous DMA engine f
On Thu, Aug 18, 2016 at 4:23 AM, Michel Dänzer wrote:
> Maybe the rasterization as two triangles results in bad PCIe bandwidth
> utilization. Using the asynchronous DMA engine for these transfers would
> probably be ideal, but having the 3D engine rasterize a single rectangle
> (either using the
On 18/08/16 05:20 PM, Christian König wrote:
> Am 18.08.2016 um 09:52 schrieb Michel Dänzer:
>> On 18/08/16 04:41 PM, Christian König wrote:
Afaiu the prime importing display gpu generates its own gem buffer
handle (prime_fd_to_handle) from that dmabuf, importing scather-gather
ta
On 18/08/16 04:41 PM, Christian König wrote:
>> Afaiu the prime importing display gpu generates its own gem buffer
>> handle (prime_fd_to_handle) from that dmabuf, importing scather-gather
>> tables to access the dmabuf in system ram. As far as page flipping is
>> concerned, so far those gem buffe
On 18/08/16 08:51 AM, Mario Kleiner wrote:
>
> That's what the ati-ddx/amdgpu-ddx does at the moment, as it detects the
> mismatch in tiling flags and uses the DRI3/Present copy path instead of
> the pageflip path. The problem is that the servers Present
> implementation doesn't request a vsync'ed
On 18/08/16 01:12 AM, Mario Kleiner wrote:
>
> Intel as display gpu + nouveau for render offload worked nicely
> on intel-ddx with page flipping, proper timing, dmabuf fence sync
> and all.
How about with AMD instead of nouveau in this case?
> Turns out that prime + page flipping currently does
Am 18.08.2016 um 09:52 schrieb Michel Dänzer:
> On 18/08/16 04:41 PM, Christian König wrote:
>>> Afaiu the prime importing display gpu generates its own gem buffer
>>> handle (prime_fd_to_handle) from that dmabuf, importing scather-gather
>>> tables to access the dmabuf in system ram. As far as p
Am 18.08.2016 um 04:32 schrieb Michel Dänzer:
> On 18/08/16 08:51 AM, Mario Kleiner wrote:
>> There is this other approach from NVidia's Alex Goins for their
>> proprietary driver, whose patches landed in the X-Server 1.19 master
>> branch a couple of weeks ago. I haven't read his patches in detai
> Afaiu the prime importing display gpu generates its own gem buffer
> handle (prime_fd_to_handle) from that dmabuf, importing scather-gather
> tables to access the dmabuf in system ram. As far as page flipping is
> concerned, so far those gem buffers / radeon_bo's aren't treated any
> differen
On 08/17/2016 07:43 PM, Alex Deucher wrote:
> On Wed, Aug 17, 2016 at 12:35 PM, Mario Kleiner
> wrote:
>> On 08/17/2016 06:27 PM, Christian König wrote:
AMD uses copy swaps because radeon/amdgpu kms can't switch the
scanout mode from tiled to linear on the fly during flips.
>>>
>>>
On 08/17/2016 07:02 PM, Christian König wrote:
> Am 17.08.2016 um 18:35 schrieb Mario Kleiner:
>> On 08/17/2016 06:27 PM, Christian König wrote:
AMD uses copy swaps because radeon/amdgpu kms can't switch the
scanout mode from tiled to linear on the fly during flips.
>>> Well I'm not an
Am 17.08.2016 um 18:35 schrieb Mario Kleiner:
> On 08/17/2016 06:27 PM, Christian König wrote:
>>> AMD uses copy swaps because radeon/amdgpu kms can't switch the
>>> scanout mode from tiled to linear on the fly during flips.
>> Well I'm not an expert on this, but as far as I know the bigger proble
On 08/17/2016 06:27 PM, Christian König wrote:
>> AMD uses copy swaps because radeon/amdgpu kms can't switch the
>> scanout mode from tiled to linear on the fly during flips.
> Well I'm not an expert on this, but as far as I know the bigger problem
> is that the dedicated AMD hardware generations
> AMD uses copy swaps because radeon/amdgpu kms can't switch the
> scanout mode from tiled to linear on the fly during flips.
Well I'm not an expert on this, but as far as I know the bigger problem
is that the dedicated AMD hardware generations you are targeting usually
can't reliable scanout fro
Hi,
i spent some time playing with DRI3/Present + PRIME for testing
how well it works for Optimus/Enduro style setups wrt. page flipping
on the current kernel/mesa/xorg. I want page flipping, because
neuroscience/medical applications need the reliable timing/timestamping
and tear free presentation
On Wed, Aug 17, 2016 at 12:35 PM, Mario Kleiner
wrote:
> On 08/17/2016 06:27 PM, Christian König wrote:
>>>
>>> AMD uses copy swaps because radeon/amdgpu kms can't switch the
>>> scanout mode from tiled to linear on the fly during flips.
>>
>> Well I'm not an expert on this, but as far as I know
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