I just came across a DMAR allocation issue when I wanted to use the UDL
driver with a DL-165 chipset and had the Intel IOMMU enabled.
It seems like it could be solved with the same patch already applied to
the EVDI driver:
https://github.com/DisplayLink/evdi/commit/74e289906dba95c0ad3208cfa6a5
Hi,
>>> On 24 July 2017 at 14:56, Volker Vogelhuber >>>
wrote: >>>> I wonder if it is
possible to have drmModeAddFB2 to handle >>>> 'X', 'R', '3', '0' at all.
So is this supported in any way? >>>
Hi,
On 24 July 2017 at 14:56, Volker Vogelhuber
wrote:
I wonder if it is possible to have drmModeAddFB2 to handle
'X', 'R', '3', '0' at all. So is this supported in any way?
Secondly, you're correct that you would need (theoretically) to
I have implemented a display manager application that takes DMB-BUF FDs
from another process and presents them to a connected output display
using the KMS infrastructure (drmModeAddFB, etc.). So far this works
without problems for XRGB. Now I wanted to have 10bit color depth
per channel. I cre
I'm currently trying to render an V4L2 image with OpenGL
on an Intel Apollo Lake using Linux 4.10 and Mesa 13.
Supprisingly I noticed that importing a DMABUF with format
DRM_FORMAT_YUYV into OpenGL using
eglCreateImage/glEGLImageTargetTexture2DOES
worked out of the box. But I noticed that there s
On Thu, Feb 02, 2017 at 05:19:58PM +0100, Volker Vogelhuber wrote:
>> I'm currently trying to mmap the memory of an OpenGL texture I've created by
>> doing the following:
>>
>> std::vector image_attribs = {
>> EGL_WIDTH,
Hi,
I'm currently trying to mmap the memory of an OpenGL texture I've
created by
doing the following:
std::vector image_attribs = {
EGL_WIDTH, static_cast(m_texWidth & 0x7FFF),
EGL_HEIGHT, static_cast(m_texHeight & 0x7FFF),
EGL_DRM_BUFFE
On 05.05.2015 17:51, Daniel Vetter wrote:
> On Tue, May 05, 2015 at 09:42:44AM +0200, Volker Vogelhuber wrote:
>> The documentation of the DMA-API writes the following about
>> dma_map_sg:
>>
>> "The implementation is free to merge several consecutive sglist
The documentation of the DMA-API writes the following about
dma_map_sg:
"The implementation is free to merge several consecutive sglist entries
into one (e.g. if DMA mapping is done with PAGE_SIZE granularity, any
consecutive sglist entries can be merged into one provided the first one
ends and th
I'm still fighting with the zero copy rendering of graphics data sent by
an FPGA to my system memory.
Basically what I've done so far is writing a kernel module based on TI's
CMEM only simpler, reserving
memory for that module during boot up using kernel command line parameter
memmap=256M$0x6
I just stumbled across the same problem the patch from Tomasz
Stanislawski (https://lkml.org/lkml/2012/8/8/163) would solve over two
years ago. But it seems like it hasn't been merged into mainline. Why
not? Is there any other possibility to avoid modules being released
while other modules stil
On 23.02.2015 10:18, Daniel Vetter wrote:
> On Mon, Feb 23, 2015 at 09:22:56AM +0100, Volker Vogelhuber wrote:
>> On 22.02.2015 12:52, Daniel Vetter wrote:
>>> On Mon, Feb 16, 2015 at 01:43:07PM +0100, Volker Vogelhuber wrote:
>>>> I'm currently trying to
On 22.02.2015 12:52, Daniel Vetter wrote:
> On Mon, Feb 16, 2015 at 01:43:07PM +0100, Volker Vogelhuber wrote:
>> I'm currently trying to setup a rendering pipe on an Intel Baytrail E3845
>> cpu.
>> In our product we want to have an FPGA streaming video images to a
>&
I'm currently trying to setup a rendering pipe on an Intel Baytrail
E3845 cpu.
In our product we want to have an FPGA streaming video images to a
predefined memory area using bus master dma and render those images
using OpenGL. So far this works in a preliminary state.
We now have the security r
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