[PATCH v2] drm/ast: Add option to initialize palette on driver load

Non-x86 systems, such as OpenPOWER and ARM machines, do not execute the ASPEED- provided option ROM on system start. As a result, the VGA palette registers remain uninitialized, leading to odd colors and generally hard to read output on the VGA port. Add a new module option, ast_resetpalette, to

[PATCH v2] drm/ast: Add option to initialize palette on driver load

enable loading a linear greyscale palette into the VGA RAMDAC. This option is intended for use by the first Linux kernel to load after initial power on, such as the skiroot kernel on OpenPOWER systems. Signed-off-by: Timothy Pearson --- drivers/gpu/drm/ast/ast_drv.c | 4 drivers/gpu/drm

[PATCH] drm/ast: Add option to initialize palette on driver load

loading a linear greyscale palette into the VGA RAMDAC. This option is intended for use by the first Linux kernel to load after initial power on, such as the skiroot kernel on OpenPOWER systems. Signed-off-by: Timothy Pearson --- drivers/gpu/drm/ast/ast_drv.c | 4 drivers/gpu/drm/ast

[PATCH] drm/ast: Fix incorrect memory size detection with analog VGA

KGPE-D16 (AST2050) w/ 8MB VRAM. Signed-off-by: Timothy Pearson --- drivers/gpu/drm/ast/ast_main.c | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 7bc3aa6..090b571 100644 --- a

[PATCH] drm/ast: Fix incorrect register check for DRAM width

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 02/26/2016 03:29 PM, Timothy Pearson wrote: > During DRAM initialization on certain ASpeed devices, an incorrect > bit (bit 10) was checked in the "SDRAM Bus Width Status" register > to determine DRAM width. > > Query bi

[PATCH] drm/ast: Fix incorrect register check for DRAM width

During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Signed-off-by: Timothy Pearson --- drivers/g

[PATCH] drm/ast: Fix incorrect register check for DRAM width

During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Signed-off-by: Timothy Pearson --- drivers/g