On 27-Sep-23 8:52 PM, Imre Deak wrote:
On Fri, Sep 22, 2023 at 03:45:45PM +0300, Imre Deak wrote:
Hi Mitul, Ankit, Swati, Vandita,
On Wed, Sep 13, 2023 at 11:35:58AM +0530, Mitul Golani wrote:
his patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some
On 21-Sep-23 5:44 PM, Jani Nikula wrote:
On Thu, 21 Sep 2023, "Sharma, Swati2" wrote:
On 21-Sep-23 1:30 PM, Jani Nikula wrote:
On Wed, 13 Sep 2023, Mitul Golani wrote:
From: Swati Sharma
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's
On 21-Sep-23 1:30 PM, Jani Nikula wrote:
On Wed, 13 Sep 2023, Mitul Golani wrote:
From: Swati Sharma
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is s
On 31-Jan-20 4:50 PM, Ville Syrjälä wrote:
On Thu, Jan 30, 2020 at 08:07:07PM +, Souza, Jose wrote:
On Thu, 2020-01-30 at 19:25 +0200, Ville Syrjälä wrote:
On Thu, Jan 16, 2020 at 05:58:37PM -0800, José Roberto de Souza
wrote:
TGL timeouts when disabling MST transcoder and fifo underruns
Hi Ville,
Can you please rebase the series? There are intel_de_write()
changes in existing code.
On 07-Nov-19 8:47 PM, Ville Syrjala wrote:
From: Ville Syrjälä
It irks me to use crtc_state_is_legacy_gamma() inside the guts
of the CHV color management code. Let's get rid of it and instead
just
On 15-Mar-19 3:17 PM, Nikula, Jani wrote:
On Fri, 15 Mar 2019, swati2.sha...@intel.com wrote:
From: Swati Sharma
Added state checker to validate gamma_lut values. This
reads hardware state, and compares the originally requested
state to the state read from hardware.
This implementation can be
On 15-Feb-19 2:12 AM, Juha-Pekka Heikkilä wrote:
Swati Sharma kirjoitti 13.2.2019 klo 15.25:
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.
Y210: For each
On 11-Jan-19 6:17 PM, Juha-Pekka Heikkila wrote:
On 11.1.2019 7.30, swati2.sha...@intel.com wrote:
From: Swati Sharma
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies
On 16-Aug-18 9:21 PM, Maarten Lankhorst wrote:
Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
Enabling of P010, P012 and P016 formats. These formats will
extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_
On 16-Aug-18 6:25 PM, Juha-Pekka Heikkila wrote:
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_atomic.c | 3 +-
drivers/gpu/
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