On 30/04/2025 14:35, Christian König wrote:
On 4/30/25 11:28, Sharma, Shashank wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
Hello Dan,
*From:* Dan Carpenter
*Sent:* Wednesday, April 30, 2025
On 30/04/2025 11:49, Dan Carpenter wrote:
On Wed, Apr 30, 2025 at 09:28:59AM +, Sharma, Shashank wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
Hello Dan,
From: Dan Carpenter
Sent: Wednesday, April 30, 2025 10:05 AM
To: Deucher
[AMD Official Use Only - AMD Internal Distribution Only]
Hello Dan,
From: Dan Carpenter
Sent: Wednesday, April 30, 2025 10:05 AM
To: Deucher, Alexander
Cc: Koenig, Christian; David Airlie; Simona Vetter; Sharma, Shashank; Khatri,
Sunil; Yadav, Arvind; Paneer
list; Sharma, Shashank
Cc: Deucher, Alexander; Pichika, UdayKiran (Uday Kiran); PV, SRIHARSHA;
Swarnakar, Praful; Wentland, Harry
Subject: Re: Introducing AMDGPU Composition Stack (ACS)
Hello,
Do you plan to migrate some of the GPU-Open repos to this Gitlab org ? Or is it
for a very distant
[AMD Official Use Only - AMD Internal Distribution Only]
Introducing AMDGPU Composition Stack (ACS).
ACS is simply AMD's fork of Weston compositor, with some additional advanced
features. We have created ACS considering the following primary goals in mind:
* To act as a staging area for Wayl
Lgtm, Reviewed-by: Shashank Sharma
Regards
Shashank
On 01/01/2025 02:58, Lu Yao wrote:
This patch add null pointer check for amdgpu_vm_put_task_info and
amdgpu_vm_get_task_info_vm, because there is only a warning if create
task_info failed in amdgpu_vm_init.
Fixes: b8f67b9ddf4f ("drm/amdgpu
Jadav ;
airl...@gmail.com ; sim...@ffwll.ch ;
lucas.demar...@intel.com ; rodrigo.v...@intel.com
; jani.nik...@linux.intel.com
; andriy.shevche...@linux.intel.com
; l...@asahilina.net ;
michal.wajdec...@intel.com ; Sharma, Shashank
Cc: intel-...@lists.freedesktop.org ;
dri-
Hey Christian,
On 19/08/2024 13:21, Christian König wrote:
Am 19.08.24 um 09:21 schrieb Friedrich Vock:
In Vulkan, it is the application's responsibility to perform adequate
synchronization before a sparse unmap, replace or BO destroy operation.
This adds an option to AMDGPU_VA_OPs to disable r
Thanks for the patch,
Patch pushed for staging.
Regards
Shashank
On 25/03/2024 00:23, Alex Deucher wrote:
On Sat, Mar 23, 2024 at 4:47 PM Sharma, Shashank
wrote:
On 23/03/2024 15:52, Johannes Weiner wrote:
On Thu, Mar 14, 2024 at 01:09:57PM -0400, Johannes Weiner wrote:
Hello,
On Fri
[AMD Official Use Only - General]
Hey Alex,
Sure, I will pick it up and push it to staging.
Regards
Shashank
From: Alex Deucher
Sent: Monday, March 25, 2024 12:23 AM
To: Sharma, Shashank
Cc: Johannes Weiner ; Christian König
; Deucher, Alexander
; Koenig
On 23/03/2024 15:52, Johannes Weiner wrote:
On Thu, Mar 14, 2024 at 01:09:57PM -0400, Johannes Weiner wrote:
Hello,
On Fri, Mar 08, 2024 at 12:32:33PM +0100, Christian König wrote:
Am 07.03.24 um 23:07 schrieb Johannes Weiner:
Lastly I went with an open loop instead of a memcpy() as I wasn'
+ Johannes
Regards
Shashank
On 13/03/2024 18:22, Sharma, Shashank wrote:
Hello Johannes,
On 07/03/2024 23:07, Johannes Weiner wrote:
An errant disk backup on my desktop got into debugfs and triggered the
following deadlock scenario in the amdgpu debugfs files. The machine
also hard-resets
On 14/03/2024 06:58, Khatri, Sunil wrote:
On 3/14/2024 2:06 AM, Alex Deucher wrote:
On Tue, Mar 12, 2024 at 8:42 AM Sunil Khatri
wrote:
Add firmware version information of each
IP and each instance where applicable.
Is there a way we can share some common code with devcoredump,
debugfs, a
+ /*
+* Copy to local buffer to avoid put_user(), which might fault
+* and acquire mmap_sem, under reservation_ww_class_mutex.
+*/
+ for (i = 0; i < ring->mqd_size/sizeof(u32); i++)
+ kbuf[i] = mqd[i];
memcpy is safe to use here.
With that change, please feel free
[AMD Official Use Only - General]
Reviewed-by: Shashank Sharma
Regards
Shashank
-Original Message-
From: Icenowy Zheng
Sent: Sunday, October 8, 2023 8:47 AM
To: Deucher, Alexander ; Koenig, Christian
; Pan, Xinhui ; David Airlie
; Daniel Vetter ; Sharma, Shashank
; Yadav, Arvind
Cc
-...@lists.freedesktop.org; linux-ker...@vger.kernel.org; Sharma, Shashank
Cc: kernel-...@igalia.com; Deucher, Alexander ;
Pelloux-Prayer, Pierre-Eric
Subject: Re: [PATCH v6 1/5] drm/amdgpu: Allocate coredump memory in a
nonblocking way
Am 11.09.23 um 05:00 schrieb André Almeida:
> During a GPU reset, a normal mem
[AMD Official Use Only - General]
Hey Christian,
Will do that.
Regards
Shashank
-Original Message-
From: Koenig, Christian
Sent: Monday, September 11, 2023 1:15 PM
To: André Almeida ; dri-devel@lists.freedesktop.org;
amd-...@lists.freedesktop.org; linux-ker...@vger.kernel.org; Sharma
; Daniel Vetter
; Sharma, Shashank ;
amd-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
Subject: [PATCH 11/20] drm/amd/amdgpu/amdgpu_doorbell_mgr: Correct
misdocumented param 'doorbell_index'
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/
[AMD Official Use Only - General]
+ Uday, for awareness.
Regards
Shashank
-Original Message-
From: Pekka Paalanen
Sent: 14 February 2023 10:28
To: Melissa Wen
Cc: Ville Syrjälä ;
dri-devel@lists.freedesktop.org; airl...@gmail.com;
laurent.pinchart+rene...@ideasonboard.com; Sharma
-devel
; Sharma, Shashank
Subject: Re: Amdgpu module is references even after unbinding the vtcon
Hi Danijel,
can you also double check that GDM/X is still capable of acquiring a DMA-buf
file descriptor for the buffer (e.g. that we have a DMA-buf handle for it while
they are started).
And
On 8/8/2022 12:59 PM, Christian König wrote:
Am 02.08.22 um 15:55 schrieb Shashank Sharma:
This patch adds:
- A new input parameter "flags" in the amdgpu_ctx_create2 call.
- Some new flags defining workload type hints.
- Some change in the caller function of amdgpu_ctx_create2, to
accomoda
On 8/2/2022 5:58 PM, Michel Dänzer wrote:
On 2022-08-02 15:55, Shashank Sharma wrote:
This patch adds:
- A new input parameter "flags" in the amdgpu_ctx_create2 call.
- Some new flags defining workload type hints.
- Some change in the caller function of amdgpu_ctx_create2, to
accomodate this
Acked-by: Shashank Sharma
Regards
Shashank
-Original Message-
From: dri-devel On Behalf Of
Christian König
Sent: Thursday, April 7, 2022 1:46 PM
To: pet...@infradead.org; daniel.vet...@ffwll.ch;
dri-devel@lists.freedesktop.org
Cc: Koenig, Christian
Subject: [PATCH] futex: add missing
On 3/16/2022 10:50 PM, Rob Clark wrote:
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
wrote:
From: Shashank Sharma
This patch adds a new sysfs event, which will indicate
the userland about a GPU reset, and can also provide
some information like:
- process ID of the process involved with
On 3/10/2022 8:56 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 11:44 AM Sharma, Shashank
wrote:
On 3/10/2022 8:35 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 11:14 AM Sharma, Shashank
wrote:
On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
On 3/10/2022 9:40 AM, Rob Clark wrote:
On
On 3/10/2022 8:35 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 11:14 AM Sharma, Shashank
wrote:
On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
On 3/10/2022 9:40 AM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
wrote:
On 3/10/2022 6:10 PM, Rob Clark wrote:
On
On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
On 3/10/2022 9:40 AM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
wrote:
On 3/10/2022 6:10 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
wrote:
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu
On 3/10/2022 6:10 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
wrote:
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 1:55 AM Christian König
wrote:
Am 09.03.22 um 19:12 schrieb Rob Clark:
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 1:55 AM Christian König
wrote:
Am 09.03.22 um 19:12 schrieb Rob Clark:
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
wrote:
From: Shashank Sharma
This patch adds a new sysfs event, which will indicate
the userland about
On 3/9/2022 8:47 AM, Simon Ser wrote:
Hi,
Maybe it would be a good idea to state the intended use-case in the
commit message?
It was added in the second patch, but yeah, it makes more sense to add a
cover-letter probably.
And explain why the current (driver-specific IIRC) APIs
aren't e
Hello Brian,
(+Uma in cc)
Thanks for your comments, Let me try to fill-in for Harry to keep the
design discussion going. Please find my comments inline.
On 8/2/2021 10:00 PM, Brian Starkey wrote:
Hi,
Thanks for having a stab at this, it's a massive complex topic to
solve.
Do you have the th
Hello Harry,
Thanks for your comments, please find mine inline.
On 10/22/2019 7:36 PM, Harry Wentland wrote:
On 2019-10-22 8:20 a.m., Ville Syrjälä wrote:
On Tue, Oct 22, 2019 at 03:29:44PM +0530, Shashank Sharma wrote:
This patch adds a scaling filter mode porperty
to allow:
- A driver/HW t
Hello Mihail,
Thanks for your review, my comments inline.
On 10/22/2019 6:56 PM, Mihail Atanassov wrote:
Hi Shashank,
On Tuesday, 22 October 2019 10:59:44 BST Shashank Sharma wrote:
This patch adds a scaling filter mode porperty
to allow:
- A driver/HW to showcase it's scaling filter capabili
On 10/22/2019 5:56 PM, Ville Syrjälä wrote:
On Tue, Oct 22, 2019 at 03:29:44PM +0530, Shashank Sharma wrote:
This patch adds a scaling filter mode porperty
to allow:
- A driver/HW to showcase it's scaling filter capabilities.
- A userspace to pick a desired effect while scaling.
This option wi
Hello Ville,
Thanks for the comments, mine inline.
On 10/22/2019 5:50 PM, Ville Syrjälä wrote:
On Tue, Oct 22, 2019 at 03:29:44PM +0530, Shashank Sharma wrote:
This patch adds a scaling filter mode porperty
to allow:
- A driver/HW to showcase it's scaling filter capabilities.
- A userspace to
Hey Daniel,
> -Original Message-
> From: Daniel Vetter On Behalf Of Daniel Vetter
> Sent: Tuesday, October 22, 2019 3:39 PM
> To: Sharma, Shashank
> Cc: dri-devel@lists.freedesktop.org; intel-...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/3] drm: Introd
On 9/25/2019 7:25 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Now that the cea mode handling is not 100% tied to the single
array the dummy VIC 0 mode is pretty much pointles. Throw it
out.
Cc: Hans Verkuil
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c
On 9/25/2019 7:25 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Add a second table to the cea modes with VIC >= 193.
Cc: Hans Verkuil
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 151 -
1 file changed, 149 insertion
Hello Ville,
On 9/25/2019 7:24 PM, Ville Syrjala wrote:
From: Ville Syrjälä
We're going to need two cea mode tables (on for VICs < 128,
another one for VICs >= 193). To that end replace the direct
edid_cea_modes[] lookups with a function call. And we'll rename
the array to edid_cea_modes_0[] t
Looks good to me,
From display side, Please feel free to use Reviewed-by: Shashank Sharma
Regards
Shashank
> -Original Message-
> From: Winkler, Tomas
> Sent: Wednesday, August 28, 2019 1:49 PM
> To: C, Ramalingam
> Cc: intel-gfx ; dri-devel de...@lists.freedeskt
Looks good to me,
From display side, Please feel free to use Reviewed-by: Shashank Sharma
> -Original Message-
> From: C, Ramalingam
> Sent: Wednesday, August 28, 2019 2:28 PM
> To: Winkler, Tomas
> Cc: intel-gfx ; dri-devel de...@lists.freedesktop.org>; Sharma, S
Regards
Shashank
On 8/22/2019 8:49 PM, Ramalingam C wrote:
From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
As ME FW needs the transcoder detail on which HDCP is enabled
on
Regards
Shashank
On 8/27/2019 10:57 AM, Ramalingam C wrote:
On 2019-08-27 at 10:49:25 +0530, Sharma, Shashank wrote:
Regards
Shashank
On 8/22/2019 8:49 PM, Ramalingam C wrote:
On gen12+ platforms, HDCP HW is associated to the transcoder.
Hence on every modeset update associated transcoder
On 8/27/2019 10:47 AM, Ramalingam C wrote:
On 2019-08-27 at 10:42:33 +0530, Sharma, Shashank wrote:
Regards
Shashank
On 8/22/2019 8:49 PM, Ramalingam C wrote:
For gen12+ platform we need to pass the transcoder info
as part of the port info into ME FW.
This change fills the payload for ME
Regards
Shashank
On 8/22/2019 8:49 PM, Ramalingam C wrote:
On gen12+ platforms, HDCP HW is associated to the transcoder.
Hence on every modeset update associated transcoder into the
intel_hdcp of the port.
v2:
s/trans/cpu_transcoder [Jani]
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
Regards
Shashank
On 8/22/2019 8:49 PM, Ramalingam C wrote:
For gen12+ platform we need to pass the transcoder info
as part of the port info into ME FW.
This change fills the payload for ME FW from hdcp_port_data.
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
---
drivers/misc/mei/hdcp/
On 8/22/2019 8:49 PM, Ramalingam C wrote:
I915 needs to send the index of the transcoder as per ME FW.
To support this, define enum mei_fw_ddi and add as a member into
the struct hdcp_port_data.
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
---
include/drm/i915_mei_hdcp_interface.h | 13
On 8/22/2019 8:49 PM, Ramalingam C wrote:
I915 needs to send the index of the transcoder as per ME FW.
To support this, define enum mei_fw_ddi and add as a member into
the struct hdcp_port_data.
The commit message says you are defining enum mei_fw_ddi, but you are
actually defining enum mei_f
Regards
Shashank
On 8/27/2019 10:03 AM, Ramalingam C wrote:
On 2019-08-27 at 09:54:18 +0530, Sharma, Shashank wrote:
Hello Ram,
On 8/22/2019 8:48 PM, Ramalingam C wrote:
I915 converts it's port value into ddi index defiend by ME FW
and pass it as a member of hdcp_port_data structure.
efine port_name(p) ((p) + 'A')
-
#endif/* _I915_DRM_H_ */
Otherwise patch looks good to me.
With(or without) above mentioned suggestion, Feel free to use:
Reviewed-by: Shashank Sharma
- Shashank
___
dri-devel
Hello Ram,
On 8/22/2019 8:48 PM, Ramalingam C wrote:
I915 converts it's port value into ddi index defiend by ME FW
and pass it as a member of hdcp_port_data structure.
Hence expose the enum mei_fw_ddi to I915 through
i915_mei_interface.h.
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
---
Hi Ram,
Just a minor nitpick.
Regards
Shashank
> -Original Message-
> From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
> Ramalingam C
> Sent: Friday, July 12, 2019 12:30 PM
> To: intel-gfx ; dri-devel de...@lists.freedesktop.org>; Pekka Paalanen ; Daniel
> V
Hi Ville,
On 7/11/2019 4:02 PM, Ville Syrjala wrote:
From: Ville Syrjälä
We're going to need two cea mode tables (on for VICs < 128,
another one for VICs >= 193). To that end replace the direct
edid_cea_modes[] lookups with a function call. And we'll rename
the array to edid_cea_modes_0[] to i
ASPECT_64_27, },
+ /* 127 - 5120x2160@100Hz 64:27 */
+ { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
+ 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 100, .picture_aspect_ratio = HDMI_PICT
On 4/15/2019 7:42 PM, Lankhorst, Maarten wrote:
mån 2019-04-15 klockan 19:26 +0530 skrev Sharma, Shashank:
-Original Message-
From: Lankhorst, Maarten
Sent: Monday, April 15, 2019 4:28 PM
To: Shankar, Uma ; intel-gfx@lists.freedeskt
op.org; dri-
de...@lists.freedesktop.org
Cc: Syrjala
per, Matthew D ;
> seanp...@chromium.org; brian.star...@arm.com; dcasta...@chromium.org;
> Sharma, Shashank
> Subject: Re: [v3 6/7] drm: Add Client Cap for advance gamma mode
>
> fre 2019-04-12 klockan 15:51 +0530 skrev Uma Shankar:
> > Introduced a client cap for advance cap mode
>
Hello Uma,
V7 looks good to me, please feel free to use for the whole series:
Reviewed-by: Shashank Sharma
Regards
Shashank
On 4/3/2019 1:50 AM, Uma Shankar wrote:
This patch series enables HDR support in drm. It basically defines
HDR metadata structures, property to pass content (after ble
On 3/20/2019 4:18 PM, Uma Shankar wrote:
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 15 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 4
2 fil
On 3/20/2019 4:18 PM, Uma Shankar wrote:
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
v2: Addressed Shashank's review comment.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++
_infoframe *frame);
enum hdmi_spd_sdi {
HDMI_SPD_SDI_UNKNOWN,
With that minor comment related to description fixed, this patch looks
good to me. Please feel free to use:
Reviewed-by: Shashank Sharma
- Shashank
___
dri-devel mailing list
dri-devel@lists.fre
On 3/20/2019 4:18 PM, Uma Shankar wrote:
HDR metadata requires a infoframe to be set. Due to fastset,
full modeset is not performed hence adding it to update_pipe
to handle that.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_ddi.c | 13 +
1 file changed, 13 insertions
On 3/20/2019 4:18 PM, Uma Shankar wrote:
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comme
On 3/20/2019 4:18 PM, Uma Shankar wrote:
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
v3: No Change
v4: Addressed Shashank's review comments
Signed-off-by: Uma Shankar
---
drive
On 3/20/2019 12:47 PM, Shankar, Uma wrote:
-Original Message-
From: Sharma, Shashank
Sent: Friday, March 15, 2019 1:01 PM
To: Shankar, Uma ; intel-...@lists.freedesktop.org; dri-
de...@lists.freedesktop.org
Cc: Lankhorst, Maarten ; Syrjala, Ville
; emil.l.veli...@gmail.com; brian.star
On 3/11/2019 9:28 AM, Uma Shankar wrote:
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions supported.
Hybrid Log-Gamma (HLG) is a high dynamic range (HDR) standard.
HLG defines a nonlinear transfer function in which the lower
half of the signal values use a gamma curve an
On 3/11/2019 9:27 AM, Uma Shankar wrote:
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comme
size_t size);
ssize_t hdmi_avi_infoframe_pack_only(const struct hdmi_avi_infoframe *frame,
void *buffer, size_t size);
int hdmi_avi_infoframe_check(struct hdmi_avi_infoframe *frame);
+int hdmi_drm_infoframe_init(struct hdmi_drm
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star...@arm.com
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star...@arm.com
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star...@arm.com
Hello Uma,
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star
Regards
Shashank
On 2/8/2019 7:00 PM, Ville Syrjälä wrote:
On Fri, Feb 08, 2019 at 06:36:39PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 2/8/2019 6:22 PM, Ville Syrjälä wrote:
On Fri, Feb 08, 2019 at 12:36:25PM +, Sharma, Shashank wrote:
Regards
Shashank
-Original
Regards
Shashank
On 2/8/2019 6:22 PM, Ville Syrjälä wrote:
On Fri, Feb 08, 2019 at 12:36:25PM +, Sharma, Shashank wrote:
Regards
Shashank
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Shankar, Uma
Sent: Friday, February 8, 2019
Regards
Shashank
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Shankar, Uma
> Sent: Friday, February 8, 2019 5:45 PM
> To: Ville Syrjälä
> Cc: intel-...@lists.freedesktop.org; Syrjala, Ville
> ; dri-
> de...@lists.freedesktop.org;
Hello Ville,
On 1/29/2019 9:33 PM, Ville Syrjälä wrote:
On Tue, Jan 29, 2019 at 03:57:29PM +, Shankar, Uma wrote:
-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
Ville Syrjälä
Sent: Tuesday, January 29, 2019 9:14 PM
To: Shankar, U
On 1/8/2019 12:10 PM, Shankar, Uma wrote:
-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
Sharma, Shashank
Sent: Thursday, December 20, 2018 11:54 PM
To: Shankar, Uma ; intel-...@lists.freedesktop.org;
dri-devel@lists.freedesktop.org
Regards
Shashank
On 1/8/2019 11:10 AM, Shankar, Uma wrote:
-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
Sharma, Shashank
Sent: Thursday, December 20, 2018 11:47 PM
To: Shankar, Uma ; intel-...@lists.freedesktop.org;
dri-devel
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
From: Ville Syrjälä
Function argument for hdmi_drm_infoframe_log is made constant.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i9
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions
supported.
Would it be possible to add some details about HLG ?
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 4
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The s
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
HDR source metadata set and get property implemented in this
patch.
Again, HDR output metadata ? How about re-arranging the line like "This
patch implements get() and set() functions for HDR output metadata
property" just to make it
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
Attach HDR metadata property to connector object.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 24
include/drm/drm_c
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 45 ++
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
Add bit field and macro for extended tag in CEA block. Also,
declare macros for HDR metadata block.
This should have been a part of patch, where these macros are being
used, so that we can see it being used properly. While re-basing c
Regards
Shashank
On 12/12/2018 2:08 AM, Uma Shankar wrote:
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
v2: Rebase and modified the metadata structure elements
as per Ville's POC changes.
Signed-off-by: U
Regards
Shashank
On 12/11/2018 11:44 PM, Uma Shankar wrote:
This patch attaches the colorspace connector property to the
hdmi connector. Based on colorspace change, modeset will be
triggered to switch to new colorspace.
Based on colorspace property value create an infoframe
with appropriate c
Regards
Shashank
On 12/11/2018 11:44 PM, Uma Shankar wrote:
This patch adds a colorspace connector property, enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
th
Regards
Shashank
On 11/27/2018 10:10 PM, Uma Shankar wrote:
This patch adds a DP colorspace property, enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the
Regards
Shashank
On 11/27/2018 10:10 PM, Uma Shankar wrote:
This patch adds a HDMI colorspace property, enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the col
Regards
Shashank
On 10/31/2018 5:35 PM, Uma Shankar wrote:
This patch attaches the colorspace connector property to the
hdmi connector. Based on colorspace change, modeset will be
triggered to switch to new colorspace.
Based on colorspace property value create an infoframe
with appropriate co
Regards
Shashank
On 10/31/2018 5:35 PM, Uma Shankar wrote:
This patch adds a colorspace property enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the colorspace
Hello Uma,
My comments inline.
On 10/31/2018 5:35 PM, Uma Shankar wrote:
This patch series creates a new connector property to program
colorspace to sink devices. Modern sink devices support more
than 1 type of colorspace like 601, 709, BT2020 etc. This helps
to switch based on content type wh
sing of those before this block, keeping |= required.
But we can always do other way around, or will take care of it when we
add code for it.
Just cross checked with the spec too,
Reviewed-by: Shashank Sharma
- Shashank
PS. It'll be useful to repost this Cc: intel-gfx just to get the CI as
Reviewed-by: Shashank Sharma
Regards
Shashank
On 3/23/2018 11:55 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Since we may attempt to reconfigure SCDC when the sink has already been
disconnected we probably shouldn't scare the user with errors in dmesg
that are 100% expected in that case. Jus
Regards
Shashank
On 3/1/2018 6:54 PM, Ville Syrjälä wrote:
On Thu, Mar 01, 2018 at 06:43:21PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 2/24/2018 12:55 AM, Ville Syrjala wrote:
From: Ville Syrjälä
While we want to potentially support multiple different gamma/degamma
LUT sizes
Regards
Shashank
On 2/24/2018 12:55 AM, Ville Syrjala wrote:
From: Ville Syrjälä
While we want to potentially support multiple different gamma/degamma
LUT sizes we can (and should) at least check that the blob length
is a multiple of the LUT entry size.
I dint understand the exact idea behin
Regards
Shashank
On 2/24/2018 12:55 AM, Ville Syrjala wrote:
From: Ville Syrjälä
Now that blob->data is void* again we don't need the casts anymore.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c| 3 +--
drivers/gpu/drm/drm_atomic_helper.c | 2 +-
drivers/gpu/drm
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