[PATCH v3 1/6] dt-bindings: drm/msm/gpu: Document gpu opp table

Update documentation to list the gpu opp table bindings including the newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling. Signed-off-by: Sharat Masetty Acked-by: Rob Herring --- .../devicetree/bindings/display/msm/gpu.txt| 28 ++ 1 file c

[PATCH v3 3/6] drm: msm: a6xx: use dev_pm_opp_set_bw to scale DDR

-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 23 --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 drivers/gpu/drm/msm/msm_gpu.h | 2 -- 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c

[PATCH v3 4/6] arm64: dts: qcom: SDM845: Enable GPU DDR bw scaling

This patch adds the interconnects property for the gpu node and the opp-peak-kBps property to the opps of the gpu opp table. This should help enable DDR bandwidth scaling dynamically and proportionally to the GPU frequency. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sdm845.dtsi

[PATCH v3 5/6] arm64: dts: qcom: sc7180: Add interconnects property for GPU

This patch adds the interconnects property to the GPU node. This enables the GPU->DDR path bandwidth voting. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/

[PATCH v3 2/6] drm: msm: a6xx: send opp instead of a frequency

This patch changes the plumbing to send the devfreq recommended opp rather than the frequency. Also consolidate and rearrange the code in a6xx to set the GPU frequency and the icc vote in preparation for the upcoming changes for GPU->DDR scaling votes. Signed-off-by: Sharat Masetty --- driv

[PATCH v3 6/6] arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp

Add opp-peak-kBps bindings to the GPU opp table, listing the peak GPU -> DDR bandwidth requirement for each opp level. This will be used to scale the DDR bandwidth along with the GPU frequency dynamically. Signed-off-by: Sharat Masetty Reviewed-by: Matthias Kaehlcke --- arch/arm64/boot/

[PATCH v3 0/6] Add support for GPU DDR BW scaling

t for SDM845 as well but its not tested yet(WIP), but the SC7180 patches are well tested now. [1] https://patchwork.freedesktop.org/series/75291/ [2] https://kernel.googlesource.com/pub/scm/linux/kernel/git/vireshk/pm/+log/opp/linux-next/ [3] https://patchwork.kernel.org/patch/11590563/ Sharat Ma

Re: [Freedreno] [PATCH 5/6] drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth

On 5/27/2020 9:08 PM, Rob Clark wrote: On Wed, May 27, 2020 at 1:47 AM Sharat Masetty wrote: + more folks On 5/18/2020 9:55 PM, Rob Clark wrote: On Mon, May 18, 2020 at 7:23 AM Jordan Crouse wrote: On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote: This patches replaces the

Re: [Freedreno] [PATCH 5/6] drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth

+ more folks On 5/18/2020 9:55 PM, Rob Clark wrote: On Mon, May 18, 2020 at 7:23 AM Jordan Crouse wrote: On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote: This patches replaces the previously used static DDR vote and uses dev_pm_opp_set_bw() to scale GPU->DDR bandwidth al

[PATCH 4/6] drm: msm: a6xx: send opp instead of a frequency

This patch changes the plumbing to send the devfreq recommended opp rather than the frequency. Also consolidate and rearrange the code in a6xx to set the GPU frequency and the icc vote in preparation for the upcoming changes for GPU->DDR scaling votes. Signed-off-by: Sharat Masetty --- driv

[PATCH 5/6] drm: msm: a6xx: use dev_pm_opp_set_bw to set DDR bandwidth

This patches replaces the previously used static DDR vote and uses dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling GPU frequency. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --gi

[PATCH 2/6] arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp

Add opp-peak-kBps bindings to the GPU opp table, listing the peak GPU -> DDR bandwidth requirement for each opp level. This will be used to scale the DDR bandwidth along with the GPU frequency dynamically. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 +++

[PATCH 0/6] Add support for GPU DDR BW scaling

hwork/cover/1230626/ [3]: https://lore.kernel.org/patchwork/cover/1240687/ Sharat Masetty (5): arm64: dts: qcom: sc7180: Add interconnect bindings for GPU arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp drm: msm: a6xx: send opp instead of a frequency drm: msm: a6xx: use dev_pm_opp_set_

[PATCH 3/6] OPP: Add and export helper to set bandwidth

From: Sibi Sankar Add and export 'dev_pm_opp_set_bw' to set the bandwidth levels associated with an OPP for a given frequency. Signed-off-by: Sibi Sankar Signed-off-by: Sharat Masetty --- drivers/opp/core.c | 43 +++ include/linux/pm_

[PATCH 6/6] dt-bindings: drm/msm/gpu: Document gpu opp table

Update documentation to list the gpu opp table bindings including the newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling. Signed-off-by: Sharat Masetty --- .../devicetree/bindings/display/msm/gpu.txt| 28 ++ 1 file changed, 28 insertions(+)

[PATCH 1/6] arm64: dts: qcom: sc7180: Add interconnect bindings for GPU

This patch adds the interconnect bindings to the GPU node. This enables the GPU->DDR path bandwidth voting. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/

[PATCH 1/2] arm64: dts: qcom: sc7180: Add A618 gpu dt blob

This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty --- * Remove GCC_DDRSS_GPU_AXI_CLK clock reference from gpu smmu node. arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++ 1 file changed, 102 insertions(+) diff

[PATCH 2/2] dt-bindings: arm-smmu: Add sc7180 compatible string

This patch simply adds a new compatible string for SC7180 platform. Signed-off-by: Sharat Masetty --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree

Re: [Freedreno] [PATCH v2] dt-bindings: arm-smmu: Add sc7180 compatible string and mem_iface clock

On 4/30/2020 11:51 PM, Doug Anderson wrote: Hi, On Thu, Apr 30, 2020 at 11:12 AM Jordan Crouse wrote: On Thu, Apr 30, 2020 at 09:29:47AM +0530, Sharat Masetty wrote: This patch adds a new compatible string for sc7180 and also an additional clock listing needed to power the TBUs and the TCU

[PATCH v2] dt-bindings: arm-smmu: Add sc7180 compatible string and mem_iface clock

This patch adds a new compatible string for sc7180 and also an additional clock listing needed to power the TBUs and the TCU. Signed-off-by: Sharat Masetty --- v2: Addressed review comments from Doug Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 8 1 file changed, 8

Re: [PATCH] dt-bindings: arm-smmu: Add a new compatible string and a clock

On 4/29/2020 3:57 AM, Doug Anderson wrote: Hi, On Tue, Apr 28, 2020 at 4:39 AM Sharat Masetty wrote: This patch adds a new compatible string for sc7180 and also an additional clock listing needed to power the TBUs and the TCU. Signed-off-by: Sharat Masetty --- Documentation/devicetree

[PATCH] dt-bindings: arm-smmu: Add a new compatible string and a clock

This patch adds a new compatible string for sc7180 and also an additional clock listing needed to power the TBUs and the TCU. Signed-off-by: Sharat Masetty --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Documentation

Re: [PATCH 3/5] drm: msm: scale DDR BW along with GPU frequency

On 3/31/2020 10:56 PM, Jordan Crouse wrote: On Tue, Mar 31, 2020 at 01:25:51PM +0530, Sharat Masetty wrote: This patch adds support to parse the OPP tables attached the GPU device, the main opp table and the DDR bandwidth opp table. Additionally, vote for the GPU->DDR bandwidth when sett

[PATCH 3/5] drm: msm: scale DDR BW along with GPU frequency

This patch adds support to parse the OPP tables attached the GPU device, the main opp table and the DDR bandwidth opp table. Additionally, vote for the GPU->DDR bandwidth when setting the GPU frequency by querying the linked DDR BW opp to the GPU opp. Signed-off-by: Sharat Masetty --- driv

[PATCH 4/5] drm: msm: a6xx: Fix off by one error when setting GPU freq

This patch fixes an error in the for loop, thereby allowing search on the full list of possible GPU power levels. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b

[PATCH 5/5] dt-bindings: drm/msm/gpu: Document OPP phandle list for the GPU

Update the documentation for listing the multiple optional GPU and the DDR OPP tables to help enable DDR scaling. Signed-off-by: Sharat Masetty --- .../devicetree/bindings/display/msm/gpu.txt| 63 +- 1 file changed, 61 insertions(+), 2 deletions(-) diff --git a

[PATCH 1/5] arm64: dts: qcom: sc7180: Add interconnect bindings for GPU

This patch adds the interconnect bindings to the GPU node. This enables the GPU->DDR path bandwidth voting. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/

[PATCH 2/5] arm64: dts: qcom: sc7180: Add GPU DDR BW opp table

frequency. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 50 +++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 51630dd..74b023b 100644

[PATCH 0/5] Add support for GPU DDR BW scaling

iumos/third_party/kernel/+/2097039/3 Sharat Masetty (5): arm64: dts: qcom: sc7180: Add interconnect bindings for GPU arm64: dts: qcom: sc7180: Add GPU DDR BW opp table drm: msm: scale DDR BW along with GPU frequency drm: msm: a6xx: Fix off by one error when setting GPU freq dt-bindings: drm/ms

[PATCH] drm: msm: a6x: Disable interrupts before recovery

This patch disables interrupts in the GPU RBBM hang detect fault handler before going to recovery. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno

Re: [PATCH] dt-bindings: arm-smmu: update the list of clocks

On 2/26/2020 8:03 PM, Rob Herring wrote: On Wed, Feb 26, 2020 at 5:17 AM Sharat Masetty wrote: On 2/21/2020 2:05 AM, Rob Herring wrote: On Thu, 20 Feb 2020 13:42:22 +0530, Sharat Masetty wrote: This patch adds a clock definition needed for powering on the GPU TBUs and the GPU TCU. Signed

Re: [PATCH] dt-bindings: arm-smmu: update the list of clocks

On 2/21/2020 2:05 AM, Rob Herring wrote: On Thu, 20 Feb 2020 13:42:22 +0530, Sharat Masetty wrote: This patch adds a clock definition needed for powering on the GPU TBUs and the GPU TCU. Signed-off-by: Sharat Masetty --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ 1

Re: [PATCH v6] arm64: dts: qcom: sc7180: Add A618 gpu dt blob

On 2/11/2020 2:51 AM, Doug Anderson wrote: Hi, On Sun, Feb 9, 2020 at 11:41 PM Sharat Masetty wrote: This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty In v4 I added my tags [1]. Please keep them for future patches unless something

[PATCH] dt-bindings: arm-smmu: update the list of clocks

This patch adds a clock definition needed for powering on the GPU TBUs and the GPU TCU. Signed-off-by: Sharat Masetty --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b

[PATCH] Update arm,smmu.yaml bindings doc

Patch [1] adds a "mem_iface_clock" in the clocks list for smmu device. This patch updates the yaml doc file for smmu by adding the definition for this new clock. 1: https://patchwork.freedesktop.org/patch/352718/ Sharat Masetty (1): dt-bindings: arm-smmu: update clocks and bindings

[PATCH v6] sc7180: Add A618 GPU bindings

Rebased changes on top of Taniyas lastet post((e) in the list above) and adding back the GX_GDSC binding. Sharat Masetty (1): arm64: dts: qcom: sc7180: Add A618 gpu dt blob arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++ 1 file ch

[PATCH v6] arm64: dts: qcom: sc7180: Add A618 gpu dt blob

This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts

[PATCH v5] arm64: dts: qcom: sc7180: Add A618 gpu dt blob

This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts

[PATCH v5] sc7180: Add A618 GPU bindings

a new patch with its dependencies listed. Also I will be sending a new patch for updating the bindings documentation. v4: Add GX_GDSC power domain binding for GMU v5: Change to a dummy GX_GDSC binding for faster landing Sharat Masetty (1): arm64: dts: qcom: sc7180: Add A618 gpu dt blob ar

[PATCH v4 1/3] dt-bindings: clk: qcom: Add support for GPU GX GDSCR

From: Taniya Das In the cases where the GPU SW requires to use the GX GDSCR add support for the same. Signed-off-by: Taniya Das --- include/dt-bindings/clock/qcom,gpucc-sc7180.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/qcom,gpucc-sc7180.h

[PATCH v4 0/3] sc7180: Add A618 GPU bindings

a new patch with its dependencies listed. Also I will be sending a new patch for updating the bindings documentation. v4: Add GX_GDSC power domain binding for GMU Sharat Masetty (1): arm64: dts: qcom: sc7180: Add A618 gpu dt blob Taniya Das (2): dt-bindings: clk: qcom: Add support for GP

[PATCH v4 2/3] clk: qcom: gpucc: Add support for GX GDSC for SC7180

From: Taniya Das Most of the time the CPU should not be touching the GX domain on the GPU except for a very special use case when the CPU needs to force the GX headswitch off. Add a dummy enable function for the GX gdsc to simulate success so that the pm_runtime reference counting is correct

[PATCH v4 3/3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob

This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts

[PATCH v3] Add A618 GPU nodes

a new patch with its dependencies listed. Also I will be sending a new patch for updating the bindings documentation. Sharat Masetty (1): arm64: dts: qcom: sc7180: Add A618 gpu dt blob arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++ 1 file ch

[PATCH v3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob

This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts

[PATCH v2] arm64: dts: qcom: sc7180: Add A618 gpu dt blob

This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 103 +++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts

[PATCH v2 2/3] drm: msm: a6xx: Add support for A618

This patch adds support for enabling Graphics Bus Interface(GBIF) used in multiple A6xx series chipets. Also makes changes to the PDC/RSC sequencing specifically required for A618. This is needed for proper interfacing with RPMH. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno

[PATCH v2 3/3] drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state

Add the relevant GBIF registers and the debug bus to the a6xx gpu state. This comes in pretty handy when debugging GPU bus related issues. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52 +++-- drivers/gpu/drm/msm/adreno

[PATCH v2 1/3] drm: msm: Add 618 gpu to the adreno gpu list

This patch adds Adreno 618 entry and its associated properties to the gpulist entries. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm

[PATCH v2 3/7] drm/msm: Attach the IOMMU device during initialization

From: Jordan Crouse Everywhere an IOMMU object is created by msm_gpu_create_address_space the IOMMU device is attached immediately after. Instead of carrying around the infrastructure to do the attach from the device specific code do it directly in the msm_iommu_init() function. This gets it out

[PATCH v2 6/7] drm/msm: rearrange the gpu_rmw() function

The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function. Signed-off-by: Sharat Masetty Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c | 8

[PATCH v2 5/7] drm: msm: a6xx: Properly free up the iommu objects

This patch calls the right function to destroy the iommu domain as well as free the associated iommu structure there by facilitating proper clean up of resources upon failure of creating an address space. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file

[PATCH v2 4/7] drm/msm: Refactor address space initialization

initialization to allow for future extensions like supporting split pagetables. Signed-off-by: Jordan Crouse Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c| 16 ++ drivers/gpu/drm/msm/adreno/a3xx_gpu.c| 1 + drivers/gpu/drm/msm/adreno/a4xx_gpu.c| 1

[PATCH v2 7/7] drm/msm/a6xx: Add support for using system cache(LLC)

larly DOMAIN_ATTR_QCOM_SYS_CACHE is another domain level attribute used by the IOMMU driver to set the right attributes to cache the hardware pagetables into the system cache. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 100 ++ drivers/gpu/dr

[PATCH v2 1/7] iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context

From: Jordan Crouse Pass the propposed io_pgtable_cfg to the implementation specific init_context() function to give the implementation an opportunity to to modify it before it gets passed to io-pgtable. Signed-off-by: Jordan Crouse Signed-off-by: Sai Prakash Ranjan --- drivers/iommu/arm-smmu

[PATCH v2 2/7] iommu/arm-smmu: Add domain attribute for QCOM system cache

From: Vivek Gautam Add iommu domain attribute for using system cache aka last level cache on QCOM SoCs by client drivers like GPU to set right attributes for caching the hardware pagetables into the system cache. Signed-off-by: Vivek Gautam Co-developed-by: Sai Prakash Ranjan Signed-off-by: Sa

[PATCH v2 0/7] drm/msm/a6xx: System Cache Support

l.org/patchwork/patch/1165298/ Jordan Crouse (3): iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context drm/msm: Attach the IOMMU device during initialization drm/msm: Refactor address space initialization Sharat Masetty (3): drm: msm: a6xx: Properly free up the iommu objects dr

[PATCH 4/5] drm/msm: Pass mmu features to generic layers

supports. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu

[PATCH 5/5] drm/msm/a6xx: Add support for using system cache(LLC)

larly DOMAIN_ATTR_QCOM_SYS_CACHE is another domain level attribute used by the IOMMU driver to set the right attributes to cache the hardware pagetables into the system cache. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 122 +- drivers/gpu/dr

[PATCH 1/5] iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context

From: Jordan Crouse Pass the propposed io_pgtable_cfg to the implementation specific init_context() function to give the implementation an opportunity to to modify it before it gets passed to io-pgtable. Signed-off-by: Jordan Crouse Signed-off-by: Sai Prakash Ranjan --- drivers/iommu/arm-smmu

[PATCH 0/5] drm/msm/a6xx: System Cache Support

io_pgtable_cfg to impl specific init_context Sharat Masetty (3): drm/msm: rearrange the gpu_rmw() function drm/msm: Pass mmu features to generic layers drm/msm/a6xx: Add support for using system cache(LLC) Vivek Gautam (1): iommu/arm-smmu: Add domain attribute for QCOM system cache drivers/gpu/drm

[PATCH 3/5] drm/msm: rearrange the gpu_rmw() function

The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function. Signed-off-by: Sharat Masetty Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c | 8

[PATCH 2/5] iommu/arm-smmu: Add domain attribute for QCOM system cache

From: Vivek Gautam Add iommu domain attribute for using system cache aka last level cache on QCOM SoCs by client drivers like GPU to set right attributes for caching the hardware pagetables into the system cache. Signed-off-by: Vivek Gautam Co-developed-by: Sai Prakash Ranjan Signed-off-by: Sa

[PATCH] arm: dts: sc7180: Add A618 gpu dt blob

This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts

[PATCH 5/5] arm: dts: sc7180: Add A618 gpu dt blob

This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts

[PATCH 0/5] Add support for A618 GPU

This patch adds support for A618 GPU. Please review. Sharat Masetty (5): drm: msm: Add 618 gpu to the adreno gpu list drm: msm: a6xx: Add support for A618 drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state drm: msm: a6xx: fix debug bus register configuration arm: dts: sc7180

[PATCH 1/5] drm: msm: Add 618 gpu to the adreno gpu list

This patch adds Adreno 618 entry and its associated properties to the gpulist entries. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm

[PATCH 4/5] drm: msm: a6xx: fix debug bus register configuration

Fix the cx debugbus related register configuration, to collect accurate bus data during gpu snapshot. This helps with complete snapshot dump and also complete proper GPU recovery. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 24 1 file

[PATCH 3/5] drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state

Add the relevant GBIF registers and the debug bus to the a6xx gpu state. This comes in pretty handy when debugging GPU bus related issues. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52 +++-- drivers/gpu/drm/msm/adreno

[PATCH 2/5] drm: msm: a6xx: Add support for A618

This patch adds support for enabling Graphics Bus Interface(GBIF) used in multiple A6xx series chipets. Also makes changes to the PDC/RSC sequencing specifically required for A618. This is needed for proper interfacing with RPMH. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno

[PATCH 3/5] drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state

Add the relevant GBIF registers and the debug bus to the a6xx gpu state. This comes in pretty handy when debugging GPU bus related issues. Change-Id: I224fda727012a456ccd28ca14caf9fcce236e629 Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52

[PATCH 0/5] Add support for A618 GPU

This series and support to enable A618 GPU revision. Please review. Sharat Masetty (5): drm: msm: Add 618 gpu to the adreno gpu list drm: msm: a6xx: Add support for A618 drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state drm: msm: a6xx: fix debug bus register configuration arm

[PATCH 2/5] drm: msm: a6xx: Add support for A618

: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 52 +++- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 24 +-- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 ++--- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 - drivers/gpu/drm

[PATCH 4/5] drm: msm: a6xx: fix debug bus register configuration

Fix the cx debugbus related register configuration, to collect accurate bus data during gpu snapshot. This helps with complete snapshot dump and also complete proper GPU recovery. Change-Id: I4f0ae3eb2dd5d24a88d805277fad212dda2d735e Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno

[PATCH 1/5] drm: msm: Add 618 gpu to the adreno gpu list

This patch adds Adreno 618 entry and its associated properties to the gpulist entries. Change-Id: Ie14ba09f32513ba6a6c882fda0d98ee1742b46d5 Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu

[PATCH 5/5] arm: dts: sc7180: Add A618 gpu dt blob

This patch adds the required dt nodes and properties to enabled A618 GPU. Change-Id: I7491c4de654c4b84d03dbcf703532448b27d4147 Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++ 1 file changed, 116 insertions(+) diff --git a/arch

[PATCH] rnndb: Add GBIF registers for a6xx GPU

Add GBIF register definitions required to implement a618 GPU revision Signed-off-by: Sharat Masetty --- rnndb/adreno/a6xx.xml | 26 ++ 1 file changed, 26 insertions(+) diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml index 747f071..2d2063a 100644 --- a/rnndb

[PATCH] drm: msm: a6xx: fix debug bus register configuration

Fix the cx debugbus related register configuration, to collect accurate bus data during gpu snapshot. This helps with complete snapshot dump and also complete proper GPU recovery. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 24 1 file

[PATCH] drm/msm/a5xx: Build a5xx_gpu_state_(get/put) under the right conditionals

Build the GPU crashstate capture functions only if either of CONFIG_DEBUG_FS, CONFIG_DEV_COREDUMP is defined. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c

[v2 1/2] drm/msm/adreno: Make adreno_gpu_state_get() return void

We are not really checking the state of the adreno_gpu_state_get() function at the callers and in addition the state capture is mostly a best effort service, so make the function return void. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 +--- drivers/gpu/drm/msm

[v2 2/2] drm/msm/a6xx: Fix NULL dereference during crashstate capture

The gpu crashstate's base objects registers pointer can be NULL if the target implementation decides to capture the register dump on its own. This patch simply checks for NULL before dereferencing. Signed-off-by: Sharat Masetty --- Changes from v1: Addressed comments from Jordan C

[PATCH 2/2] drm/msm/a6xx: Fix NULL dereference during crashstate capture

The gpu crashstate's base objects registers pointer can be NULL if the target implementation decides to capture the register dump on its own. This patch simply checks for NULL before dereferencing. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++---

[PATCH 1/2] drm/msm/adreno: Make adreno_gpu_state_get() return void

We are not really checking the state of the adreno_gpu_state_get() function at the callers and in addition the state capture is mostly a best effort service, so make the function return void. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 +--- drivers/gpu/drm/msm

[PATCH 2/2] drm/scheduler: Add drm_sched_suspend/resume_timeout()

patch also makes the job_list_lock IRQ safe. Suggested-by: Christian Koenig Signed-off-by: Sharat Masetty --- drivers/gpu/drm/etnaviv/etnaviv_dump.c | 9 ++-- drivers/gpu/drm/scheduler/sched_main.c | 91 -- include/drm/gpu_scheduler.h| 4 ++ 3 files

[PATCH 1/2] drm/scheduler: Set sched->thread to NULL on failure

In cases where the scheduler instance is used as a base object of another driver object, it's not clear if the driver can call scheduler cleanup on the fail path. So, Set the sched->thread to NULL, so that the driver can safely call drm_sched_fini() during cleanup. Signed-off-by: Sharat

[PATCH 3/4] drm/msm: Use msm_gpu_state_bo for ringbuffer data

The ring substructure in msm_gpu_state is an extension of msm_gpu_state_bo, so this patch changes the ring structure to reuse the msm_gpu_state_bo as a base class, instead of redefining the required variables. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 20

[PATCH 2/4] include/linux/ascii85: Update ascii85_encode()

The current implementation of ascii85_encode() does not copy the encoded buffer 'z' to the output buffer in case the input is zero. This patch simply adds this missing piece. This makes it easier to use this function to encode large buffers. Signed-off-by: Sharat Masetty --- inc

[PATCH 4/4] drm/msm: Optimize adreno_show_object()

depends on the size of the data captured by the driver. This is certainly not desirable and does not scale well with large captures. This patch encodes the buffer only once in the read path. With this there is an immediate >10X speed improvement in crashstate save time. Signed-off-by: Sharat Mase

[PATCH 1/4] drm/msm: use kvmalloc for ring data in gpu crashstate

The ringbuffer data to capture at crashtime can end up being large sometimes, and the size can vary from being less than a page to the full size of 32KB. So use the kvmalloc variant that perfectly fits the bill. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4

Re: [PATCH] drm/scheduler: Add drm_sched_suspend/resume timeout functions

On 11/15/2018 12:33 AM, Koenig, Christian wrote: Am 14.11.18 um 18:29 schrieb Sharat Masetty: On 11/8/2018 8:11 PM, Koenig, Christian wrote: Am 08.11.18 um 14:42 schrieb Sharat Masetty: Hi Christian, Can you please review this patch? It is a continuation of the discussion at [1]. At

Re: [PATCH] drm/scheduler: Add drm_sched_suspend/resume timeout functions

On 11/8/2018 8:11 PM, Koenig, Christian wrote: Am 08.11.18 um 14:42 schrieb Sharat Masetty: Hi Christian, Can you please review this patch? It is a continuation of the discussion at [1]. At first I was thinking of using a cancel for suspend instead of a mod(to an arbitrarily large value

[PATCH] drm/scheduler: Add drm_sched_suspend/resume timeout functions

n the right direction, I will put this through my testing drill and polish it. IMO I think I prefer the callback approach as it appears to be simple, less error prone for both the scheduler and the drivers. [1] https://patchwork.freedesktop.org/patch/259914/ Signed-off-by: Sharat Masetty --- driver

[PATCH 1/2] drm/msm/a6xx: Build a6xx_gpu_state under the right conditionals

Build a6xx_gpu_state.c only if either of CONFIG_DEBUG_FS, CONFIG_DEV_COREDUMP is defined. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/Makefile | 5 - drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu

[PATCH 2/2] drm/msm/a6xx: Fix a typo in a6xx gpu crash state

This patch simply fixes a typo for the name of an indexed register. CP_MEMPOOOL -> CP_MEMPOOL. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/driv

[PATCH 1/3] drm/msm: use kvmalloc for ring data in gpu crashstate

The ringbuffer data to capture at crashtime can end up being large sometimes, and the size can vary from being less than a page to the full size of 32KB. So use the kvmalloc variant that perfectly fits the bill. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4

[PATCH 2/3] include/linux/ascii85: Add ascii85_encode_to_buf()

: Sharat Masetty --- include/linux/ascii85.h | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/include/linux/ascii85.h b/include/linux/ascii85.h index 4cc4020..3665899 100644 --- a/include/linux/ascii85.h +++ b/include/linux/ascii85.h @@ -23,8 +23,12

[PATCH 3/3] drm/msm: Optimize adreno_show_object()

depends on the size of the data captured by the driver. This is certainly not desirable and does not scale well with large captures. This patch encodes the buffer only once in the read path. With this there is an immediate >10X speed improvement in crashstate save time. Signed-off-by: Sharat Mase

Re: [Freedreno] [PATCH 2/2] drm/scheduler: Add a start_timeout_notify() backend function

On 11/2/2018 7:07 PM, Koenig, Christian wrote: Am 02.11.18 um 14:25 schrieb Sharat Masetty: On 11/2/2018 4:09 PM, Koenig, Christian wrote: Am 02.11.18 um 11:31 schrieb Sharat Masetty: Add an optional backend function op which will let the scheduler clients know when the timeout got

Re: [Freedreno] [PATCH 2/2] drm/scheduler: Add a start_timeout_notify() backend function

On 11/2/2018 4:09 PM, Koenig, Christian wrote: Am 02.11.18 um 11:31 schrieb Sharat Masetty: Add an optional backend function op which will let the scheduler clients know when the timeout got scheduled on the scheduler instance. This will help drivers with multiple schedulers(one per ring

[PATCH 1/2] drm/scheduler: Set sched->thread to NULL on failure

In cases where the scheduler instance is used as a base object of another driver object, it's not clear if the driver can call scheduler cleanup on the fail path. So, Set the sched->thread to NULL, so that the driver can safely call drm_sched_fini() during cleanup. Signed-off-by: Sharat

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