-
From: Dave Airlie [mailto:airl...@gmail.com]
Sent: Tuesday, July 31, 2012 8:02 PM
To: Segovia, Benjamin
Cc: dri-devel at lists.freedesktop.org
Subject: Re: drm_intel_bo for the KMS framebuffer with IvyBridge?
On Wed, Aug 1, 2012 at 12:59 PM, Segovia, Benjamin
wrote:
> Hello all,
>
> Saying
Hello all,
Saying I want to play with an IvyBridge machine and the display when X is *not*
running (I just opened /dev/dri/card0 from a terminal). Is there a simple way
to get a drm_intel_bo for the terminal framebuffer such that I can brutally
write into it? So, can I easily get its bo and its
-
From: Dave Airlie [mailto:airl...@gmail.com]
Sent: Tuesday, July 31, 2012 8:02 PM
To: Segovia, Benjamin
Cc: dri-devel@lists.freedesktop.org
Subject: Re: drm_intel_bo for the KMS framebuffer with IvyBridge?
On Wed, Aug 1, 2012 at 12:59 PM, Segovia, Benjamin
wrote:
> Hello all,
>
> Saying
Hello all,
Saying I want to play with an IvyBridge machine and the display when X is *not*
running (I just opened /dev/dri/card0 from a terminal). Is there a simple way
to get a drm_intel_bo for the terminal framebuffer such that I can brutally
write into it? So, can I easily get its bo and its
Hello all,
I saw at some point that per-process GTT (ppGTT) may be (or is already)
implemented to handle paging. Right now, I am investigating some flat space
addressing (ab)using surface states. The idea is to create a surface state (raw
buffer only, this is GPGPU stuff) as big enough to cover
Hello all,
I saw at some point that per-process GTT (ppGTT) may be (or is already)
implemented to handle paging. Right now, I am investigating some flat space
addressing (ab)using surface states. The idea is to create a surface state (raw
buffer only, this is GPGPU stuff) as big enough to cover
1/ Thanks!
2/ Is it available now or is it still a project?
Thanks,
Ben
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Saturday, May 28, 2011 1:54 AM
To: Segovia, Benjamin; dri-devel@lists.freedesktop.org
Subject: Re: Questions about libdrm_intel and way
1/ Thanks!
2/ Is it available now or is it still a project?
Thanks,
Ben
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Saturday, May 28, 2011 1:54 AM
To: Segovia, Benjamin; dri-devel at lists.freedesktop.org
Subject: Re: Questions about libdrm_intel and
Hello gurus,
I have two question mostly regarding libdrm_intel
1/ What is the difference between drm_intel_bo_map and drm_intel_gem_bo_map_gtt
?
2/ Will it be possible (or is it already possible) to directly share a
regularly allocated piece of physical memory? Typical use case is the following
Hello gurus,
I have two question mostly regarding libdrm_intel
1/ What is the difference between drm_intel_bo_map and drm_intel_gem_bo_map_gtt
?
2/ Will it be possible (or is it already possible) to directly share a
regularly allocated piece of physical memory? Typical use case is the following
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Saturday, March 26, 2011 12:21 AM
To: Segovia, Benjamin; DRI
Subject: Re: Tracking drm_intel_bo allocation
On Fri, 25 Mar 2011 23:36:33 -0700, "Segovia, Benjamin"
wrote:
> Hello all,
>
> I am
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Saturday, March 26, 2011 12:21 AM
To: Segovia, Benjamin; DRI
Subject: Re: Tracking drm_intel_bo allocation
On Fri, 25 Mar 2011 23:36:33 -0700, "Segovia, Benjamin" wrote:
> Hello all,
>
> I am
Hello all,
I am using drm_intel to access the HW. I would like to know if there is any way
to know if my application frees all the bos I used. I would like to be sure I
cleanly freed my resources and no bo is still referenced.
Is there any tool in the memory allocation part of drm_intel to do th
Hello all,
I am using drm_intel to access the HW. I would like to know if there is any way
to know if my application frees all the bos I used. I would like to be sure I
cleanly freed my resources and no bo is still referenced.
Is there any tool in the memory allocation part of drm_intel to do th
.uk]
Sent: Tuesday, December 14, 2010 2:00 AM
To: Segovia, Benjamin; Segovia, Benjamin; Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
On Mon, 13 Dec 2010 20:32:42 -0800, "Segovia, Benjamin"
wrote:
> To be more explicit, my concern is that I read that Chris Wilson pro
.uk]
Sent: Tuesday, December 14, 2010 2:00 AM
To: Segovia, Benjamin; Segovia, Benjamin; Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
On Mon, 13 Dec 2010 20:32:42 -0800, "Segovia, Benjamin" wrote:
> To be more explicit, my concern is that I read that Chris Wilson pro
using surface
descriptors.
Cheers,
Ben
From: Chris Wilson [ch...@chris-wilson.co.uk]
Sent: Tuesday, December 14, 2010 2:59 AM
To: Segovia, Benjamin; Segovia, Benjamin; Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
On Mon, 13 Dec 2010 20:32:42
using surface
descriptors.
Cheers,
Ben
From: Chris Wilson [ch...@chris-wilson.co.uk]
Sent: Tuesday, December 14, 2010 2:59 AM
To: Segovia, Benjamin; Segovia, Benjamin; Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
On Mon, 13 Dec 2010 20:32:42
mapped in user space, my buffer can be safely used by
both CPUs and GPUs and that the VM will never swap it?
Ben
Original Message-
From: Segovia, Benjamin
Sent: Monday, December 13, 2010 8:20 PM
To: Segovia, Benjamin; Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
I have been
mapped in user space, my buffer can be safely used by
both CPUs and GPUs and that the VM will never swap it?
Ben
Original Message-
From: Segovia, Benjamin
Sent: Monday, December 13, 2010 8:20 PM
To: Segovia, Benjamin; Zhenyu Wang
Cc: DRI
Subject: RE: Intel DRM driver for SNB
I have been
is
processing the batch buffer.
Am I doing something correct?
Ben
-Original Message-
From: dri-devel-bounces+benjamin.segovia=intel@lists.freedesktop.org
[mailto:dri-devel-bounces+benjamin.segovia=intel@lists.freedesktop.org] On
Behalf Of Segovia, Benjamin
Sent: Friday
is
processing the batch buffer.
Am I doing something correct?
Ben
-Original Message-
From: dri-devel-bounces+benjamin.segovia=intel.com at lists.freedesktop.org
[mailto:dri-devel-bounces+benjamin.segovia=intel@lists.freedesktop.org] On
Behalf Of Segovia, Benjamin
Sent: Friday
functions. However, I am not sure I can get symbols from i915 properly. Is a
i915 patch the only solution?
Cheers,
Ben
From: Zhenyu Wang [zhen...@linux.intel.com]
Sent: Monday, December 06, 2010 11:00 PM
To: Segovia, Benjamin
Cc: DRI
Subject: Re: Intel DRM
functions. However, I am not sure I can get symbols from i915 properly. Is a
i915 patch the only solution?
Cheers,
Ben
From: Zhenyu Wang [zhen...@linux.intel.com]
Sent: Monday, December 06, 2010 11:00 PM
To: Segovia, Benjamin
Cc: DRI
Subject: Re: Intel DRM
Hello all,
is the kernel driver configured to support reads/writes to LLC (last level
cache i.e. L3) on SNB?
Cheers,
Ben
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
Hello all,
is the kernel driver configured to support reads/writes to LLC (last level
cache i.e. L3) on SNB?
Cheers,
Ben
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