_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
> > > else
> > > hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
> > >
> > > Note:
> > > //(2: 1 for sync, 1 for phy idle)
> > > data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_h
; //(2: 1 for sync, 1 for phy idle)
> > data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
> >
> > bpp: bit per pixel
> >
> > Signed-off-by: Jitao Shi
> > Tested-by: Ryan Case
> > Reviewed-by: CK Hu
>
> This version is different than previou
On Thu, Jun 27, 2019 at 11:11 PM CK Hu wrote:
>
> Hi, Jitao:
>
> On Thu, 2019-06-27 at 16:01 +0800, Jitao Shi wrote:
> > DSI panel driver need attach function which is inculde in
> > mipi_dsi_host_ops.
> >
> > If mipi_dsi_host_register is not in probe, dsi panel will
> > probe more delay.
> >
> >
On Mon, Jul 8, 2019 at 3:37 PM wrote:
>
> From: Yongqiang Niu
>
> This patch add mutex description for mt8183 display
>
> Signed-off-by: Yongqiang Niu
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
> a/Documen
On Mon, Jul 8, 2019 at 3:35 PM wrote:
>
> From: Yongqiang Niu
>
> This patch add ovl0/ovl_2l0 usecase
> in ovl->ovl_2l0 direct link usecase:
> 1. the crtc support layer number will 4+2
> 2. ovl_2l0 background color input select ovl0 when crtc init
> and disable it when crtc finish
> 3. config ovl
-* overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
> -* mipi_ratio = (htotal_time + overhead_time) / htotal_time
> -* data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
> -*/
> - pixel_clock = dsi->vm.pixelclock;
> - htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch
> +
> - dsi->vm.hsync_len;
> - htotal_bits = htotal * bit_per_pixel;
> -
> - overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
> - T_HS_EXIT;
> - overhead_bits = overhead_cycles * dsi->lanes * 8;
> - total_bits = htotal_bits + overhead_bits;
> -
> - dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
> - htotal * dsi->lanes);
> + dsi->data_rate = dsi->vm.pixelclock * bit_per_pixel / dsi->lanes;
>
> ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
> if (ret < 0) {
With the earlier fix feel free to add to the next revision
Tested-by: Ryan Case
