Hello Frank,
On Mon May 8, 2023 at 10:47 AM CEST, Frank Oltmanns wrote:
> I tested this on my pinephone on drm-next, using additional patches for
> the pinephone's panel. [1] [2] [3]
Thank you for testing this and all the previous version of this
patchset. I appreciate your help.
> I played back
In DSI mode, TCON0's data clock is required to run at 1/4 the per-lane
bit rate.
Signed-off-by: Roman Beranek
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 36 +-
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/dr
so stick with that.
Signed-off-by: Roman Beranek
---
drivers/gpu/drm/sun4i/Makefile | 2 +-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 10 +-
.../drm/sun4i/{sun4i_dotclock.c => sun4i_tcon_dclk.c} | 2 +-
.../drm/sun4i/{sun4i_dotclock.h => sun
While the rate of TCON0's DCLK matches dotclock for parallel and LVDS
outputs, this doesn't hold for DSI. According manuals from Allwinner,
DCLK is an abbreviation of Data Clock, not dotclock, so go with that
instead.
Signed-off-by: Roman Beranek
---
arch/arm/boot/dts/
s prevents PLL_VIDEO0 from participating
in setting of the TCON0 data clock rate, limiting the precision with
which a target pixel clock can be matched.
For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock
can deviate up to 8% off target.
Signed-off-by: Roman Beranek
---
drivers
video0 can't be included in setting TCON0 DCLK rate
2. reset pll-video0 to its default rate in case u-boot changed it
v4:
1. keep pll-video0 as is
2. assign parent to TCON0 mux in sun50i_a64_ccu_probe (not in DT)
Roman Beranek (4):
clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 m
Hello everyone,
I apologize for my absence from the discussion during past week, I got
hit with tonsillitis.
On Mon May 1, 2023 at 3:40 PM CEST, Frank Oltmanns wrote:
> Looking at ccu_nkm_determine_rate(), we've found our culprit because it
> does not try parent clock rates other than the current
In DSI mode, TCON0's data clock is required to run at 1/4 the per-lane
bit rate.
Signed-off-by: Roman Beranek
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 36 +-
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/dr
Hz, a value preferable to what it is
later set to in u-boot (294 MHz). This happens unintentionally though,
as u-boot, for the sake of simplicity, rounds the rate requested by DE2
driver (297 MHz) to 6 MHz steps.
Reset the PLL to its default rate of 297 MHz.
Signed-off-by: Roman Beranek
---
arch/
While the rate of TCON0's DCLK matches dotclock for parallel and LVDS
outputs, this doesn't hold for DSI. According manuals from Allwinner,
DCLK is an abbreviation of Data Clock, not dotclock, so go with that
instead.
Signed-off-by: Roman Beranek
---
arch/arm/boot/dts/
so forcing them to settle on pll-mipi. The parent will be assigned
during boot based off of tcon0's DT node.
Signed-off-by: Roman Beranek
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/dr
so stick with that.
Signed-off-by: Roman Beranek
---
drivers/gpu/drm/sun4i/Makefile | 2 +-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 10 +-
.../drm/sun4i/{sun4i_dotclock.c => sun4i_tcon_dclk.c} | 2 +-
.../drm/sun4i/{sun4i_dotclock.h => sun
PLL_MIPI will be referenced as assigned parent to TCON0
Signed-off-by: Roman Beranek
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 4 +++-
include/dt-bindings/clock/sun50i-a64-ccu.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
b
Assign pll-mipi parent to tcon0's source clock via 'assigned-clocks'.
Signed-off-by: Roman Beranek
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwi
video0 can't be included in setting TCON0 DCLK rate
2. reset pll-video0 to its default rate in case u-boot changed it
Roman Beranek (7):
clk: sunxi-ng: a64: export PLL_MIPI
clk: sunxi-ng: a64: prevent CLK_TCON0 being reparented
arm64: dts: allwinner: a64: assign PLL_MIPI to CLK_TCON0
a
so stick with that.
Signed-off-by: Roman Beranek
---
drivers/gpu/drm/sun4i/Makefile | 2 +-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 10 +-
.../drm/sun4i/{sun4i_dotclock.c => sun4i_tcon_dclk.c} | 2 +-
.../drm/sun4i/{sun4i_dotclock.h => sun
While the rate of TCON0's DCLK matches dotclock for parallel and LVDS
outputs, this doesn't hold for DSI. According manuals from Allwinner,
DCLK is an abbreviation of Data Clock, not dotclock, so go with that
instead.
Signed-off-by: Roman Beranek
---
arch/arm/boot/dts/
Propagating rate change from tcon0 all the way to pll-video0 allows for
greater precision in matching requested display timing.
Signed-off-by: Roman Beranek
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu
PLL_MIPI will be referenced as assigned parent to TCON0
Signed-off-by: Roman Beranek
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 4 +++-
include/dt-bindings/clock/sun50i-a64-ccu.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
b
Assign pll-mipi parent to tcon0's source clock via 'assigned-clocks'.
Signed-off-by: Roman Beranek
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwi
so forcing them to settle on pll-mipi. The parent will be assigned
during boot based off of tcon0's DT node.
Signed-off-by: Roman Beranek
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/dr
In DSI mode, TCON0's data clock is required to run at 1/4 the per-lane
bit rate.
Signed-off-by: Roman Beranek
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 36 +-
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/dr
hould now match refresh rate implied by set display mode. It
was verified to do so on a A64 board with a 2-lane and a 4-lane panel.
v2:
1. prevent reparent of tcon0 to pll-video0-2x
2. include pll-video0 in setting TCON0 DCLK rate
3. tested the whole thing also on a PinePhone
Roman Beranek (7):
clk
On Wed Apr 5, 2023 at 5:03 PM CEST, Maxime Ripard wrote:
> On Wed, Apr 05, 2023 at 02:34:11PM +0200, Roman Beranek wrote:
> > It turns out however that the new dclk rates can't be set exactly as
> > requested without touching pll-video0*, tcon0 now therefore gets
> > r
On Sat Apr 8, 2023 at 9:07 AM CEST, Jernej Škrabec wrote:
> Dne sreda, 05. april 2023 ob 14:34:11 CEST je Roman Beranek napisal(a):
> > While simply forbidding the video0-2x mux option seems
> > to me as the right way to go because there's not much use for it with
> >
Hello Maxime,
On Wed Mar 29, 2023 at 9:58 PM CEST, Maxime Ripard wrote:
> > In order to preserve semantic correctness however, I propose to preface
> > the change with a patch that renames sun4i_dotclock and tcon-pixel-clock
> > such that dot/pixel is replaced with d/data. What do you think?
>
> I
On Mon Apr 3, 2023 at 5:08 PM CEST, Frank Oltmanns wrote:
>
> On 2023-04-03 at 15:52:36 +0200, "Roman Beranek" wrote:
> > As little a change as setting .clock in the default mode of PP's panel
> > to 73500 can fix it. Better yet, dropping pll-video0-2x from the
On Sun Apr 2, 2023 at 12:49 PM CEST, Frank Oltmanns wrote:
>
> When apply this to drm-next my panel stays dark. I haven't figured out
> yet why, though. The other two patches in this series work fine, i.e.
> they have no effect as they are just a refactoring.
>
> I'm testing this on my pinephone. I
so stick with that.
Signed-off-by: Roman Beranek
---
drivers/gpu/drm/sun4i/Makefile | 2 +-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 10 +-
.../drm/sun4i/{sun4i_dotclock.c => sun4i_tcon_dclk.c} | 2 +-
.../drm/sun4i/{sun4i_dotclock.h => sun
While the rate of TCON0's DCLK matches dotclock for parallel and LVDS
outputs, this doesn't hold for DSI. According manuals from Allwinner,
DCLK is an abbrebiation of Data Clock, not dotclock, so go with that
instead.
Signed-off-by: Roman Beranek
---
arch/arm/boot/dts/
In DSI mode, TCON0's data clock is required to run at 1/4 the per-lane
bit rate.
Signed-off-by: Roman Beranek
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 36 +-
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/dr
While the rate of TCON0's DCLK matches dotclock for parallel and LVDS
outputs, this doesn't hold for DSI. According manuals from Allwinner,
DCLK is an abbrebiation of Data Clock, not dotclock, so go with that
instead.
Signed-off-by: Roman Beranek
---
arch/arm/boot/dts/
. It
was verified to do so on a A64 board with a 2-lane and a 4-lane panel.
Roman Beranek (3):
drm: sun4i: rename sun4i_dotclock to sun4i_tcon_dclk
ARM: dts: sunxi: rename tcon's clock output
drm: sun4i: calculate proper DCLK rate for DSI
arch/arm/boot/dts/sun5i.dtsi
Hello Frank,
On Thu Mar 30, 2023 at 6:45 AM CEST, Frank Oltmanns wrote:
> Roman, will you please submit a V2 of the patch I submitted then? Or do
> you want me to do it?
Yes, I'm already on it, only missing a cover letter.
Roman
On Mon Mar 27, 2023 at 10:20 PM CEST, Maxime Ripard wrote:
>
> On Sat, Mar 25, 2023 at 12:40:04PM +0100, Frank Oltmanns wrote:
> > Claiming to set the divider to a different value (bpp / lanes) than what
> > we’re actually using in
> > the end (SUN6I_DSIO_TCON_DIV) is somehow bugging me. I feel li
On Tue Mar 21, 2023 at 8:55 PM CET, Frank Oltmanns wrote:
> My apologies, I wasn’t patient enough.
Frank, there's no need to apologize, in my judgement. You weren't
impatient, we simply happened to run into a coordination problem for
which, I think, neither of us was particularly to blamew. Take i
On Tue Mar 21, 2023 at 5:50 PM CET, Roman Beranek wrote:
> > Also, how was it tested/confirmed?
>
> By counting Vblank interrupts (GIC 118).
Sorry, that was perhaps too abbreviated. To test this change, I set up
an A64 board running kmscube on DSI-1 and verified that the rate of
Hello Maxime,
On Tue Mar 21, 2023 at 3:56 PM CET, Maxime Ripard wrote:
>
> This is similar to
> https://lore.kernel.org/all/20230319160704.9858-2-fr...@oltmanns.dev/
>
> What's the story there?
Yes, Frank Oltmanns wrote me recently in relation to a patch I wrote
~ 3 years ago that addressed the f
xel / number of DSI lanes
[2]
https://github.com/BPI-SINOVOIP/BPI-M64-bsp-4.4/blob/66bef0f2f30b367eb93b1cbad21ce85e0361f7ae/linux-sunxi/drivers/video/fbdev/sunxi/disp2/disp/de/lowlevel_sun50iw1/disp_al.c#L322
Signed-off-by: Roman Beranek
---
drivers/gpu/drm/sun4i/sun4i_dotclock.c | 6 +-
drivers/
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