From: Rob Clark
If userspace is trying to achieve a timeout of zero, let 'em have it.
Only round up if the timeout is greater than zero.
Fixes: 4969bccd5f4e ("drm/msm: Avoid rounding down to zero jiffies")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.h | 11
From: Rob Clark
If userspace is trying to achieve a timeout of zero, let 'em have it.
Only round up if the timeout is greater than zero.
Fixes: 4969bccd5f4e ("drm/msm: Avoid rounding down to zero jiffies")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.h | 10 +++
On Wed, Jan 8, 2025 at 7:14 PM Abhinav Kumar wrote:
>
>
>
> On 1/8/2025 7:04 PM, Rob Clark wrote:
> > On Wed, Jan 8, 2025 at 6:22 PM Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 1/8/2025 6:14 PM, Dmitry Baryshkov wrote:
> >
On Wed, Jan 8, 2025 at 6:22 PM Abhinav Kumar wrote:
>
>
>
> On 1/8/2025 6:14 PM, Dmitry Baryshkov wrote:
> > On Thu, 9 Jan 2025 at 03:45, Rob Clark wrote:
> >>
> >> On Wed, Jan 8, 2025 at 2:58 PM Jessica Zhang
> >> wrote:
> >>>
> >
On Wed, Jan 8, 2025 at 2:58 PM Jessica Zhang wrote:
>
> Force commit that are disabling a plane in the async_crtc to take the
> non-async commit tail path.
>
> In cases where there are two consecutive async cursor updates (one
> regular non-NULL update followed by a disabling NULL FB update), it i
nd bandwidth index of OPP and set it along freq index
drm/msm: adreno: enable GMU bandwidth for A740 and A750
Rex Nie (1):
drm/msm/hdmi: simplify code in pll_get_integloop_gain
Rob Clark (2):
Merge remote-tracking branch 'pm/opp/linux-next' into HEAD
drm/msm
On Tue, Jan 7, 2025 at 4:58 AM Will Deacon wrote:
>
> On Tue, Jan 07, 2025 at 12:55:55PM +, Mostafa Saleh wrote:
> > On Tue, Dec 10, 2024 at 08:51:18AM -0800, Rob Clark wrote:
> > > From: Rob Clark
> > >
> > > This series extends io-pgtable-arm with a
ee for communication with AOSS.
> >
> > The devicetree patch in this series adds the acd-level data for X1-85
> > GPU present in Snapdragon X1 Elite chipset.
> >
> > The last two devicetree patches are for Bjorn and all the rest for
> > Rob Clark.
>
From: Rob Clark
Debugging incorrect UAPI usage tends to be a bit painful, so add a
helper macro to make it easier to add debug logging which can be enabled
at runtime via drm.debug.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21
drivers/gpu/drm/msm
4 5:50 PM, Akhil P Oommen wrote:
> >>>> On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
> >>>>> On 12/12/24 4:58 PM, Akhil P Oommen wrote:
> >>>>>> On 12/5/2024 10:24 PM, Rob Clark wrote:
> >>>>>>> From: Rob Clark
ntonino Maniscalco wrote:
> > >>> On 12/12/24 4:58 PM, Akhil P Oommen wrote:
> > >>>> On 12/5/2024 10:24 PM, Rob Clark wrote:
> > >>>>> From: Rob Clark
> > >>>>>
> > >>>>> Performance counter usage falls
On Fri, Dec 13, 2024 at 8:47 AM Akhil P Oommen wrote:
>
> On 12/12/2024 10:42 PM, Rob Clark wrote:
> > On Thu, Dec 12, 2024 at 9:08 AM Rob Clark wrote:
> >>
> >> On Thu, Dec 12, 2024 at 7:59 AM Akhil P Oommen
> >> wrote:
> >>>
> >&g
On Fri, Dec 13, 2024 at 5:11 AM Konrad Dybcio
wrote:
>
> On 23.11.2024 3:41 AM, Rob Clark wrote:
> > On Fri, Nov 22, 2024 at 4:19 PM Konrad Dybcio
> > wrote:
> >>
> >> On 22.11.2024 4:51 PM, Rob Clark wrote:
> >>> On Fri, Nov 22, 2024 at 4:21
On Thu, Dec 12, 2024 at 9:08 AM Rob Clark wrote:
>
> On Thu, Dec 12, 2024 at 7:59 AM Akhil P Oommen
> wrote:
> >
> > On 12/5/2024 10:24 PM, Rob Clark wrote:
> > > From: Rob Clark
> > >
> > > Performance counter usage falls into two categorie
On Thu, Dec 12, 2024 at 7:59 AM Akhil P Oommen wrote:
>
> On 12/5/2024 10:24 PM, Rob Clark wrote:
> > From: Rob Clark
> >
> > Performance counter usage falls into two categories:
> >
> > 1. Local usage, where the counter configuration, start, and end read
On Tue, Dec 10, 2024 at 7:08 PM Akhil P Oommen wrote:
>
> On 12/11/2024 6:43 AM, Bjorn Andersson wrote:
> > On Tue, Dec 10, 2024 at 02:22:27AM +0530, Akhil P Oommen wrote:
> >> On 12/10/2024 1:24 AM, Rob Clark wrote:
> >>> On Mon, Dec 9, 2024 at 12:2
From: Rob Clark
In the case of iova fault triggered devcore dumps, include additional
debug information based on what we think is the current page tables,
including the TTBR0 value (which should match what we have in
adreno_smmu_fault_info unless things have gone horribly wrong), and
the
From: Rob Clark
This series extends io-pgtable-arm with a method to retrieve the page
table entries traversed in the process of address translation, and then
beefs up drm/msm gpu devcore dump to include this (and additional info)
in the devcore dump.
This is a respin of https
On Tue, Dec 10, 2024 at 3:14 AM Will Deacon wrote:
>
> Hi Rob,
>
> On Mon, Oct 28, 2024 at 02:31:36PM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > This series extends io-pgtable-arm with a method to retrieve the page
> > table entries traversed in the
On Mon, Dec 9, 2024 at 12:52 PM Akhil P Oommen wrote:
>
> On 12/10/2024 1:24 AM, Rob Clark wrote:
> > On Mon, Dec 9, 2024 at 12:20 AM Akhil P Oommen
> > wrote:
> >>
> >> When kernel is booted in EL2, SECVID registers are accessible to the
> >> KMD. S
On Mon, Dec 9, 2024 at 12:20 AM Akhil P Oommen wrote:
>
> When kernel is booted in EL2, SECVID registers are accessible to the
> KMD. So we can use that to switch GPU's secure mode to avoid dependency
> on Zap firmware. Also, we can't load a secure firmware without a
> hypervisor that supports it.
From: Rob Clark
Add a SET_PARAM for userspace to request to manage to the VM itself,
instead of getting a kernel managed VM.
In order to transition to a userspace managed VM, this param must be set
before any mappings are created.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno
From: Rob Clark
We'll re-use this in the vm_bind path.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 12 ++--
drivers/gpu/drm/msm/msm_gem.h | 1 +
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/dr
From: Rob Clark
If userspace has opted-in to VM_BIND, then GPU faults and VM_BIND errors
will mark the VM as unusable.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.h| 17 +
drivers/gpu/drm/msm/msm_gem_submit.c | 3 +++
drivers/gpu/drm/msm/msm_gpu.c
From: Rob Clark
Add PRR (Partial Resident Region) is a bypass address which make GPU
writes go to /dev/null and reads return zero. This is used to implement
vulkan sparse residency.
To support PRR/NULL mappings, we allocate a page to reserve a physical
address which we know will not be used as
From: Rob Clark
This fits better drm_gpuvm/drm_gpuva.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 16 +++-
drivers/gpu/drm/msm/msm_gem_vma.c | 2 ++
2 files changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu
From: Rob Clark
Bump version to signal to userspace that VM_BIND is supported.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index b31ec287c600
From: Rob Clark
Hook up the map/remap/unmap ops to apply MAP/UNMAP operations. The
MAP/UNMAP operations are split up by drm_gpuvm into a series of map/
remap/unmap ops, for example an UNMAP operation which spans multiple
vmas will get split up into a sequence of unmap (and possibly remap)
ops
From: Rob Clark
Buffers that are not shared between contexts can share a single resv
object. This way drm_gpuvm will not track them as external objects, and
submit-time validating overhead will be O(1) for all N non-shared BOs,
instead of O(n).
Signed-off-by: Rob Clark
---
drivers/gpu/drm
From: Rob Clark
This is a more descriptive name.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 4 ++--
drivers/gpu/drm/msm/msm_gem.h | 2 +-
drivers/gpu/drm/msm/msm_gem_vma.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm
From: Rob Clark
Only needs to be supported for iopgtables mmu, the other cases are
either only used for kernel managed mappings (where offset is always
zero) or devices which do not support sparse bindings.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a2xx_gpummu.c | 5
From: Rob Clark
This is a bit different than the path taken by other clean-slate
drivers. But there is a lot in similar with BO pinning in the legacy
"EXEC" path and "VM_BIND" MAP path. Also, we want the same fence and
syncobj handling.
(Why bother with fence fd's?
From: Rob Clark
This submitqueue type isn't tied to a hw ringbuffer, but instead
executes on the CPU for performing async VM_BIND ops.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 3 +-
drivers/gpu/drm/msm/msm_gem.h | 10 +++
drivers/gpu/dr
From: Rob Clark
For VM_BIND, in the first step, we just want to get the backing pages,
but defer creating the vma until the map/unmap/ops are evaluated.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem_submit.c | 27 +++
1 file changed, 19 insertions(+), 8
From: Rob Clark
In the next commit, a way for userspace to opt-in to userspace managed
VM is added. For this to work, we need to defer creation of the VM
until it is needed.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 ++-
drivers/gpu/drm/msm/adreno/adreno_gpu.c
From: Rob Clark
Most of the driver code doesn't need to reach in to msm specific fields,
so just use the drm_gpuvm/drm_gpuva types directly. This should
hopefully improve commonality with other drivers and make the code
easier to understand.
Signed-off-by: Rob Clark
---
drivers/gpu/dr
From: Rob Clark
It is standing in the way of drm_gpuvm / VM_BIND support. Not to
mention frequently broken and rarely tested. And I think only needed
for a 10yr old not quite upstream SoC (msm8974).
Maybe we can add support back in later, but I'm doubtful.
Signed-off-by: Rob
From: Rob Clark
The WIP VM_BIND patches don't yet support shrinker..
Not-signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 2aefb8b
From: Rob Clark
Now that we've realigned deletion and allocation, switch over to using
drm_gpuvm/drm_gpuva. This allows us to support multiple VMAs per BO per
VM, to allow mapping different parts of a single BO at different virtual
addresses, which is a key requirement for sparse/VM_BIND.
From: Rob Clark
Now that we've dropped vram carveout support, we can collapse vma
allocation and initialization. This better matches how things work
with drm_gpuvm.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 30 +++---
drivers/gpu/drm/msm/msm_
From: Rob Clark
Re-aligning naming to better match drm_gpuvm terminology will make
things less confusing at the end of the drm_gpuvm conversion.
This is just rename churn, no functional change.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 18 ++--
drivers/gpu
From: Rob Clark
See commit a414fe3a2129 ("drm/msm/gem: Drop obj lock in
msm_gem_free_object()") for justification.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_gpuvm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_gpuvm.c b/drive
From: Rob Clark
Conversion to DRM GPU VA Manager[1], and adding support for Vulkan Sparse
Memory[2] in the form of:
1. A new VM_BIND submitqueue type for executing VM MSM_SUBMIT_BO_OP_MAP/
MAP_NULL/UNMAP commands
2. Extending the SUBMIT` ioctl to allow submitting batches of one or more
MAP
From: Rob Clark
This is a more descriptive name.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++--
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 4 +--
drivers/gpu/drm/msm/msm_drv.c | 14 -
drivers
From: Rob Clark
Just some tidying up.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu.h | 44 +++
1 file changed, 29 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 76ad75f06706
From: Rob Clark
If the driver is using an external mutex to synchronize vm access, it
doesn't need to hold vm->r_obj->resv. And if the driver is already
holding obj->resv, then needing to pointlessly grab vm->r_obj->resv will
be seen by lockdep as nested locking.
Sign
From: Rob Clark
Performance counter usage falls into two categories:
1. Local usage, where the counter configuration, start, and end read
happen within (locally to) a single SUBMIT. In this case, there is
no dependency on counter configuration or values between submits, and
in fact
On Wed, Dec 4, 2024 at 1:47 PM Rob Clark wrote:
>
> On Wed, Dec 4, 2024 at 11:04 AM Akhil P Oommen
> wrote:
> >
> > On 12/1/2024 10:06 PM, Rob Clark wrote:
> > > On Sat, Nov 30, 2024 at 12:30 PM Akhil P Oommen
> > > wrote:
> > >>
> >
On Wed, Dec 4, 2024 at 11:04 AM Akhil P Oommen wrote:
>
> On 12/1/2024 10:06 PM, Rob Clark wrote:
> > On Sat, Nov 30, 2024 at 12:30 PM Akhil P Oommen
> > wrote:
> >>
> >> On 11/30/2024 7:01 PM, Konrad Dybcio wrote:
> >>> On 25.11.2024 5:33
On Tue, Dec 3, 2024 at 1:59 AM Danylo Piliaiev
wrote:
>
> This adds MSM_PARAM_UCHE_TRAP_BASE that will be used by Mesa
> implementation for VK_KHR_shader_clock and GL_ARB_shader_clock.
>
> Signed-off-by: Danylo Piliaiev
> ---
> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 6 --
> drivers/gpu/d
On Sat, Nov 30, 2024 at 12:30 PM Akhil P Oommen
wrote:
>
> On 11/30/2024 7:01 PM, Konrad Dybcio wrote:
> > On 25.11.2024 5:33 PM, Akhil P Oommen wrote:
> >> There are a few chipsets which don't have system cache a.k.a LLC.
> >> Currently, the assumption in the driver is that the system cache
> >>
On Fri, Nov 22, 2024 at 4:19 PM Konrad Dybcio
wrote:
>
> On 22.11.2024 4:51 PM, Rob Clark wrote:
> > On Fri, Nov 22, 2024 at 4:21 AM Konrad Dybcio
> > wrote:
> >>
> >> On 21.11.2024 5:48 PM, Rob Clark wrote:
> >>> From: Rob Clark
> >>
On Fri, Nov 22, 2024 at 4:21 AM Konrad Dybcio
wrote:
>
> On 21.11.2024 5:48 PM, Rob Clark wrote:
> > From: Rob Clark
> >
> > Debugging incorrect UAPI usage tends to be a bit painful, so add a
> > helper macro to make it easier to add debug logging which can
On Fri, Nov 22, 2024 at 1:51 AM Jani Nikula wrote:
>
> On Fri, 22 Nov 2024, Masahiro Yamada wrote:
> > Documentation/process/changes.rst
> > documents basic tools necessary for building the kernel.
> >
> > Python3 is listed as "optional" because it is required
> > only for some CONFIG options.
>
On Thu, Nov 21, 2024 at 11:50 AM Rob Clark wrote:
>
> On Tue, Nov 19, 2024 at 9:56 AM Neil Armstrong
> wrote:
> >
> > The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
>
> nit, s/GNU/GMU/
And I guess you meant "GPU Management Unit&quo
On Tue, Nov 19, 2024 at 9:56 AM Neil Armstrong
wrote:
>
> The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
nit, s/GNU/GMU/
> along the Frequency and Power Domain level, but by default we leave the
> OPP core vote for the interconnect ddr path.
>
> While scaling via the inter
On Thu, Nov 21, 2024 at 10:44 AM Dmitry Baryshkov
wrote:
>
> On Wed, Nov 20, 2024 at 10:54:24AM -0800, Rob Clark wrote:
> > On Wed, Nov 20, 2024 at 3:18 AM Dmitry Baryshkov
> > wrote:
> > >
> > > On Tue, Nov 19, 2024 at 06:56:38PM +0100, Neil Armstrong wro
From: Rob Clark
Debugging incorrect UAPI usage tends to be a bit painful, so add a
helper macro to make it easier to add debug logging which can be enabled
at runtime via drm.debug.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21
drivers/gpu/drm/msm
On Wed, Nov 20, 2024 at 5:17 PM Petr Vorel wrote:
>
> > On Thu, Nov 21, 2024 at 5:41 AM Petr Vorel wrote:
>
> > > It will be used in the next commit for DRM_MSM.
>
> > > Suggested-by: Rob Clark
> > > Signed-off-by: Petr Vorel
> > > ---
>
On Wed, Nov 20, 2024 at 3:18 AM Dmitry Baryshkov
wrote:
>
> On Tue, Nov 19, 2024 at 06:56:38PM +0100, Neil Armstrong wrote:
> > Now the features defines have the right name, introduce a features
> > bitfield and move the features defines in it, fixing all code checking
> > for them.
> >
> > No fun
On Wed, Nov 20, 2024 at 7:49 AM Petr Vorel wrote:
>
> 0fddd045f88e introduced python3 dependency, require it to quick early.
>
> Signed-off-by: Petr Vorel
> ---
> Hi all,
>
> RFC because I'm not sure if previous failed build wasn't better:
>
> GENHDR drivers/gpu/drm/msm/generated/a2xx.xm
On Fri, Nov 15, 2024 at 6:18 AM Dmitry Baryshkov
wrote:
>
> On Fri, 15 Nov 2024 at 11:21, Neil Armstrong
> wrote:
> >
> > On 15/11/2024 08:07, Dmitry Baryshkov wrote:
> > > On Wed, Nov 13, 2024 at 04:48:28PM +0100, Neil Armstrong wrote:
> > >> The Adreno GMU Management Unit (GNU) can also scale
The "upstream" for the gpu related .xml files is in mesa because they
are used by the usermode (gl/vk) drivers:
https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/freedreno/registers/adreno/adreno_pm4.xml?ref_type=heads#L573
Things should be fixed/changed there, otherwise the change will ge
e and make the call.
>
> Signed-off-by: Bjorn Andersson
Reviewed-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> b/drivers/gpu/drm/msm/adreno/
statically setup by firmware).
>
> This is necessary on e.g. QCS6490 Rb3Gen2, in order to avoid "CP | AHB
> bus error"-errors from the GPU.
>
> Introduce a function to allow the msm driver to invoke this call.
>
> Signed-off-by: Bjorn Andersson
Reviewed-by: Ro
ting default vrend context
> if context_init is supported.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer
> Signed-off-by: Dmitry Osipenko
Reviewed-by: Rob Clark
> ---
> drivers/gpu/drm/virtio/virtgpu_gem.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
s explicit fencing.
>
> Signed-off-by: Dongwon Kim
> [dmitry.osipe...@collabora.com>: Edit commit message]
> Signed-off-by: Dmitry Osipenko
Reviewed-by: Rob Clark
> ---
> drivers/gpu/drm/virtio/virtgpu_plane.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --g
Hi Dave, Simona,
A second late pull for v6.13, mainly to get in big/churny but
mechanical (mass dp symbol renames and kerneldoc cleanups) changes to
avoid merge conflicts in the next cycle.
The following changes since commit 4a6fd06643afa99989a0e6b848e125099674227b:
Merge remote-tracking branc
On Mon, Oct 28, 2024 at 4:53 AM Mostafa Saleh wrote:
>
> Hi Rob,
>
> On Tue, Aug 27, 2024 at 11:17:08AM -0700, Rob Clark wrote:
> > From: Rob Clark
> >
> > This series extends io-pgtable-arm with a method to retrieve the page
> > table entries traversed in the
From: Rob Clark
In the case of iova fault triggered devcore dumps, include additional
debug information based on what we think is the current page tables,
including the TTBR0 value (which should match what we have in
adreno_smmu_fault_info unless things have gone horribly wrong), and
the
From: Rob Clark
This series extends io-pgtable-arm with a method to retrieve the page
table entries traversed in the process of address translation, and then
beefs up drm/msm gpu devcore dump to include this (and additional info)
in the devcore dump.
This is a respin of https
5P support
Puranam V G Tejaswi (2):
drm/msm/a6xx: Add support for A663
dt-bindings: display/msm/gmu: Add Adreno 663 GMU
Rob Clark (2):
drm/msm/a6xx+: Insert a fence wait before SMMU table update
Merge branch 'msm-fixes' into msm-next
Shen Lichuan (1):
drm/ms
On Fri, Sep 20, 2024 at 9:15 AM Akhil P Oommen wrote:
>
> On Wed, Sep 18, 2024 at 08:39:30AM -0700, Rob Clark wrote:
> > On Wed, Sep 18, 2024 at 12:46 AM Neil Armstrong
> > wrote:
> > >
> > > Hi,
> > >
> > > On 17/09/2024 13:14, Ant
r latency measurement purposes.
> >>
> >> Reviewed-by: Akhil P Oommen
> >> Tested-by: Rob Clark
> >> Tested-by: Neil Armstrong # on SM8650-QRD
> >> Tested-by: Neil Armstrong # on SM8550-QRD
> >> Tested-by: Neil Armstrong # on SM8450-HDK
> >> Signe
m merge_3d block
Jonathan Marek (2):
drm/msm/dsi: improve/fix dsc pclk calculation
drm/msm/dsi: fix 32-bit signed integer extension in pclk_rate calculation
Rob Clark (1):
drm/msm/a6xx+: Insert a fence wait before SMMU table update
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
On Thu, Sep 26, 2024 at 2:17 PM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
On Thu, Sep 26, 2024 at 2:17 PM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
From: Rob Clark
The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
devices (x1-85, possibly others), it seems to pass that barrier while
there are still things in the event completion FIFO waiting to be
written back to memory.
Work around that by adding a fence wait before
On Tue, Sep 24, 2024 at 8:22 AM Akhil P Oommen wrote:
>
> On Tue, Sep 24, 2024 at 07:47:12AM -0700, Rob Clark wrote:
> > On Tue, Sep 24, 2024 at 4:54 AM Antonino Maniscalco
> > wrote:
> > >
> > > On 9/20/24 7:09 PM, Akhil P Oommen wrote:
> > > >
nit, lowercase "a6xx" in subject prefix
(no need to resend just for this, I can fix it up when applying
patches if needed.. but if you do resend pls fix that)
BR
-R
On Tue, Sep 24, 2024 at 4:30 AM Antonino Maniscalco
wrote:
>
> Initialize with 4 rings to enable preemption.
>
> For now only on A
On Wed, Sep 18, 2024 at 9:51 AM Connor Abbott wrote:
>
> On Fri, Sep 13, 2024 at 8:51 PM Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
> > devices (x1-85, possibly others), it seems to p
On Tue, Sep 24, 2024 at 4:54 AM Antonino Maniscalco
wrote:
>
> On 9/20/24 7:09 PM, Akhil P Oommen wrote:
> > On Wed, Sep 18, 2024 at 09:46:33AM +0200, Neil Armstrong wrote:
> >> Hi,
> >>
> >> On 17/09/2024 13:14, Antonino Maniscalco wrote:
> >>> This series implements preemption for A7XX targets,
On Fri, Sep 20, 2024 at 9:54 AM Akhil P Oommen wrote:
>
> On Tue, Sep 17, 2024 at 01:14:19PM +0200, Antonino Maniscalco wrote:
> > Some userspace changes are necessary so add a flag for userspace to
> > advertise support for preemption when creating the submitqueue.
> >
> > When this flag is not s
On Fri, Sep 20, 2024 at 9:15 AM Akhil P Oommen wrote:
>
> On Wed, Sep 18, 2024 at 08:39:30AM -0700, Rob Clark wrote:
> > On Wed, Sep 18, 2024 at 12:46 AM Neil Armstrong
> > wrote:
> > >
> > > Hi,
> > >
> > > On 17/09/2024 13:14, Ant
On Wed, Sep 18, 2024 at 12:46 AM Neil Armstrong
wrote:
>
> Hi,
>
> On 17/09/2024 13:14, Antonino Maniscalco wrote:
> > This series implements preemption for A7XX targets, which allows the GPU to
> > switch to an higher priority ring when work is pushed to it, reducing
> > latency
> > for high pri
On Tue, Sep 17, 2024 at 4:37 PM Konrad Dybcio wrote:
>
> On 17.09.2024 5:30 PM, Rob Clark wrote:
> > On Tue, Sep 17, 2024 at 6:47 AM Konrad Dybcio
> > wrote:
> >>
> >> On 13.09.2024 9:51 PM, Rob Clark wrote:
> >>> From: Rob Clark
> >>
On Tue, Sep 17, 2024 at 6:47 AM Konrad Dybcio wrote:
>
> On 13.09.2024 9:51 PM, Rob Clark wrote:
> > From: Rob Clark
> >
> > The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
> > devices (x1-85, possibly others), it seems to pass that barrier while
From: Rob Clark
Fixes a race condition reported here:
https://github.com/AsahiLinux/linux/issues/309#issuecomment-2238968609
The whole premise of lockless access to a single-producer-single-
consumer queue is that there is just a single producer and single
consumer. That means we can't
From: Rob Clark
The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
devices (x1-85, possibly others), it seems to pass that barrier while
there are still things in the event completion FIFO waiting to be
written back to memory.
Work around that by adding a fence wait before
On Fri, Sep 13, 2024 at 10:03 AM Michel Dänzer
wrote:
>
> On 2024-09-13 18:53, Rob Clark wrote:
> > From: Rob Clark
> >
> > Fixes a race condition reported here:
> > https://github.com/AsahiLinux/linux/issues/309#issuecomment-2238968609
> >
> > The wh
From: Rob Clark
Fixes a race condition reported here:
https://github.com/AsahiLinux/linux/issues/309#issuecomment-2238968609
The whole premise of lockless access to a single-producer-single-
consumer queue is that there is just a single producer and single
consumer. That means we can't
On Fri, Sep 6, 2024 at 12:59 PM Akhil P Oommen wrote:
>
> On Thu, Sep 05, 2024 at 04:51:18PM +0200, Antonino Maniscalco wrote:
> > This series implements preemption for A7XX targets, which allows the GPU to
> > switch to an higher priority ring when work is pushed to it, reducing
> > latency
> >
On Mon, Sep 9, 2024 at 6:43 AM Connor Abbott wrote:
>
> On Mon, Sep 9, 2024 at 2:15 PM Antonino Maniscalco
> wrote:
> >
> > On 9/6/24 9:54 PM, Akhil P Oommen wrote:
> > > On Thu, Sep 05, 2024 at 04:51:22PM +0200, Antonino Maniscalco wrote:
> > >> This patch implements preemption feature for A6xx
On Mon, Sep 9, 2024 at 2:54 AM Dmitry Baryshkov
wrote:
>
> On Mon, 9 Sept 2024 at 10:50, Maxime Ripard wrote:
> >
> > Hi,
> >
> > On Tue, Jul 09, 2024 at 01:27:51AM GMT, Dmitry Baryshkov wrote:
> > > On Mon, 8 Jul 2024 at 21:38, Rob Clark wrote:
> &g
On Wed, Sep 4, 2024 at 6:39 AM Antonino Maniscalco
wrote:
>
> On 8/30/24 8:32 PM, Rob Clark wrote:
> > On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
> > wrote:
> >>
> >> Use the postamble to reset perf counters when switching between rings,
> >>
"qcom,hdmi-tx-8998" compatible
Otto Pflüger (1):
drm/msm/adreno: Add A306A support
Richard Acayan (1):
drm/msm/adreno: add a615 support
Rob Clark (1):
drm/msm: Remove unused pm_state
Sherry Yang (1):
drm/msm: fix %s null argument error
Vladimir Lypak (4):
drm/
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
On Fri, Aug 30, 2024 at 12:09 PM Connor Abbott wrote:
>
> On Fri, Aug 30, 2024 at 8:00 PM Rob Clark wrote:
> >
> > On Fri, Aug 30, 2024 at 11:54 AM Connor Abbott wrote:
> > >
> > > On Fri, Aug 30, 2024 at 7:08 PM Rob Clark wrote:
> > > >
On Fri, Aug 30, 2024 at 11:54 AM Connor Abbott wrote:
>
> On Fri, Aug 30, 2024 at 7:08 PM Rob Clark wrote:
> >
> > On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
> > wrote:
> > >
> > > This patch implements preemption feature for A6xx targets
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