On 12/30/24 7:41 PM, Andre Przywara wrote:
> On Fri, 27 Dec 2024 20:06:30 +0530
> Parthiban wrote:
>
>> On 12/27/24 6:30 PM, Parthiban Nallathambi wrote:
>>> This series depends on [1] for the eMMC/MMC controller to work and
>>> [2] (lined up for 6.14) which ad
On 12/27/24 6:30 PM, Parthiban Nallathambi wrote:
> This series depends on [1] for the eMMC/MMC controller to work and
> [2] (lined up for 6.14) which adds support for the sram nodes and
> display engine extends it's usage. Idea of this series to get initial
> feedback and adju
Some platforms like A100/A133 also uses pll-com clock as additional
clock source for the display clock. This is not documents both in
user manual and DE 2.0 specification. These changes are mainly from
vendor BSP.
Signed-off-by: Parthiban Nallathambi
---
.../devicetree/bindings/clock/allwinner
-by: Parthiban Nallathambi
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 3e28c32050e0..067820ab704d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers
A100/A133 comes with 2 x LVDS, 1 x DSI without TV support. Add
quirks with tv0 disabled. DSI support is not added.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
.
Signed-off-by: Parthiban Nallathambi
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index f2aa71206bc2..3e28c32050e0 100644
--- a/drivers
current implementation of tcon top assumes tv0 is always present, which
isn't case in A100/A133 SoC's. Make tv0 optional by introducing another
control similar to tv1 and make existing users with true/present.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_tcon_
Mixers in Allwinner A100/A133 have similar capabilities as others
SoCs with DE2. Add support for them.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers
Display Engine(DE2) in Allwinner A100/A133 has one mixers and tcon.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
A100/A133 has one 18 bit LCD / 2 x LVDS / 1 x DSI. All the controller
shares the same GPIO D block, where LVDS controller can co-exits.
Although 2 LVDS controller is available, there is no document details
for the second. Add compatible for a100 lcd controller.
Signed-off-by: Parthiban
Szbaijie Baijie Technology A133 helper board is an evaluation
board of their A133-Core SoM. Add its compatible (with the
SoM compatible) to the sunxi board DT binding file.
Signed-off-by: Parthiban Nallathambi
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++
1 file changed, 6
lvds, lcd, dsi all shares the same GPIO D bank and lvds0
data 3 lines and lvds1 pins are missed, add them.
Signed-off-by: Parthiban Nallathambi
---
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i
A133/A100 SoC doesn't have reset control from the CCU. Get reset
control line optionally.
Signed-off-by: Parthiban Nallathambi
---
drivers/iommu/sun50i-iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
Add entry for Shenzhen Baijie Technology (https://szbaijie.com)
Signed-off-by: Parthiban Nallathambi
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation
lvds in A100/A133 platform uses phy from DSI block, which needs
to be handled in phy driver. Add phy property to tcon with
generic name 'phy'.
Signed-off-by: Parthiban Nallathambi
---
.../devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml | 6 ++
1 file changed, 6
A100/A133 uses one mixer without rotation support, which is same
as sun8i v3s. Add it with fallback to v3s compatible.
Signed-off-by: Parthiban Nallathambi
---
.../devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml | 4
1 file changed, 4 insertions(+)
diff --git
a
A100/A133 comes with display enginer 2.0 with 1 x Mixer with write
back support and 1 tcon top. Mixer can be used with lcd/lvds/dsi,
but shares the same GPIO bank.
Signed-off-by: Parthiban Nallathambi
---
.../display/allwinner,sun4i-a10-display-engine.yaml | 2 ++
.../display/allwinner
iommu in a133/a100 does not have reset control. remove it
from required property to make it optional.
Signed-off-by: Parthiban Nallathambi
---
Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git
a/Documentation/devicetree
sunxi/20241109003739.3440904-1-masterr3c0rd@epochal.quest/
[2]:
https://lore.kernel.org/linux-sunxi/20241218-a100-syscon-v2-0-dae60b9ce192@epochal.quest/
Signed-off-by: Parthiban Nallathambi
---
Parthiban Nallathambi (22):
dt-bindings: iommu: sun50i: remove resets from required property
-by: Parthiban Nallathambi
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 3e28c32050e0..067820ab704d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers
A100/A133 comes with 2 x LVDS, 1 x DSI without TV support. Add
quirks with tv0 disabled. DSI support is not added.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
apart from the one in combo phy. MIPI got enable
control in analog 4 register which must be disabled when using
in LVDS mode.
Introduce set_mode in phy ops to control only for MIPI DSI.
Signed-off-by: Parthiban Nallathambi
---
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 23 +++--
.
Signed-off-by: Parthiban Nallathambi
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index f2aa71206bc2..3e28c32050e0 100644
--- a/drivers
current implementation of tcon top assumes tv0 is always present, which
isn't case in A100/A133 SoC's. Make tv0 optional by introducing another
control similar to tv1 and make existing users with true/present.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_tcon_
Mixers in Allwinner A100/A133 have similar capabilities as others
SoCs with DE2. Add support for them.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers
Display Engine(DE2) in Allwinner A100/A133 has one mixers and tcon.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
lvds, lcd, dsi all shares the same GPIO D bank and lvds0
data 3 lines and lvds1 pins are missed, add them.
Signed-off-by: Parthiban Nallathambi
---
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i
A133/A100 SoC doesn't have reset control from the CCU. Get reset
control line optionally.
Signed-off-by: Parthiban Nallathambi
---
drivers/iommu/sun50i-iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
Szbaijie Baijie Technology A133 helper board is an evaluation
board of their A133-Core SoM. Add its compatible (with the
SoM compatible) to the sunxi board DT binding file.
Signed-off-by: Parthiban Nallathambi
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++
1 file changed, 6
Add entry for Shenzhen Baijie Technology (https://szbaijie.com)
Signed-off-by: Parthiban Nallathambi
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation
A100/A133 has one 18 bit LCD / 2 x LVDS / 1 x DSI. All the controller
shares the same GPIO D block, where LVDS controller can co-exits.
Although 2 LVDS controller is available, there is no document details
for the second. Add compatible for a100 lcd controller.
Signed-off-by: Parthiban
lvds in A100/A133 platform uses phy from DSI block, which needs
to be handled in phy driver. Add phy property to tcon with
generic name 'phy'.
Signed-off-by: Parthiban Nallathambi
---
.../devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml | 6 ++
1 file changed, 6
A100/A133 comes with display enginer 2.0 with 1 x Mixer with write
back support and 1 tcon top. Mixer can be used with lcd/lvds/dsi,
but shares the same GPIO bank.
Signed-off-by: Parthiban Nallathambi
---
.../display/allwinner,sun4i-a10-display-engine.yaml | 2 ++
.../display/allwinner
A100/A133 uses one mixer without rotation support, which is same
as sun8i v3s. Add it with fallback to v3s compatible.
Signed-off-by: Parthiban Nallathambi
---
.../devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml | 4
1 file changed, 4 insertions(+)
diff --git
a
sunxi/20241109003739.3440904-1-masterr3c0rd@epochal.quest/
[2]:
https://lore.kernel.org/linux-sunxi/20241218-a100-syscon-v2-0-dae60b9ce192@epochal.quest/
Signed-off-by: Parthiban Nallathambi
---
Parthiban Nallathambi (22):
dt-bindings: iommu: sun50i: remove resets from required property
Some platforms like A100/A133 also uses pll-com clock as additional
clock source for the display clock. This is not documents both in
user manual and DE 2.0 specification. These changes are mainly from
vendor BSP.
Signed-off-by: Parthiban Nallathambi
---
.../devicetree/bindings/clock/allwinner
iommu in a133/a100 does not have reset control. remove it
from required property to make it optional.
Signed-off-by: Parthiban Nallathambi
---
Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git
a/Documentation/devicetree
the
> same time.
Agreed. But back to the original discussion about setting 0x20 to the port
register, it work fine in my end without that changes for A133 display pipeline
with LVDS. Not sure if the reason is independent DE.
Thanks,
Parthiban
On 11/26/24 2:59 PM, Philipp Zabel wrote:
> On Mo, 2024-11-25 at 22:07 +0530, Parthiban Nallathambi wrote:
>> On some platforms like Allwinner A133 with GE8300 includes
>> reset control from reset control unit. Add reset control
>> optionally from the devicetree.
>>
On 11/26/24 3:02 PM, Krzysztof Kozlowski wrote:
> On 26/11/2024 04:46, Parthiban wrote:
>> On 11/25/24 11:37 PM, Conor Dooley wrote:
>>> On Mon, Nov 25, 2024 at 10:07:03PM +0530, Parthiban Nallathambi wrote:
>>>> GE8300 in Allwinner A133 have reset control fro
://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/5
Signed-off-by: Parthiban Nallathambi
---
Parthiban Nallathambi (2):
dt-bindings: gpu: add reset control property
drm/imagination: add reset control support
.../devicetree/bindings/gpu/img,powervr-rogue.yaml | 3 +++
drivers/gpu/drm
On some platforms like Allwinner A133 with GE8300 includes
reset control from reset control unit. Add reset control
optionally from the devicetree.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/imagination/pvr_device.h | 8
drivers/gpu/drm/imagination/pvr_drv.c| 5
GE8300 in Allwinner A133 have reset control from the ccu.
Add the resets property as optional one to control it.
Signed-off-by: Parthiban Nallathambi
---
Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree
r GE8300 in Allwinner A133 is organized with core, bus and additional
pll as
input. Where "bus" controlled as gate clock and optionally using pll.
If am not wrong, GE8300 also comes under rogue architecture without mem and sys
clocks.
Does this needs to be considered into separ
On 11/25/24 11:37 PM, Conor Dooley wrote:
> On Mon, Nov 25, 2024 at 10:07:03PM +0530, Parthiban Nallathambi wrote:
>> GE8300 in Allwinner A133 have reset control from the ccu.
>> Add the resets property as optional one to control it.
>
> There's no specific compatible
On 11/13/24 5:03 AM, John Watts wrote:
> Hi there,
>
> On Tue, Nov 12, 2024 at 10:43:44PM +0530, Parthiban wrote:
>> #define TCON_TOP_PORT_DE0_MSK GENMASK(1, 0)
>> #define TCON_TOP_PORT_DE1_MSK GENMASK(5, 4)
>>
>> references tow
On 11/12/24 5:27 PM, John Watts wrote:
> Hey everyone,
>
> I'm not sure exactly where to add this but I discussed some of this with
> Parthiban on #linux-sunxi a few days ago, so I want to write it down
> before I work on the next version of the patch.
>
> I had ass
lection, which fails to work? Not sure,
may be disabling CORE1_SCLK_GATE and CORE1_HCLK_GATE in de2-clk helps.
With A133 following the same as T113 with single mixer without TV, still
sets 0x20 in vendor kernel.
copied from R40:
Note: The priority of DE0 is higher than DE1.
If TCON_LCD0 selects DE0 and DE1 as source at the same time, then
DE0 will be used for the source of TCON_LCD0.
Thanks,
Parthiban
>
>>
>> Cheers,
>> Andre
>
> Thanks,
> John Watts
>
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