ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB
bridge")
Cc: # 6.12.x, 6.6.x
Signed-off-by: Nikolaus Voss
---
v2:
- use .atomic_check() instead of .mode_fixup() (Dmitry Baryshkov)
- add Fixes tag (Liu Ying)
- use fsl_ldb_link_frequency() and drop const qualifier for
struc
Hi Marek,
On 09.12.2024 22:46, Marek Vasut wrote:
On 12/9/24 9:46 AM, Nikolaus Voss wrote:
and store the panel's timing in EDID EEPROM.
Oh, that is a new one. Does the EDID EEPROM store the entirety of
'struct display_timing {}' somehow , or is that a custom format ?
Well, so
Hi Marek,
On 09.12.2024 22:51, Marek Vasut wrote:
On 12/9/24 10:27 AM, Nikolaus Voss wrote:
On 07.12.2024 12:46, Marek Vasut wrote:
On 12/4/24 11:40 AM, Nikolaus Voss wrote:
LDB clock has to be a fixed multiple of the pixel clock.
As LDB and pixel clock are derived from different clock
On 07.12.2024 12:46, Marek Vasut wrote:
On 12/4/24 11:40 AM, Nikolaus Voss wrote:
LDB clock has to be a fixed multiple of the pixel clock.
As LDB and pixel clock are derived from different clock sources
Can you please share the content of /sys/kernel/debug/clk/clk_summary
?
Sure. Without
Hi Marek,
On 07.12.2024 12:30, Marek Vasut wrote:
On 12/4/24 11:55 AM, Nikolaus Voss wrote:
I doubt that pixel clock tree cannot find appropriate division
ratios
for some pixel clock rates, especially for dual-link LVDS on
i.MX8MP
and i.MX93 platforms, because PLL clock rate should be 7x
Hi Miquèl,
On 06.12.2024 15:08, Miquel Raynal wrote:
On 03/12/2024 at 20:09:52 +01, Nikolaus Voss wrote:
LDB clock has to be a fixed multiple of the pixel clock.
Not only, IIUC it also needs to be synchronized, ie. share the same
source.
As LDB and pixel clock are derived from different
ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB
bridge")
Cc:
Signed-off-by: Nikolaus Voss
---
v2:
- use .atomic_check() instead of .mode_fixup() (Dmitry Baryshkov)
- add Fixes tag (Liu Ying)
- use fsl_ldb_link_frequency() and drop const qualifier for
struct fsl_ldb* (
Hi Marek,
On 04.12.2024 00:40, Marek Vasut wrote:
On 12/3/24 8:20 AM, Nikolaus Voss wrote:
On 03.12.2024 04:12, Marek Vasut wrote:
On 12/3/24 3:22 AM, Liu Ying wrote:
[...]
I doubt that pixel clock tree cannot find appropriate division
ratios
for some pixel clock rates, especially for dual
Hi Marek,
On 03.12.2024 21:15, Marek Vasut wrote:
On 12/3/24 8:09 PM, Nikolaus Voss wrote:
LDB clock has to be a fixed multiple of the pixel clock.
As LDB and pixel clock are derived from different clock sources
Can you please share the content of /sys/kernel/debug/clk/clk_summary ?
Sure
this condition in .atomic_check() and
adapt the pixel clock accordingly.
Cc:
Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB
bridge")
Signed-off-by: Nikolaus Voss
---
v2:
- use .atomic_check() instead of .mode_fixup() (Dmitry Baryshkov)
- add Fixes tag
On 03.12.2024 03:22, Liu Ying wrote:
On 12/02/2024, Nikolaus Voss wrote:
[You don't often get email from n...@vosn.de. Learn why this is
important at https://aka.ms/LearnAboutSenderIdentification ]
Hi Liu,
Hi,
On 02.12.2024 07:32, Liu Ying wrote:
On 11/27/2024, Nikolaus Voss wrote:
rt unnecessary.
That is exactly what my patch is about. I want to use one DT for all
panels and store the panel's timing in EDID EEPROM.
--
Nikolaus Voss
On 02.12.2024 13:56, Marek Vasut wrote:
On 12/2/24 7:32 AM, Liu Ying wrote:
On 11/27/2024, Nikolaus Voss wrote:
LDB clock has to be a fixed multiple of the pixel clock.
As LDB and pixel clock are derived from different clock sources
(at least on imx8mp), this constraint cannot be satisfied for
Hi Liu,
On 02.12.2024 07:32, Liu Ying wrote:
On 11/27/2024, Nikolaus Voss wrote:
LDB clock has to be a fixed multiple of the pixel clock.
As LDB and pixel clock are derived from different clock sources
(at least on imx8mp), this constraint cannot be satisfied for
any pixel clock, which leads
Hi Dmitry,
On Sat, 30 Nov 2024, Dmitry Baryshkov wrote:
On Tue, Nov 26, 2024 at 04:45:54PM +0100, Nikolaus Voss wrote:
LDB clock has to be a fixed multiple of the pixel clock.
As LDB and pixel clock are derived from different clock sources
(at least on imx8mp), this constraint cannot be
this condition in mode_fixup() and
adapt the pixel clock accordingly.
Cc:
Signed-off-by: Nikolaus Voss
---
drivers/gpu/drm/bridge/fsl-ldb.c | 40
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm
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