Re: [PATCH v5 RESEND 2/2] i2c: i2c-qcom-geni: Add Block event interrupt support

2025-02-12 Thread Mukesh Kumar Savaliya
100 kHz. BEI optimizations are currently implemented for I2C write transfers only, as there is no use case for multiple I2C read messages in a single transfer at this time. Acked-by: Mukesh Kumar Savaliya Signed-off-by: Jyothi Kumar Seerapu --- v4 -> v5: - Block event interrupt flag nam

Re: [PATCH v5 RESEND 1/2] dmaengine: qcom: gpi: Add GPI Block event interrupt support

2025-02-12 Thread Mukesh Kumar Savaliya
expected for the first 7 message completions, only the last message triggers an interrupt, indicating the completion of 8 messages. This BEI mechanism enhances overall transfer efficiency. Acked-by: Mukesh Kumar Savaliya Signed-off-by: Jyothi Kumar Seerapu --- v4 -> v5: - BEI flag nam

Re: [PATCH v4 2/2] i2c: i2c-qcom-geni: Add Block event interrupt support

2025-01-13 Thread Mukesh Kumar Savaliya
On 1/7/2025 4:09 PM, Jyothi Kumar Seerapu wrote: On 1/7/2025 11:33 AM, Mukesh Kumar Savaliya wrote: On 12/17/2024 10:34 PM, Jyothi Kumar Seerapu wrote: The I2C driver gets an interrupt upon transfer completion. When handling multiple messages in a single transfer, this results in N

Re: [PATCH v4 2/2] i2c: i2c-qcom-geni: Add Block event interrupt support

2025-01-06 Thread Mukesh Kumar Savaliya
On 12/17/2024 10:34 PM, Jyothi Kumar Seerapu wrote: The I2C driver gets an interrupt upon transfer completion. When handling multiple messages in a single transfer, this results in N interrupts for N messages, leading to significant software interrupt latency. To mitigate this latency, utiliz

Re: [PATCH v4 1/2] dmaengine: qcom: gpi: Add GPI Block event interrupt support

2025-01-06 Thread Mukesh Kumar Savaliya
On 12/17/2024 10:34 PM, Jyothi Kumar Seerapu wrote: GSI hardware generates an interrupt for each transfer completion. For multiple messages within a single transfer, this results in N interrupts for N messages, leading to significant software interrupt latency. To mitigate this latency, utili