ruct host1x *host1x);
void host1x_debug_dump(struct host1x *host1x);
-void host1x_debug_dump_syncpts(struct host1x *host1x);
#endif
Acked-by: Mikko Perttunen
From: Mikko Perttunen
Syncpoint IRQs are currently requested in a code path that runs
during resume. Due to this, we get multiple overlapping registered
interrupt handlers as host1x is suspended and resumed.
Rearrange interrupt code to only request IRQs during initialization.
Signed-off-by
From: Mikko Perttunen
These tables contain fixed values to program the host1x hardware
with, so fill in the missing entries.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 150 +++
1 file changed, 72 insertions(+), 78 deletions(-)
diff --git
From: Mikko Perttunen
Timing can be wonky on pre-silicon platforms, so disable fence timeouts
on pre-silicon platforms.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/fence.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/host1x/fence.c b/drivers/gpu/host1x
From: Mikko Perttunen
Add class IDs / MLOCKs for MLOCK recovery for rest of engines
present on Tegra234.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/cdma_hw.c | 12
include/linux/host1x.h | 5 +
2 files changed, 17 insertions(+)
diff --git a/drivers
From: Mikko Perttunen
Some of the _writel functions in dev.h had the r and v parameters
swapped. Fix this to avoid confusion.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/host1x/dev.h b
From: Mikko Perttunen
During channel debug information dump, when printing CDMA
opcodes, the circular nature of the CDMA pushbuffer wasn't being
taken into account, sometimes accessing past the end. Change
the printing to take this into account.
Signed-off-by: Mikko Perttunen
---
driver
From: Mikko Perttunen
The dma-buf import code currently attaches and maps all imported
dma-bufs to the drm device to get their sgt for mapping to the
directly managed IOMMU domain.
In many cases, like for newer chips (Tegra186+), the directly
managed IOMMU domain is, however, not used. Mapping
From: Mikko Perttunen
Since we aren't using drm_gem_prime_import(_dev), for clarity don't
use the corresponding destroy function either.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/gem.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
On 2/23/24 03:06, Thierry Reding wrote:
On Thu Feb 22, 2024 at 2:05 AM CET, Mikko Perttunen wrote:
From: Mikko Perttunen
On Tegra186, secure world applications may need to access host1x
during suspend/resume, and rely on the kernel to keep Host1x out
of reset during the suspend cycle. As such
From: Mikko Perttunen
On Tegra186, secure world applications may need to access host1x
during suspend/resume, and rely on the kernel to keep Host1x out
of reset during the suspend cycle. As such, as a quirk,
skip asserting Host1x's reset on Tegra186.
We don't need to keep the clocks e
On 2/16/24 19:02, Thierry Reding wrote:
On Wed Feb 14, 2024 at 12:40 PM CET, Mikko Perttunen wrote:
From: Mikko Perttunen
On Tegra186, other software components may rely on the kernel to
keep Host1x operational even during suspend. As such, as a quirk,
skip asserting Host1x's res
From: Mikko Perttunen
On Tegra186, other software components may rely on the kernel to
keep Host1x operational even during suspend. As such, as a quirk,
skip asserting Host1x's reset on Tegra186.
We don't need to keep the clocks enabled, as BPMP ensures the clock
stays on while Host1
From: Mikko Perttunen
UBSAN reports an invalid load for bool, as the iosys_map is read
later without being initialized. Zero-initialize it to avoid this.
Reported-by: Ashish Mhetre
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/gem.c | 2 +-
1 file changed, 1 insertion(+), 1
ned-off-by: Johnny Liu
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/context.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/host1x/context.c b/drivers/gpu/host1x/context.c
index a3f336edd991..955c971c528d 100644
--- a/drivers/gpu/host1x/context.c
+++ b/d
From: Mikko Perttunen
Support sharded syncpoint interrupts on Tegra234+. This feature
allows specifying one of eight interrupt lines for each syncpoint
to lower processing latency of syncpoint threshold
interrupts.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c| 28
From: Mikko Perttunen
Before going into suspend, wait all CDMA to go idle and stop it.
This will ensure no channel is still active while we enter
suspend, and ensures the driver doesn't think that CDMA is still
active when coming back from suspend (as HW state has been reset).
Signed-o
From: Mikko Perttunen
With the previous CDMA stop fix, executing runtime PM ops around
system suspend now makes channel submissions work after system
suspend, so do that.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Mikko Perttunen
Add locking around channel allocation to avoid race conditions.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/channel.c | 7 +++
drivers/gpu/host1x/channel.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/host1x/channel.c b/drivers/gpu
On 7/25/23 10:46, Mikko Perttunen wrote:
From: Mikko Perttunen
dma_fence_get_status is not guaranteed to return valid information
on if the fence has been signaled or not if SW signaling has not
been enabled for the fence. To ensure valid information is reported,
enable SW signaling for fences
On 8/30/23 13:19, Thomas Zimmermann wrote:
Hi
Am 25.08.23 um 15:22 schrieb Thierry Reding:
From: Thierry Reding
Tegra DRM doesn't support display on Tegra234 and later, so make sure
not to remove any existing framebuffers in that case.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/teg
On 8/22/23 10:15, Jinjie Ruan wrote:
Return PTR_ERR_OR_ZERO() instead of return 0 or PTR_ERR() to
simplify code.
Signed-off-by: Jinjie Ruan
---
drivers/gpu/drm/tegra/drm.c | 5 +
drivers/gpu/drm/tegra/gem.c | 5 +
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/driver
From: Mikko Perttunen
dma_fence_get_status is not guaranteed to return valid information
on if the fence has been signaled or not if SW signaling has not
been enabled for the fence. To ensure valid information is reported,
enable SW signaling for fences before getting their status.
Signed-off
From: Mikko Perttunen
Currently, engine drivers only enable runtime PM during the host1x
init callback. This can happen slightly later than the probe, which
can cause the power domain to intermittently not be turned off after
probe.
My hypothesis is that there is a race condition between the
From: Mikko Perttunen
The return value for tegra_drm_alloc was missing an error check.
Add one.
Reported-by: Dan Carpenter
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/nvdec.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm
From: Mikko Perttunen
If a context device was not attached to IOMMU, we kept the old
success err value causing context devices to be unregistered but
success to be returned. This would mean that things would go on
but with context isolation disabled.
To decide on an explicit behavior, let&#
i: Clear enable register if powered by bootloader
Lee Jones (1):
drm/tegra: dc: Remove set but unused variable 'state'
Mikko Perttunen (1):
gpu: host1x: Don't rely on dma_fence_wait_timeout return value
Nur Hussein (1):
drm/tegra: Avoid potential 32-bit integ
From: Mikko Perttunen
dma_fence_wait_timeout (along with a host of other jiffies-based
timeouting functions) returns zero both in case of timeout and when
the wait completes during the last jiffy before timeout. As such,
we can't rely on it to distinguish between success and timeout.
To pr
On 2/16/23 15:19, Stanislaw Gruszka wrote:
Hi
On Thu, Feb 16, 2023 at 02:37:15AM +0100, Jesper Juhl wrote:
From 4fe34831e2e7677b1c9616356f0a2e0a36ec092f Mon Sep 17 00:00:00 2001
From: Jesper Juhl
Date: Thu, 16 Feb 2023 02:33:05 +0100
Subject: [PATCH] Don't test for NULL firmware before releas
pt_irq < 0)
+ return host->syncpt_irq;
mutex_init(&host->devices_lock);
INIT_LIST_HEAD(&host->devices);
--
2.39.0
Thanks both for the fix :)
FWIW,
Reviewed-by: Mikko Perttunen
From: Mikko Perttunen
The code to write the syncpoint channel assignment register
incorrectly skips the write if hypervisor registers are not available.
The register, however, is within the guest aperture so remove the
check and assign syncpoints properly even on virtualized systems.
Fixes
From: Mikko Perttunen
In the IMM opcode check, don't call is_addr_reg if it's not set.
Fixes: 8cc95f3fd35e ("drm/tegra: Add job firewall")
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/firewall.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/d
From: Mikko Perttunen
Ensure appropriate configuration is done to make the host1x device
and context devices DMA coherent by adding the dma-coherent flag.
Fixes: b35f5b53a87b ("arm64: tegra: Add context isolation domains on Tegra234")
Signed-off-by: Mikko Perttunen
---
arch/arm6
From: Mikko Perttunen
On Tegra186+, the syncpoint ID has 10 bits of space. To allow
using more than 256 syncpoints, fix the mask.
Fixes: 9abdd497cd0a ("gpu: host1x: Tegra234 device data and headers")
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/hw_host1x06_uclass.h | 2 +
From: Mikko Perttunen
In anticipation of removal of the intr API, implement job tracking
using DMA fences instead. The main two things about this are
making cdma_update schedule the work since fence completion can
now be called from interrupt context, and some complication in
ensuring the
From: Mikko Perttunen
Currently all fences have a 30 second timeout to ensure they are
cleaned up if the fence never completes otherwise. However, this
one size fits all solution doesn't actually fit in every case,
such as syncpoint waiting where we want to be able to have timeouts
longer
From: Mikko Perttunen
Move from the old, complex intr handling code to a new implementation
based on dma_fences. While there is a fair bit of churn to get there,
the new implementation is much simpler and likely faster as well due
to allowing signaling directly from interrupt context.
Signed
From: Mikko Perttunen
In anticipation of removal of the intr API, move host1x_syncpt_wait
to use DMA fences instead. As of this patch, this means that waits
have a 30 second maximum timeout because of the implicit timeout
we have with fences, but that will be lifted in a follow-up patch.
Signed
On 12/30/22 12:01, Mikko Perttunen wrote:
On 12/30/22 11:15, Stanislaw Gruszka wrote:
On Wed, Dec 28, 2022 at 03:17:59PM +0200, Mikko Perttunen wrote:
On 12/28/22 15:08, Deepak R Varma wrote:
On Wed, Dec 28, 2022 at 02:28:54PM +0200, Mikko Perttunen wrote:
On 12/27/22 19:14, Deepak R Varma
On 12/30/22 11:15, Stanislaw Gruszka wrote:
On Wed, Dec 28, 2022 at 03:17:59PM +0200, Mikko Perttunen wrote:
On 12/28/22 15:08, Deepak R Varma wrote:
On Wed, Dec 28, 2022 at 02:28:54PM +0200, Mikko Perttunen wrote:
On 12/27/22 19:14, Deepak R Varma wrote:
kfree() & vfree() internally per
On 12/28/22 15:34, Deepak R Varma wrote:
On Wed, Dec 28, 2022 at 03:17:59PM +0200, Mikko Perttunen wrote:
On 12/28/22 15:08, Deepak R Varma wrote:
On Wed, Dec 28, 2022 at 02:28:54PM +0200, Mikko Perttunen wrote:
On 12/27/22 19:14, Deepak R Varma wrote:
kfree() & vfree() internally per
On 12/28/22 15:08, Deepak R Varma wrote:
On Wed, Dec 28, 2022 at 02:28:54PM +0200, Mikko Perttunen wrote:
On 12/27/22 19:14, Deepak R Varma wrote:
kfree() & vfree() internally perform NULL check on the pointer handed
to it and take no action if it indeed is NULL. Hence there is no need
f
On 12/27/22 19:14, Deepak R Varma wrote:
kfree() & vfree() internally perform NULL check on the pointer handed
to it and take no action if it indeed is NULL. Hence there is no need
for a pre-check of the memory pointer before handing it to
kfree()/vfree().
Issue reported by ifnullfree.cocci Cocc
On 12/1/22 03:55, zys.zlj...@gmail.com wrote:
From: Yushan Zhou
Fix the following coccicheck warning:
./drivers/gpu/host1x/fence.c:97:2-7: WARNING:
NULL check before some freeing functions is not needed.
Signed-off-by: Yushan Zhou
---
drivers/gpu/host1x/fence.c | 3 +--
1 file changed, 1 i
On 9/21/22 21:37, Krzysztof Kozlowski wrote:
On 20/09/2022 10:11, Mikko Perttunen wrote:
From: Mikko Perttunen
On Tegra234 NVDEC firmware is loaded from a secure carveout, where it
has been loaded by a bootloader. When booting NVDEC, we need to tell it
the address of this firmware, which we
On 9/21/22 10:26, Krzysztof Kozlowski wrote:
On 20/09/2022 10:11, Mikko Perttunen wrote:
From: Mikko Perttunen
v3:
* Updated patch 3 based on comments
v2:
* Updated patches 1,3 based on comments
* Added Acked-by to patch 2
Original message:
Hi all,
this series adds support for the HW
From: Mikko Perttunen
NVDEC on Tegra234 requires multiple clocks. Add support for that.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/nvdec.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/tegra/nvdec.c b
From: Mikko Perttunen
On Tegra234 NVDEC firmware is loaded from a secure carveout, where it
has been loaded by a bootloader. When booting NVDEC, we need to tell it
the address of this firmware, which we can determine by checking the
starting address of the carveout. As such, add an MC API to
From: Mikko Perttunen
Add helper code for booting RISC-V based engines where firmware is
located in a carveout.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/Makefile | 3 +-
drivers/gpu/drm/tegra/riscv.c | 106 +
drivers/gpu/drm/tegra/riscv.h
From: Mikko Perttunen
Add clock, memory controller, powergate and reset dt-binding headers
necessary for NVDEC.
Signed-off-by: Mikko Perttunen
Acked-by: Krzysztof Kozlowski
---
include/dt-bindings/clock/tegra234-clock.h | 4
include/dt-bindings/memory/tegra234-mc.h | 3
From: Mikko Perttunen
Add support for the Tegra234 version of NVDEC to the NVDEC driver.
This version sports a RISC-V controller and requires a few additional
clocks. After firmware has been loaded, the behavior is, however,
backwards compatible.
Signed-off-by: Mikko Perttunen
---
drivers/gpu
From: Mikko Perttunen
Update NVDEC bindings for Tegra234. This new engine version only has
two memory clients, but now requires three clocks, and as a bigger
change the engine loads firmware from a secure carveout configured by
the bootloader.
For the latter, we need to add a phandle to the
From: Mikko Perttunen
Add entries for NVDEC to the Tegra234 SID table.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 0cd3f97e7e49..d6b4614f968f 100644
From: Mikko Perttunen
Add a device tree node for NVDEC on Tegra234.
Booting the firmware requires some information regarding offsets
within the firmware binary. These are passed through the device
tree, but since the values vary depending on the firmware version,
and the firmware itself is not
From: Mikko Perttunen
v3:
* Updated patch 3 based on comments
v2:
* Updated patches 1,3 based on comments
* Added Acked-by to patch 2
Original message:
Hi all,
this series adds support for the HW video decoder, NVDEC,
on Tegra234 (Orin). The main change is a switch from Falcon
to RISC-V for
On 9/14/22 15:08, Rob Herring wrote:
On Tue, Sep 13, 2022 at 04:14:41PM +0300, Mikko Perttunen wrote:
From: Mikko Perttunen
Update NVDEC bindings for Tegra234. This new engine version only has
two memory clients, but now requires three clocks, and as a bigger
change the engine loads firmware
From: Mikko Perttunen
Update NVDEC bindings for Tegra234. This new engine version only has
two memory clients, but now requires three clocks, and as a bigger
change the engine loads firmware from a secure carveout configured by
the bootloader.
For the latter, we need to add a phandle to the
From: Mikko Perttunen
Add helper code for booting RISC-V based engines where firmware is
located in a carveout.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/Makefile | 3 +-
drivers/gpu/drm/tegra/riscv.c | 106 +
drivers/gpu/drm/tegra/riscv.h
From: Mikko Perttunen
On Tegra234 NVDEC firmware is loaded from a secure carveout, where it
has been loaded by a bootloader. When booting NVDEC, we need to tell it
the address of this firmware, which we can determine by checking the
starting address of the carveout. As such, add an MC API to
From: Mikko Perttunen
v2:
* Updated patches 1,3 based on comments
* Added Acked-by to patch 2
Original message:
Hi all,
this series adds support for the HW video decoder, NVDEC,
on Tegra234 (Orin). The main change is a switch from Falcon
to RISC-V for the internal microcontroller, which
From: Mikko Perttunen
NVDEC on Tegra234 requires multiple clocks. Add support for that.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/nvdec.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/tegra/nvdec.c b
From: Mikko Perttunen
Add entries for NVDEC to the Tegra234 SID table.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 0cd3f97e7e49..d6b4614f968f 100644
From: Mikko Perttunen
Add clock, memory controller, powergate and reset dt-binding headers
necessary for NVDEC.
Signed-off-by: Mikko Perttunen
Acked-by: Krzysztof Kozlowski
---
include/dt-bindings/clock/tegra234-clock.h | 4
include/dt-bindings/memory/tegra234-mc.h | 3
From: Mikko Perttunen
Add support for the Tegra234 version of NVDEC to the NVDEC driver.
This version sports a RISC-V controller and requires a few additional
clocks. After firmware has been loaded, the behavior is, however,
backwards compatible.
Signed-off-by: Mikko Perttunen
---
drivers/gpu
From: Mikko Perttunen
Add a device tree node for NVDEC on Tegra234.
Booting the firmware requires some information regarding offsets
within the firmware binary. These are passed through the device
tree, but since the values vary depending on the firmware version,
and the firmware itself is not
On 7.9.2022 13.58, Krzysztof Kozlowski wrote:
On 07/09/2022 07:27, Mikko Perttunen wrote:
On 9/6/22 20:50, Krzysztof Kozlowski wrote:
On 06/09/2022 15:28, Mikko Perttunen wrote:
From: Mikko Perttunen
Hi all,
this series adds support for the HW video decoder, NVDEC,
on Tegra234 (Orin). The
From: Mikko Perttunen
Add Host1x context isolation domains on Tegra234. On Tegra234 we have
two IOMMUs that are connected to Host1x-channel programmed engines,
so we have to include domains for each of them.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 19
From: Mikko Perttunen
Add defines for stream IDs used for Host1x context isolation
on Tegra234. The same stream IDs are used for both NISO0 and
NISO1 SMMUs since Host1x's stream ID protection tables don't
make a distinction between the two.
Signed-off-by: Mikko Perttunen
---
From: Mikko Perttunen
On Tegra234, engines that are programmed through Host1x channels can
be attached to either the NISO0 or NISO1 SMMU. Because of that, when
selecting a context device to use with an engine, we need to select
one that is also attached to the same SMMU.
Add a parameter to
From: Mikko Perttunen
Hi all,
this series adds support for Host1x context isolation
on Tegra234 (Orin). The difference from previous generations
is that there are two IOMMUs to which engines can be attached
to, resulting in having to have a set of contexts for each one.
Patches should be
On 9/6/22 20:50, Krzysztof Kozlowski wrote:
On 06/09/2022 15:28, Mikko Perttunen wrote:
From: Mikko Perttunen
Hi all,
this series adds support for the HW video decoder, NVDEC,
on Tegra234 (Orin). The main change is a switch from Falcon
to RISC-V for the internal microcontroller, which brings
From: Mikko Perttunen
Update NVDEC bindings for Tegra234. This new engine version only has
two memory clients, but now requires three clocks, and as a bigger
change the engine loads firmware from a secure carveout configured by
the bootloader.
For the latter, we need to add a phandle to the
From: Mikko Perttunen
Add clock, memory controller, powergate and reset dt-binding headers
necessary for NVDEC.
Signed-off-by: Mikko Perttunen
---
include/dt-bindings/clock/tegra234-clock.h | 4
include/dt-bindings/memory/tegra234-mc.h | 3 +++
include/dt-bindings/power
From: Mikko Perttunen
On Tegra234 NVDEC firmware is loaded from a secure carveout, where it
has been loaded by a bootloader. When booting NVDEC, we need to tell it
the address of this firmware, which we can determine by checking the
starting address of the carveout. As such, add an MC API to
From: Mikko Perttunen
Hi all,
this series adds support for the HW video decoder, NVDEC,
on Tegra234 (Orin). The main change is a switch from Falcon
to RISC-V for the internal microcontroller, which brings along
a change in how the engine is booted. Otherwise it is backwards
compatible with
From: Mikko Perttunen
Add a device tree node for NVDEC on Tegra234.
Booting the firmware requires some information regarding offsets
within the firmware binary. These are passed through the device
tree, but since the values vary depending on the firmware version,
and the firmware itself is not
From: Mikko Perttunen
Add entries for NVDEC to the Tegra234 SID table.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 0cd3f97e7e49..d6b4614f968f 100644
From: Mikko Perttunen
NVDEC on Tegra234 requires multiple clocks. Add support for that.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/nvdec.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/tegra/nvdec.c b
From: Mikko Perttunen
Add helper code for booting RISC-V based engines where firmware is
located in a carveout.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/Makefile | 3 +-
drivers/gpu/drm/tegra/riscv.c | 106 +
drivers/gpu/drm/tegra/riscv.h
From: Mikko Perttunen
Add support for the Tegra234 version of NVDEC to the NVDEC driver.
This version sports a RISC-V controller and requires a few additional
clocks. After firmware has been loaded, the behavior is, however,
backwards compatible.
Signed-off-by: Mikko Perttunen
---
drivers/gpu
From: Mikko Perttunen
During the refactoring of channel_submit, assignment of syncval
was moved but it is also used in channel_submit. Add this assignment
back to channel_submit as well.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/channel_hw.c | 1 +
1 file changed, 1 insertion
From: Mikko Perttunen
host1x_cdma_push_wide had the assumptions that the last parameter word
was a NOP opcode, and that NOP opcodes could be used in all situations.
Neither are true with the new job opcode sequence, so adjust the
function to not have these assumptions, and instead place an
t;bus type registration failed: %d\n", err);
Reviewed-by: Mikko Perttunen
Cheers,
Mikko
From: Mikko Perttunen
Host1x on Tegra234 does not have a software-controllable reset line.
As such, don't bail out if we don't find one in the device tree.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/
From: Mikko Perttunen
Add Host1x context stream IDs on systems that support Host1x context
isolation. Host1x and attached engines can use these stream IDs to
allow isolation between memory used by different processes.
The specified stream IDs must match those configured by the hypervisor,
if
From: Mikko Perttunen
With the full-featured opcode sequence using MLOCKs, we need to also
unlock those MLOCKs in the event of a timeout. However, it turns out
that on Tegra186/Tegra194, by default, we don't need to do this;
furthermore, on Tegra234 it is much simpler to do; so only impl
From: Mikko Perttunen
Host1x class information and opcodes are unchanged or backwards
compatible across SoCs so let's not duplicate them for each one
but have them in a shared header file.
At the same time, add opcode functions for acquire/release_mlock.
Signed-off-by: Mikko Pert
From: Mikko Perttunen
The DMACTX field determines which context, as specified in the
TRANSCFG register, is used. While during boot it doesn't matter
which is used, later on it matters and this value is reused by
the firmware.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/fal
From: Mikko Perttunen
The bracketing for the interrupts property in the device tree
example is incorrect. Fix it.
Signed-off-by: Mikko Perttunen
---
.../bindings/display/tegra/nvidia,tegra20-host1x.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
a
From: Mikko Perttunen
On Tegra234, each Host1x VM has 8 interrupt lines. Each syncpoint
can be configured with which interrupt line should be used for
threshold interrupt, allowing for load balancing.
For now, to keep backwards compatibility, just set all syncpoints
to the first interrupt
From: Mikko Perttunen
When MLOCK enforcement is enabled, the 0-word write currently done
is rejected by the hardware outside of an MLOCK region. As such,
on these chips, which also have the newer, more convenient RESTART_W
opcode, use that instead to skip over the timed out job.
Signed-off-by
From: Mikko Perttunen
Integrated the Host1x context isolation series (patches 1 to 8) and
Tegra234 support series (patches 9 to 22) in one email thread for
the benefit of automatic testers.
Changes from previous versions:
Context isolation:
* Improved check to ensure context devices are
From: Mikko Perttunen
Add Tegra234 support for VIC. It is backwards compatible with
Tegra194.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 1 +
drivers/gpu/drm/tegra/vic.c | 12
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/tegra/drm.c b
From: Mikko Perttunen
Add code to register context devices from device tree, allocate them
out and manage their refcounts.
Signed-off-by: Mikko Perttunen
---
v2:
* Directly set DMA mask instead of inheriting from Host1x.
* Use iommu-map instead of custom DT property.
v4:
* Use u64 instead of
From: Mikko Perttunen
Program virtualization tables specifying which VMs have access to which
Host1x hardware resources. Programming these has become mandatory in
Tegra234.
For now, since the driver does not operate as a Host1x hypervisor, we
basically allow access to everything to everyone
From: Mikko Perttunen
Update VIC and Host1x bindings for changes in Tegra234.
Namely,
- New compatible strings
- Sharded syncpoint interrupts
- Optional reset.
Also, fix the order of descriptions for VM/hypervisor
register apertures -- while the reg-names specification
was correct, the
From: Mikko Perttunen
Implement the get_streamid_offset and can_use_memory_ctx callbacks
required for supporting context isolation. Since old firmware on VIC
cannot support context isolation without hacks that we don't want to
implement, check the firmware binary to see if context isol
From: Mikko Perttunen
For engines that support context isolation, allocate a context when
opening a channel, and set up stream ID offset and context fields
when submitting a job.
As of this commit, the stream ID offset and fallback stream ID
are not used when context isolation is disabled
From: Mikko Perttunen
Refactor 'regs' property loading using devm_platform_ioremap_*
and add loading of the 'common' region found on Tegra234.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 46 +---
drivers/gpu/host1x/dev
From: Mikko Perttunen
NVDEC's TRANSCFG register is at a different offset than VIC.
This becomes a problem now when context isolation is enabled and
the reset value of the register is no longer sufficient.
Signed-off-by: Mikko Perttunen
---
v6:
* New patch
---
drivers/gpu/drm/tegra/nvdec.
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