compatibility with kernels before 6.0, as we do not
support anymore the legacy `iface_clk` name.
Signed-off-by: Loic Poulain
---
v3: Drop extra pm_runtime calls from probe
Reword resume error on message
Document compatibility break
v2: Move AHB clock into a proper PM dep instead of manually
If the interrupt occurs before resource initialization is complete, the
interrupt handler/worker may access uninitialized data such as the I2C
tcpc_client device, potentially leading to NULL pointer dereference.
Signed-off-by: Loic Poulain
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 6
Hi Dmitry,
On Sun, Jun 29, 2025 at 4:57 PM Dmitry Baryshkov
wrote:
>
> On Sun, Jun 29, 2025 at 10:50:36AM +0200, Loic Poulain wrote:
> > To configure and enable the DSI PHY PLL clocks, the MDSS AHB clock must
> > be active for MMIO operations. Typically, this AHB clock is enab
On Mon, Jun 30, 2025 at 10:40 AM Maxime Ripard wrote:
>
> On Mon, Jun 30, 2025 at 09:46:40AM +0200, Loic Poulain wrote:
> > Hi Maxime,
> >
> > On Mon, Jun 30, 2025 at 9:07 AM Maxime Ripard wrote:
> > > On Sun, Jun 29, 2025 at 04:38:36AM +0200, Loic Poulain wro
Hi Maxime,
On Mon, Jun 30, 2025 at 9:07 AM Maxime Ripard wrote:
> On Sun, Jun 29, 2025 at 04:38:36AM +0200, Loic Poulain wrote:
> > DRM checks EDID block count against allocated size in drm_edid_valid
> > function. We have to allocate the right EDID size instead of the max
>
is the parent of the PLL
clocks, this resolves the PLL/AHB dependency. Now the AHB clock is enabled
prior the PLL clk_prepare callback, as part of the runtime-resume chain.
We also eliminate dsi_phy_[enable|disable]_resource functions, which are
superseded by runtime PM.
Signed-off-by: Loic Poulain
DRM checks EDID block count against allocated size in drm_edid_valid
function. We have to allocate the right EDID size instead of the max
size to prevent the EDID to be reported as invalid.
Fixes: 7c585f9a71aa ("drm/bridge: anx7625: use struct drm_edid more")
Signed-off-by: Lo
Hi Dmitry,
On Tue, 18 Jan 2022 at 19:02, Dmitry Baryshkov
wrote:
>
> On 18/01/2022 18:47, Loic Poulain wrote:
> > Add compatibility for QCM2290 display subsystem, including
> > required entries in DPU hw catalog.
> >
> > Signed-off-by: Loic Poulain
> > ---
QCM2290 MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for DPU device
tree bindings
Signed-off-by: Loic Poulain
---
.../bindings/display/msm/dpu-qcm2290.yaml | 214 +
1 file changed, 214 insertions
Add compatibility for QCM2290 display subsystem, including
required entries in DPU hw catalog.
Signed-off-by: Loic Poulain
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 175 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1
t; Signed-off-by: Marek Vasut
> >> Cc: Douglas Anderson
> >> Cc: Jagan Teki
> >> Cc: Laurent Pinchart
> >> Cc: Linus Walleij
> >> Cc: Philippe Schenker
> >> Cc: Sam Ravnborg
> >> Cc: Stephen Boyd
> >> Cc: Valentin Raevsky
617 ++
3 files changed, 628 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi83.c
Tested on MSC-SM2S-IMX8MINI module with a 1024x768 (VESA-24) single LVDS
channel panel.
Tested-by: Loic Poulain
Loic
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