set of parameters
> should cover all potential users.
>
> Cc: Kishon Vijay Abraham I
> Cc: Vinod Koul
> Cc: NXP Linux Team
> Signed-off-by: Liu Ying
> ---
> v4->v5:
> * Align kernel-doc style to include/linux/phy/phy.h. (Vinod)
> * Trivial tweaks.
> * Drop R
On 09/01/20 2:37 AM, Jonas Karlman wrote:
> This series make it possible to use more HDMI modes on RK3328,
> and presumably also on RK3228. It also prepares for a future YUV420 and
> 10-bit output series.
>
> Part of this has been reworked from vendor BSP 4.4 kernel commits.
>
> Patch 1-5 fixe
On 08/01/20 12:22 AM, Jyri Sarha wrote:
> On 06/01/2020 14:22, Yuti Amonkar wrote:
>> Allow DisplayPort PHYs to be configured through the generic
>> functions through a custom structure added to the generic union.
>> The configuration structure is used for reconfiguration of
>> DisplayPort PHYs
+ Maxime (Fixed Maxime's email address)
On 23/12/19 5:57 PM, Kishon Vijay Abraham I wrote:
> + Maxime
>
> Hi,
>
> On 23/12/19 12:24 PM, Yuti Amonkar wrote:
>> Allow DisplayPort PHYs to be configured through the generic
>> functions through a custom structure ad
+ Maxime
Hi,
On 23/12/19 12:24 PM, Yuti Amonkar wrote:
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.
The pa
;http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Cadence Torrent SD0801 PHY binding for DisplayPort
+
+description:
+ This binding describes the Cadence SD0801 PHY hardware included with
+ the Cadence MHDP DisplayPort controller.
+
+maintainers:
+ - Kishon Vijay Abraham I
No,
Hi Yuti,
On 04/12/19 1:51 am, Jyri Sarha wrote:
Yuti, you have phy maintainer (Kishon) in cc, but you do not have
linux-ker...@vger.kernel.org list mentioned under "GENERIC PHY
FRAMEWORK" entry in the MAINTAINERS file [1]. Please add that to the
recipient list
in the next round.
Can you resend
Hi,
On 24/05/19 9:31 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On 24/05/19 5:53 PM, Fabio Estevam wrote:
>> Hi Kishon,
>>
>> On Sun, May 12, 2019 at 7:49 AM Guido Günther wrote:
>>>
>>> This adds support for the Mixel DPHY as found on i.MX8 CPUs bu
Hi,
On 24/05/19 5:53 PM, Fabio Estevam wrote:
> Hi Kishon,
>
> On Sun, May 12, 2019 at 7:49 AM Guido Günther wrote:
>>
>> This adds support for the Mixel DPHY as found on i.MX8 CPUs but since
>> this is an IP core it will likely be found on others in the future. So
>> instead of adding this to t
Hi Maxime,
On 01/04/19 3:43 PM, Guido Günther wrote:
> This adds support for the Mixel DPHY as found on i.MX8 CPUs but since
> this is an IP core it will likely be found on others in the future. So
> instead of adding this to the nwl host driver make it a generic PHY
> driver.
>
> The driver supp
Hi,
On 06/02/19 5:55 PM, Maxime Ripard wrote:
> Hi Kishon,
>
> On Wed, Feb 06, 2019 at 05:43:12PM +0530, Kishon Vijay Abraham I wrote:
>> On 05/02/19 2:16 PM, Daniel Vetter wrote:
>>> On Mon, Feb 04, 2019 at 03:33:31PM +0530, Kishon Vijay Abraham I wrote:
>>&g
Hi,
On 05/02/19 2:16 PM, Daniel Vetter wrote:
> On Mon, Feb 04, 2019 at 03:33:31PM +0530, Kishon Vijay Abraham I wrote:
>>
>>
>> On 21/01/19 9:15 PM, Maxime Ripard wrote:
>>> Hi,
>>>
>>> Here is a set of patches to allow the phy framework consum
On 21/01/19 9:15 PM, Maxime Ripard wrote:
> Hi,
>
> Here is a set of patches to allow the phy framework consumers to test and
> apply runtime configurations.
>
> This is needed to support more phy classes that require tuning based on
> parameters depending on the current use case of the device,
Hi,
On 09/01/19 3:03 PM, Maxime Ripard wrote:
> Now that we have everything we need in the phy framework to allow to tune
> the phy parameters, let's convert the Cadence DSI bridge to that API
> instead of creating a ad-hoc driver for its phy.
>
> Signed-off-by: Maxime Ripard
For this too, need
Hi Maxime,
On 09/01/19 3:03 PM, Maxime Ripard wrote:
> The current configuration of the DSI bridge and its associated D-PHY is
> intertwined. In order to ease the future conversion to the phy framework
> for the D-PHY part, let's split the configuration in two.
>
> Signed-off-by: Maxime Ripard
Maxime,
On 06/11/18 8:24 PM, Maxime Ripard wrote:
> Hi,
>
> Here is a set of patches to allow the phy framework consumers to test and
> apply runtime configurations.
>
> This is needed to support more phy classes that require tuning based on
> parameters depending on the current use case of the
Hi Maxime,
On 21/11/18 3:03 PM, Maxime Ripard wrote:
> Hi Sakari,
>
> Thanks for your review.
>
> On Mon, Nov 19, 2018 at 03:43:57PM +0200, Sakari Ailus wrote:
>>> +/*
>>> + * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
>>> + * from the valid ranges specified in Section 6.9,
Hi,
On 21/11/18 7:17 PM, Maxime Ripard wrote:
> Hi Kishon,
>
> On Wed, Nov 21, 2018 at 03:59:43PM +0530, Kishon Vijay Abraham I wrote:
>> On 21/11/18 3:41 PM, Maxime Ripard wrote:
>>> Hi Kishon,
>>>
>>> On Tue, Nov 20, 2018 at 11:02:34AM +0530, Kishon
Hi Maxime,
On 21/11/18 3:41 PM, Maxime Ripard wrote:
> Hi Kishon,
>
> On Tue, Nov 20, 2018 at 11:02:34AM +0530, Kishon Vijay Abraham I wrote:
>>>> +static int cdns_dphy_config_from_opts(struct phy *phy,
>>>> +struct p
Hi,
On 12/11/18 3:21 PM, Kishon Vijay Abraham I wrote:
Hi Maxime,
On 06/11/18 8:24 PM, Maxime Ripard wrote:
Cadence has designed a D-PHY that can be used by the, currently in tree,
DSI bridge (DRM), CSI Transceiver and CSI Receiver (v4l2) drivers.
Only the DSI driver has an ad-hoc driver for
Hi Maxime,
On 06/11/18 8:24 PM, Maxime Ripard wrote:
> The phy framework is only allowing to configure the power state of the PHY
> using the init and power_on hooks, and their power_off and exit
> counterparts.
>
> While it works for most, simple, PHYs supported so far, some more advanced
> PHYs
Hi Maxime,
On 06/11/18 8:24 PM, Maxime Ripard wrote:
> Cadence has designed a D-PHY that can be used by the, currently in tree,
> DSI bridge (DRM), CSI Transceiver and CSI Receiver (v4l2) drivers.
>
> Only the DSI driver has an ad-hoc driver for that phy at the moment, while
> the v4l2 drivers ar
Hi Maxime,
On Wednesday 19 September 2018 05:44 PM, Maxime Ripard wrote:
> Hi,
>
> On Fri, Sep 14, 2018 at 02:18:37PM +0530, Kishon Vijay Abraham I wrote:
>>>>>>> +/**
>>>>>>> + * phy_validate() - Checks the phy parameters
>>>&g
Hi Maxime,
On Monday 24 September 2018 03:24 PM, Maxime Ripard wrote:
> Hi,
>
> On Mon, Sep 24, 2018 at 02:18:35PM +0530, Kishon Vijay Abraham I wrote:
>> On Wednesday 19 September 2018 05:44 PM, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Fri, Sep 14, 2018
Hi Maxime,
On Wednesday 12 September 2018 02:12 PM, Maxime Ripard wrote:
> Hi!
>
> On Wed, Sep 12, 2018 at 01:12:31PM +0530, Kishon Vijay Abraham I wrote:
>> On Thursday 06 September 2018 08:26 PM, Maxime Ripard wrote:
>>> Hi Kishon,
>>>
>>> On Thu, Sep
Hi,
On Thursday 06 September 2018 08:26 PM, Maxime Ripard wrote:
> Hi Kishon,
>
> On Thu, Sep 06, 2018 at 02:57:58PM +0530, Kishon Vijay Abraham I wrote:
>> On Wednesday 05 September 2018 02:46 PM, Maxime Ripard wrote:
>>> The phy framework is only allowing to configur
Hi,
On Wednesday 05 September 2018 02:46 PM, Maxime Ripard wrote:
> The phy framework is only allowing to configure the power state of the PHY
> using the init and power_on hooks, and their power_off and exit
> counterparts.
>
> While it works for most, simple, PHYs supported so far, some more ad
On Friday 16 February 2018 06:35 PM, Heiko Stübner wrote:
> Hi Kishon,
>
> Am Freitag, 16. Februar 2018, 12:04:42 CET schrieb Kishon Vijay Abraham I:
>> On Friday 10 February 2017 01:14 PM, Chris Zhong wrote:
>>> There are 2 Type-c PHYs in RK3399, but only one DP contro
Hi,
On Friday 10 February 2017 01:14 PM, Chris Zhong wrote:
>
> There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence
> only one PHY can connect to DP controller at one time, the other should
> be disconnected. The GRF_SOC_CON26 register has a switch bit to do it,
> set this bit me
Hi Archit,
On Tuesday 23 February 2016 03:06 PM, Archit Taneja wrote:
>
>
> On 02/23/2016 12:57 AM, Rob Herring wrote:
>> On Mon, Feb 22, 2016 at 5:07 AM, Archit Taneja
>> wrote:
>>>
>>>
>>> On 02/22/2016 08:24 AM, Rob Herring wrote:
On Mon, Feb 15, 2016 at 12:23:26PM +0530, Archit T
Hi,
On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
> This phy driver is binded with the Rockchip DisplayPort
> driver, here are the brief properties:
> edp_phy: edp-phy at ff770274 {
> compatible = "rockchip,rk3288-dp-phy";
> rockchip,grf = <&grf>;
>
Hi,
On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.
Add ph
Hi,
On Wednesday 19 August 2015 08:21 PM, Yakir Yang wrote:
> Signed-off-by: Yakir Yang
where's the commit message?
> ---
> Changes in v3:
> - Take Heiko suggest, add rockchip dp phy driver,
> collect the phy clocks and power control.
>
> Changes in v2: None
>
> .../devicetree/bindings/phy/
On Thursday 18 September 2014 08:55 AM, Vivek Gautam wrote:
> Hi Kishon,
>
>
> On Wed, Sep 17, 2014 at 10:24 PM, Kishon Vijay Abraham I
> wrote:
>>
>>
>> On Tuesday 16 September 2014 10:32 AM, Vivek Gautam wrote:
>>> Currently the DP_PHY_ENABLE
#x27;reg' property for the
> controller and allocating a memory resource for that.
>
> To facilitate this, we have added another compatible string
> for Exynso5420 SoC to acquire driver data which contains
> different DP-PHY-CONTROL register offset.
>
> Signed-off-by: Vi
On Thursday 15 May 2014 07:05 PM, Rahul Sharma wrote:
> Hi,
>
> On 15 May 2014 19:01, Bartlomiej Zolnierkiewicz
> wrote:
>>
>> Hi,
>>
>> On Thursday, May 15, 2014 12:47:21 AM Rahul Sharma wrote:
>>> From: Tomasz Stanislawski
>>>
>>> Add exynos-simple-phy driver to support a single register
>>>
Hi,
On Wednesday 09 April 2014 03:31 PM, Sylwester Nawrocki wrote:
> Hi,
>
> On 09/04/14 11:12, Rahul Sharma wrote:
>> Idea looks good. How about keeping compatible which is independent
>> of SoC, something like "samsung,exynos-simple-phy" and provide Reg
>> and Bit through phy provider node. Thi
Hi,
On Friday 25 October 2013 01:21 PM, Tomasz Stanislawski wrote:
> Hi,
> Please refer to the comments below.
>
> On 10/24/2013 05:52 PM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Monday 21 October 2013 07:48 PM, Tomasz Stanislawski wrote:
>>> Ad
Hi,
On Monday 21 October 2013 07:48 PM, Tomasz Stanislawski wrote:
> Add simple-phy driver to support a single register
> PHY interfaces present on Exynos4 SoC.
How are these PHY interfaces modelled in the SoC? Where does the register
actually reside?
>
> Signed-off-by: Tomasz Stanislawski
> --
Hi,
On Monday 21 October 2013 07:48 PM, Tomasz Stanislawski wrote:
> Use default handler of_phy_simple_xlate() when NULL is passed as argument to
> of_phy_provider_register().
>
> Signed-off-by: Tomasz Stanislawski
> ---
> drivers/phy/phy-core.c |2 +-
> 1 file changed, 1 insertion(+), 1 de
Hi,
On Tuesday 30 July 2013 09:12 AM, Rahul Sharma wrote:
>
>
> On Tue, Jun 18, 2013 at 5:07 PM, Kishon Vijay Abraham I <mailto:kishon at ti.com>> wrote:
>
> Hi,
>
> On Tuesday 18 June 2013 03:33 PM, Rahul Sharma wrote:
> > Thanks all,
>
Hi,
On Tuesday 30 July 2013 09:12 AM, Rahul Sharma wrote:
>
>
> On Tue, Jun 18, 2013 at 5:07 PM, Kishon Vijay Abraham I <mailto:kis...@ti.com>> wrote:
>
> Hi,
>
> On Tuesday 18 June 2013 03:33 PM, Rahul Sharma wrote:
> > Thanks all,
>
Hi,
On Tuesday 18 June 2013 03:33 PM, Rahul Sharma wrote:
> Thanks all,
>
> On Fri, Jun 14, 2013 at 11:39 AM, ??? wrote:
>> Hello Kishon,
>>
>> On 2013? 06? 13? 21:54, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Thursday 13 June 2013 0
Hi,
On Tuesday 18 June 2013 03:33 PM, Rahul Sharma wrote:
> Thanks all,
>
> On Fri, Jun 14, 2013 at 11:39 AM, 김승우 wrote:
>> Hello Kishon,
>>
>> On 2013년 06월 13일 21:54, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Thursday 13 June 2013 0
...@lists.ozlabs.org; DRI mailing list; Kukjin Kim; Seung-Woo Kim;
Sean Paul; sunil joshi; Kishon Vijay Abraham I; Stephen Warren;
grant.lik...@linaro.org
Subject: Re: [RFC 0/2] exynos5250/hdmi: replace dummy hdmiphy clock with
pmu reg control
Hi,
On 06/13/2013 06:26 AM, Rahul Sharma wrote:
Mr. Dae,
Thanks for
g-soc at vger.kernel.org; devicetree-
>> discuss at lists.ozlabs.org; DRI mailing list; Kukjin Kim; Seung-Woo Kim;
>> Sean Paul; sunil joshi; Kishon Vijay Abraham I; Stephen Warren;
>> grant.likely at linaro.org
>> Subject: Re: [RFC 0/2] exynos5250/hdmi: replace dummy hdmiphy cl
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