On 4/16/2025 4:25 AM, Maciej Falkowski wrote:
From: Karol Wachowski
Introduce a heartbeat-based Timeout Detection and Recovery (TDR) mechanism.
The enhancement aims to improve the reliability of device hang detection by
monitoring heartbeat updates.
Each progressing inference will update heart
On 2/25/2025 12:55 AM, Tomeu Vizoso wrote:
+/**
+ * rocket_gem_create_object - Implementation of driver->gem_create_object.
+ * @dev: DRM device
+ * @size: Size in bytes of the memory the object will reference
+ *
+ * This lets the GEM helpers allocate object structs for us, and keep
+ * our BO s
On 2/25/2025 12:55 AM, Tomeu Vizoso wrote:
+int rocket_ioctl_fini_bo(struct drm_device *dev, void *data, struct drm_file
*file)
+{
+ struct drm_rocket_fini_bo *args = data;
+ struct drm_gem_object *gem_obj;
+ struct rocket_gem_object *rkt_obj;
+ struct drm_gem_shmem_objec
On 2/17/2025 8:26 AM, Jacek Lawrynowicz wrote:
Hi,
On 2/14/2025 5:41 PM, Jeffrey Hugo wrote:
On 2/4/2025 1:46 AM, Jacek Lawrynowicz wrote:
From: Andrzej Kacprowski
Multiple threads were accessing mmu cmd queue simultaneously
causing sporadic failures in ivpu_mmu_cmdq_sync() function
On 2/17/2025 8:33 AM, Jacek Lawrynowicz wrote:
Hi,
On 2/14/2025 5:49 PM, Jeffrey Hugo wrote:
On 2/4/2025 1:46 AM, Jacek Lawrynowicz wrote:
From: Andrzej Kacprowski
Increment the runtime PM counter when entering
ivpu_context_abort_work_fn() to prevent the device
from suspending while the
On 2/14/2025 10:34 AM, Manivannan Sadhasivam wrote:
On Fri, Feb 14, 2025 at 09:21:09AM -0700, Jeffrey Hugo wrote:
If mhi_fw_load_handler() bails out early because the EE is not capable
of loading firmware, we may reference fw_load_type in cleanup which is
uninitialized at this point. The
On 2/4/2025 1:46 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
Add power_profile firmware boot param and set it to 0 by default
which is default FW power profile.
I don't think that patch does this. It looks like
boot_params->power_profile is already defined. What am I missing?
-Jeff
Reviewed-by: Jeffrey Hugo
can be MMU-mapped only to a single context.
Each import now creates a new instance of ivpu_bo object that shares
the same sg_table but have separate MMU mappings.
Reviewed-by: Jacek Lawrynowicz
Signed-off-by: Tomasz Rusinowicz
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
priority band, facilitating validation and fine-tuning.
Reviewed-by: Jacek Lawrynowicz
Signed-off-by: Karol Wachowski
Signed-off-by: Jacek Lawrynowicz
As a stand alone patch, seems ok to me.
Reviewed-by: Jeffrey Hugo
On 2/4/2025 1:46 AM, Jacek Lawrynowicz wrote:
From: Andrzej Kacprowski
Increment the runtime PM counter when entering
ivpu_context_abort_work_fn() to prevent the device
from suspending while the function is executing.
Why should suspend be prevented during the abort fn?
-Jeff
On 2/4/2025 1:46 AM, Jacek Lawrynowicz wrote:
From: Andrzej Kacprowski
Multiple threads were accessing mmu cmd queue simultaneously
causing sporadic failures in ivpu_mmu_cmdq_sync() function.
Protect critical code with mmu mutex.
Describe a scenario in which this can occur? The two functions
r via
BHIe in PBL")
Signed-off-by: Jeffrey Hugo
---
drivers/bus/mhi/host/boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/bus/mhi/host/boot.c b/drivers/bus/mhi/host/boot.c
index c8e48f621a8c..efa3b6dddf4d 100644
--- a/drivers/bus/mhi/host/boot.c
+++ b/drivers/bu
On 2/13/2025 7:17 AM, Thomas Zimmermann wrote:
Hi
Am 12.02.25 um 16:52 schrieb Jeffrey Hugo:
On 2/12/2025 6:27 AM, Jacek Lawrynowicz wrote:
Hi,
Thanks for your detailed feedback and constructive suggestions. I
appreciate this as it is not easy to learn all process details
otherwise.
I
On 1/24/2025 10:35 AM, Lizhi Hou wrote:
It is required by firmware to wait up to 2 seconds for pending commands
before sending the destroy hardware context command. After 2 seconds
wait, if there are still pending commands, driver needs to cancel them.
So the context destroy steps need to be:
On 2/12/2025 6:27 AM, Jacek Lawrynowicz wrote:
Hi,
Thanks for your detailed feedback and constructive suggestions. I appreciate
this as it is not easy to learn all process details otherwise.
I echo this. At times, accel feels a bit isolated from DRM.
On 2/12/2025 11:20 AM, Thomas Zimmerma
);
| ^~~
Add the missing include.
Fixes: b87f920b9344 ("accel/amdxdna: Support hardware mailbox")
Signed-off-by: Su Hui
Reviewed-by: Lizhi Hou
Reviewed-by: Jeffrey Hugo
Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
er
to wait for the hardware to reach a specific state. This allows to test
failures during NPU boot and shutdown, IPC message handling and more.
Fault injection can be enabled using debugfs or a module parameter.
Reviewed-by: Maciej Falkowski
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
Lawrynowicz
Reviewed-by: Jeffrey Hugo
On 1/29/2025 5:56 AM, Jacek Lawrynowicz wrote:
From: Karol Wachowski
Hardware scheduling (HWS) is supposed to be supported on all existing
platform with recent FW including pre-silicon ones. Turn on HWS by
default.
Is there released firmware which does not have this enabled/supported?
Should
and new events are not missed.
Reviewed-by: Jacek Lawrynowicz
Signed-off-by: Karol Wachowski
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
On 1/29/2025 5:56 AM, Jacek Lawrynowicz wrote:
Call pm_runtime_mark_last_busy() in top half of IRQ handler to prevent
device from being runtime suspended before bottom half is executed on
a workqueue.
Reviewed-by: Karol Wachowski
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
. Also, move common reset/recovery
code to separate functions for better code readability.
Fixes: 27d19268cf39 ("accel/ivpu: Improve recovery and reset support")
Cc: # v6.8+
Reviewed-by: Maciej Falkowski
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
the NPU fails to boot during
runtime resume.
Fixes: 7d4b4c74432d ("accel/ivpu: Remove suspend_reschedule_counter")
Cc: # v6.11+
Reviewed-by: Maciej Falkowski
Signed-off-by: Jacek Lawrynowicz
---
Reviewed-by: Jeffrey Hugo
Reviewed-by: Jeffrey Hugo
: Jeffrey Hugo
On 1/17/2025 10:09 AM, Jeffrey Hugo wrote:
Initial support to the driver to boot up AIC200. AIC200 uses BHIe
without BHI, which is something that the MHI bus has not supported until
now. While the MHI changes are listed first to facilitate cross-tree
merging, they are not needed until the last
On 1/21/2025 10:06 AM, Manivannan Sadhasivam wrote:
On Tue, Jan 21, 2025 at 08:29:32AM -0700, Jeffrey Hugo wrote:
On 1/20/2025 10:16 PM, Manivannan Sadhasivam wrote:
On Fri, Jan 17, 2025 at 10:09:43AM -0700, Jeffrey Hugo wrote:
Add basic support for the new AIC200 product. The PCIe Device ID
On 1/20/2025 10:16 PM, Manivannan Sadhasivam wrote:
On Fri, Jan 17, 2025 at 10:09:43AM -0700, Jeffrey Hugo wrote:
Add basic support for the new AIC200 product. The PCIe Device ID is
0xa110. With this, we can turn on the lights for AIC200 by leveraging
much of the existing driver.
Co-developed
, and does not set
fbc_download. The intention is to transfer firmware using BHIe in PBL
without further BHIe transfers in SBL.
Signed-off-by: Matthew Leung
Reviewed-by: Youssef Samir
Reviewed-by: Jeffrey Hugo
Signed-off-by: Jeffrey Hugo
Reviewed-by: Jacek Lawrynowicz
---
drivers/bus/mhi/host
.
Signed-off-by: Youssef Samir
Reviewed-by: Jeffrey Hugo
Signed-off-by: Jeffrey Hugo
Reviewed-by: Lizhi Hou
---
drivers/accel/qaic/qaic_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/accel/qaic/qaic_drv.c b/drivers/accel/qaic/qaic_drv.c
index 6e9bed17b3f1
Add basic support for the new AIC200 product. The PCIe Device ID is
0xa110. With this, we can turn on the lights for AIC200 by leveraging
much of the existing driver.
Co-developed-by: Youssef Samir
Signed-off-by: Youssef Samir
Signed-off-by: Jeffrey Hugo
Reviewed-by: Lizhi Hou
---
drivers
-off-by: Youssef Samir
Reviewed-by: Jeffrey Hugo
Signed-off-by: Jeffrey Hugo
Reviewed-by: Lizhi Hou
---
drivers/accel/qaic/qaic_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/accel/qaic/qaic_drv.c b/drivers/accel/qaic/qaic_drv.c
index ce0428f6cb82..00fa07aebacd
let the driver configure the
qaic_device struct based on the configurations passed to the driver.
Co-developed-by: Youssef Samir
Signed-off-by: Youssef Samir
Signed-off-by: Jeffrey Hugo
Reviewed-by: Lizhi Hou
---
drivers/accel/qaic/qaic.h | 13 +++--
drivers/accel/qaic/qaic_drv.c
.
Allocate only the needed number of MSI vectors per device.
Signed-off-by: Youssef Samir
Reviewed-by: Troy Hanson
Reviewed-by: Jeffrey Hugo
Signed-off-by: Jeffrey Hugo
Reviewed-by: Lizhi Hou
---
drivers/accel/qaic/qaic_drv.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a
: Youssef Samir
Reviewed-by: Jeffrey Hugo
Signed-off-by: Jeffrey Hugo
---
drivers/bus/mhi/host/boot.c | 144 +---
1 file changed, 99 insertions(+), 45 deletions(-)
diff --git a/drivers/bus/mhi/host/boot.c b/drivers/bus/mhi/host/boot.c
index e8c92972f9df..9fe13d3f09f0
mhi_load_image_bhie()
-Adjust the order of mhi_cntrl init in qaic_mhi_register_controller()
Jeffrey Hugo (2):
accel/qaic: Add config structs for supported cards
accel/qaic: Add AIC200 support
Matthew Leung (2):
bus: mhi: host: Refactor BHI/BHIe based firmware loading
bus: mhi: host: Add a
On 1/7/2025 10:42 PM, Manivannan Sadhasivam wrote:
On Fri, Dec 13, 2024 at 02:33:35PM -0700, Jeffrey Hugo wrote:
From: Matthew Leung
Currently, mhi host only performs firmware transfer via BHI in PBL and
s/mhi/MHI here and below.
Done
BHIe from SBL. To support BHIe transfer directly
On 1/7/2025 10:24 PM, Manivannan Sadhasivam wrote:
On Fri, Dec 13, 2024 at 02:33:34PM -0700, Jeffrey Hugo wrote:
From: Matthew Leung
Refactor the firmware loading code to have distinct helper functions for
BHI and BHIe operations. This lays the foundation for separating the
firmware loading
On 12/13/2024 11:51 AM, Jeffrey Hugo wrote:
From: Youssef Samir
aic100_image_table is currently defined as a "const char *" array,
this can potentially lead to the accidental modification of the
pointers inside. Also, checkpatch.pl gives a warning about it.
Change the type to a &
: Stanislaw Gruszka
Reviewed-by: Oded Gabbay
Reviewed-by: Jeffrey Hugo
On 12/20/2024 10:33 AM, Lizhi Hou wrote:
On 12/20/24 09:26, Jeffrey Hugo wrote:
On 12/13/2024 5:49 PM, Lizhi Hou wrote:
On 12/13/24 13:33, Jeffrey Hugo wrote:
+static const struct qaic_device_config aic200_config = {
+ .family = FAMILY_AIC200,
+ .bar_mask = BIT(0) | BIT(1) | BIT(2
On 12/13/2024 5:49 PM, Lizhi Hou wrote:
On 12/13/24 13:33, Jeffrey Hugo wrote:
@@ -573,6 +898,13 @@ struct mhi_controller
*qaic_mhi_register_controller(struct pci_dev *pci_dev, voi
mhi_cntrl->nr_irqs = 1;
mhi_cntrl->irq = devm_kmalloc(&pci_dev->dev,
sizeof(*m
On 12/13/2024 5:35 PM, Lizhi Hou wrote:
On 12/13/24 13:33, Jeffrey Hugo wrote:
-static struct qaic_device *create_qdev(struct pci_dev *pdev, const
struct pci_device_id *id)
+static struct qaic_device *create_qdev(struct pci_dev *pdev,
+ const struct qaic_device_config
-off-by: Youssef Samir
Reviewed-by: Jeffrey Hugo
Signed-off-by: Jeffrey Hugo
---
drivers/accel/qaic/qaic_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/accel/qaic/qaic_drv.c b/drivers/accel/qaic/qaic_drv.c
index ce0428f6cb82..00fa07aebacd 100644
--- a/drivers
: Youssef Samir
Reviewed-by: Jeffrey Hugo
Signed-off-by: Jeffrey Hugo
---
drivers/bus/mhi/host/boot.c | 155 +---
1 file changed, 110 insertions(+), 45 deletions(-)
diff --git a/drivers/bus/mhi/host/boot.c b/drivers/bus/mhi/host/boot.c
index e8c92972f9df..e3f3c07166ad
Add basic support for the new AIC200 product. The PCIe Device ID is
0xa110. With this, we can turn on the lights for AIC200 by leveraging
much of the existing driver.
Co-developed-by: Youssef Samir
Signed-off-by: Youssef Samir
Signed-off-by: Jeffrey Hugo
---
drivers/accel/qaic
let the driver configure the
qaic_device struct based on the configurations passed to the driver.
Co-developed-by: Youssef Samir
Signed-off-by: Youssef Samir
Signed-off-by: Jeffrey Hugo
---
drivers/accel/qaic/qaic.h | 13 +++--
drivers/accel/qaic/qaic_drv.c | 76
.
Signed-off-by: Youssef Samir
Reviewed-by: Jeffrey Hugo
Signed-off-by: Jeffrey Hugo
---
drivers/accel/qaic/qaic_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/accel/qaic/qaic_drv.c b/drivers/accel/qaic/qaic_drv.c
index 6e9bed17b3f1..ce0428f6cb82 100644
--- a
.
Allocate only the needed number of MSI vectors per device.
Signed-off-by: Youssef Samir
Reviewed-by: Troy Hanson
Reviewed-by: Jeffrey Hugo
Signed-off-by: Jeffrey Hugo
---
drivers/accel/qaic/qaic_drv.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/accel/qaic
different product from AIC100 with MSI-X, different
BARs, and different MHI configuration so we finally need some
infrastructure in the driver to be able to handle product differences.
This is expected to evolve more over time.
Jeffrey Hugo (2):
accel/qaic: Add config structs for supported cards
, and does not set
fbc_download. The intention is to transfer firmware using BHIe in PBL
without further BHIe transfers in SBL.
Signed-off-by: Matthew Leung
Reviewed-by: Youssef Samir
Reviewed-by: Jeffrey Hugo
Signed-off-by: Jeffrey Hugo
---
drivers/bus/mhi/host/boot.c | 80
e pointers
immutable, preventing accidental modification of the images' paths.
Signed-off-by: Youssef Samir
Reviewed-by: Carl Vanderlip
Reviewed-by: Jeffrey Hugo
Signed-off-by: Jeffrey Hugo
---
drivers/accel/qaic/sahara.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff -
On 12/13/2024 10:57 AM, Lizhi Hou wrote:
On 12/13/24 09:49, Jeffrey Hugo wrote:
On 12/13/2024 10:41 AM, Lizhi Hou wrote:
On 12/13/24 09:07, Jeffrey Hugo wrote:
On 12/13/2024 2:02 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
The old SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS macros
On 12/13/2024 10:41 AM, Lizhi Hou wrote:
On 12/13/24 09:07, Jeffrey Hugo wrote:
On 12/13/2024 2:02 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
The old SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS macros cause a
build
warning when CONFIG_PM is disabled:
drivers/accel/amdxdna
On 12/13/2024 10:02 AM, Lizhi Hou wrote:
On 12/13/24 08:58, Jeffrey Hugo wrote:
On 12/6/2024 3:00 PM, Lizhi Hou wrote:
The latest released firmware supports reading firmware interface version
from registers directly. The driver's probe routine reads the major and
minor version numbers. I
d-by: Mike Lothian
Closes:
https://lore.kernel.org/dri-devel/CAHbf0-E+Z2O7rW-x+-EKNQ-nLbf=_ohanzxxe7wd2cj9kfj...@mail.gmail.com/
Signed-off-by: Mike Lothian
Reviewed-by: Mario Limonciello
Reviewed-by: Jeffrey Hugo
Signed-off-by: Lizhi Hou
Applied to drm-misc-next
-Jeff
urce solver")
Signed-off-by: Arnd Bergmann
amdxdna: includ linux/interrupt.h
Signed-off-by: Arnd Bergmann
The interrupt part of this is now fixed, see "accel/amdxdna: Add include
interrupt.h to amdxdna_mailbox.c".
The slab portion looks sane. I'll trim the patch when applying unless
you'd prefer something else.
Reviewed-by: Jeffrey Hugo
On 12/13/2024 2:02 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
The old SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS macros cause a build
warning when CONFIG_PM is disabled:
drivers/accel/amdxdna/amdxdna_pci_drv.c:343:12: error: 'amdxdna_pmops_resume'
defined but not used [-Werror=unused-fu
d-by: Mike Lothian
Closes:
https://lore.kernel.org/dri-devel/CAHbf0-E+Z2O7rW-x+-EKNQ-nLbf=_ohanzxxe7wd2cj9kfj...@mail.gmail.com/
Signed-off-by: Mike Lothian
Reviewed-by: Mario Limonciello
Reviewed-by: Jeffrey Hugo
Signed-off-by: Lizhi Hou
Pushed to drm-misc-next
-Jeff
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
Add recent improvements and bug fixes for amdxdna driver (depends on [1])
1. Support recent hardware and firmware.
2. Replace idr APIs with xarray.
3. Fix the bugs been found.
[1]: https://lore.kernel.org/all/20241118172942.2014541-1-lizhi@amd.com/
Cha
On 12/6/2024 3:00 PM, Lizhi Hou wrote:
The latest released firmware supports reading firmware interface version
from registers directly. The driver's probe routine reads the major and
minor version numbers. If the firmware interface does not compatible with
the driver, the driver's probe routine
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
+/**
+ * struct amdxdna_drm_get_power_mode - Get the configured power mode
+ * @power_mode: The mode type from enum amdxdna_power_mode_type
+ * @pad: MBZ.
I don't see a check for zero in the implementation
+ */
+struct amdxdna_drm_get_power_mode {
+
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
Enhance GET_INFO ioctl to support retrieving firmware version.
Signed-off-by: Lizhi Hou
Reviewed-by: Jeffrey Hugo
Warning below through.
enum amdxdna_drm_get_param {
DRM_AMDXDNA_QUERY_AIE_STATUS,
DRM_AMDXDNA_QUERY_AIE_METADATA
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
Switch mailbox message id and hardware context id management over from
the idr api to the xarray api.
Signed-off-by: Lizhi Hou
Implementation looks sane, however you appear to be missing several
instances of #include
-Jeff
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
Add NPU6 registers and other private configurations.
Co-developed-by: Xiaoming Ren
Signed-off-by: Xiaoming Ren
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/Makefile| 3 +-
drivers/accel/amdxdna/npu6_regs.c | 121 +++
dead lock.
Fixes: aac243092b70 ("accel/amdxdna: Add command execution")
Signed-off-by: Lizhi Hou
Reviewed-by: Jeffrey Hugo
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
Add device status to track if aie2_hw_start() or aie2_hw_stop() is
re-entered. In aie2_hw_stop(), call drmm_kfree to free mbox.
Signed-off-by: Lizhi Hou
Reviewed-by: Jeffrey Hugo
is SOB.
With either of those:
Reviewed-by: Jeffrey Hugo
On 11/29/2024 1:28 PM, Jeffrey Hugo wrote:
The documentation header for struct qaic_manage_trans_passthrough has a
typo - "t" is missing in "transaction".
Signed-off-by: Jeffrey Hugo
---
include/uapi/drm/qaic_accel.h | 2 +-
1 file changed, 1 insertion(+), 1 delet
On 12/10/2024 6:09 AM, Jacek Lawrynowicz wrote:
Move pm_runtime_set_active() to ivpu_pm_inti() so when
ivpu_pm_init()
With that
Reviewed-by: Jeffrey Hugo
eviewed-by: Karol Wachowski
Reviewed-by: Jeffrey Hugo
pu_addr,
bo->base.base.size,
bo->flags, kref_read(&bo->base.base.refcount));
if (bo->base.pages)
Reviewed-by: Jeffrey Hugo
On 12/6/2024 11:47 AM, Lizhi Hou wrote:
On 12/6/24 09:01, Mike Lothian wrote:
On Fri, 6 Dec 2024 at 16:41, Mike Lothian wrote:
On Fri, 6 Dec 2024 at 16:26, Jeffrey Hugo
wrote:
On 12/5/2024 8:44 AM, Mike Lothian wrote:
Hi
I needed to add the following to get things compiling for me
diff
On 12/5/2024 8:44 AM, Mike Lothian wrote:
Hi
I needed to add the following to get things compiling for me
diff --git a/drivers/accel/amdxdna/amdxdna_mailbox.c
b/drivers/accel/amdxdna/amdxdna_mailbox.c
index fe684f463b945..79b9801935e71 100644
--- a/drivers/accel/amdxdna/amdxdna_mailbox.c
+++ b
The documentation header for struct qaic_manage_trans_passthrough has a
typo - "t" is missing in "transaction".
Signed-off-by: Jeffrey Hugo
---
include/uapi/drm/qaic_accel.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/uapi/drm/qaic_accel.
On 11/24/2024 6:28 AM, Sasha Levin wrote:
From: Jeffrey Hugo
[ Upstream commit b8128f7815ff135f0333c1b46dcdf1543c41b860 ]
Add basic support for the new AIC080 product. The PCIe Device ID is
0xa080. AIC080 is a lower cost, lower performance SKU variant of AIC100.
From the qaic perspective, it
On 11/18/2024 10:29 AM, Lizhi Hou wrote:
This patchset introduces a new Linux Kernel Driver, amdxdna for AMD NPUs.
The driver is based on Linux accel subsystem.
Merged to drm-misc-next
-Jeff
On 11/17/2024 1:26 PM, Jeffrey Hugo wrote:
The documentation for vfree() says that passing in NULL is ok. Therefore
we can drop the null check as redundant.
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202410301732.abf5md4e-...@intel.com/
Signed-off-by: Jeffrey
On 11/18/2024 10:29 AM, Lizhi Hou wrote:
This patchset introduces a new Linux Kernel Driver, amdxdna for AMD NPUs.
The driver is based on Linux accel subsystem.
Not seeing any additional issues. Build for bisect looks good. My plan
is to let this sit on list until Friday to allow for one fin
file.build:478: drivers/accel] Error 2
make[2]: *** [scripts/Makefile.build:478: drivers] Error 2
make[2]: *** Waiting for unfinished jobs
AR kernel/module/built-in.a
AR kernel/built-in.a
With the above two things fixed:
Reviewed-by: Jeffrey Hugo
The documentation for vfree() says that passing in NULL is ok. Therefore
we can drop the null check as redundant.
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202410301732.abf5md4e-...@intel.com/
Signed-off-by: Jeffrey Hugo
---
drivers/accel/qaic/sahara.c | 3
debugfs file that tracks firewall interrupts.
Fixes: 8a27ad81f7d3 ("accel/ivpu: Split IP and buttress code")
Cc: # v6.11+
Signed-off-by: Andrzej Kacprowski
Reviewed-by: Jacek Lawrynowicz
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
ruct
drm_driver, its initialization from drivers, along with the common
DRIVER_DATE macros.
v2: Also update drivers/accel (kernel test robot)
Reviewed-by: Javier Martinez Canillas
Acked-by: Alex Deucher
Acked-by: Simon Ser
Signed-off-by: Jani Nikula
For QAIC -
Acked-by: Jeffrey Hugo
On 10/25/2024 3:28 PM, Lizhi Hou wrote:
On 10/25/24 10:55, Jeffrey Hugo wrote:
On 10/21/2024 10:19 AM, Lizhi Hou wrote:
This patchset introduces a new Linux Kernel Driver, amdxdna for AMD
NPUs.
The driver is based on Linux accel subsystem.
NPU (Neural Processing Unit) is an AI inference
On 10/21/2024 10:19 AM, Lizhi Hou wrote:
This patchset introduces a new Linux Kernel Driver, amdxdna for AMD NPUs.
The driver is based on Linux accel subsystem.
NPU (Neural Processing Unit) is an AI inference accelerator integrated
into AMD client CPUs. NPU enables efficient execution of Machine
On 10/21/2024 10:19 AM, Lizhi Hou wrote:
diff --git a/include/uapi/drm/amdxdna_accel.h b/include/uapi/drm/amdxdna_accel.h
index 3792750834b2..08f3ec7146ab 100644
--- a/include/uapi/drm/amdxdna_accel.h
+++ b/include/uapi/drm/amdxdna_accel.h
@@ -13,6 +13,7 @@
extern "C" {
#endif
+#define AMD
message. The thread
stops the clients which are using the column where error occurred. Then
the driver resets that column.
Co-developed-by: Min Ma
Signed-off-by: Min Ma
Signed-off-by: Lizhi Hou
Reviewed-by: Jeffrey Hugo
On 10/21/2024 2:03 PM, Jeffrey Hugo wrote:
The Sahara protocol has a crashdump functionality. In the hello
exchange, the device can advertise it has a memory dump available for
the host to collect. Instead of the device making requests of the host,
the host requests data from the device which
the original files from.
Reviewed-by: Carl Vanderlip
Signed-off-by: Jeffrey Hugo
---
v2:
-Clarify the dump structure to userspace
-Use array notation for copying an array to the dump
-Use min() over trinary operator
-Remove extra return statement
-Remove extra cast
-Use all cpu_to_le operations
On 10/15/2024 1:04 PM, Bjorn Andersson wrote:
On Tue, Oct 15, 2024 at 12:34:29PM -0600, Jeffrey Hugo wrote:
On 10/14/2024 3:52 PM, Bjorn Andersson wrote:
On Wed, Sep 18, 2024 at 09:52:54AM -0600, Jeffrey Hugo wrote:
+ dev_table_entry = (struct sahara_debug_table_entry64 *)(context->
: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
ws to allocate more command queues with corresponding
preemption buffers without running out of address range.
Signed-off-by: Karol Wachowski
Reviewed-by: Jacek Lawrynowicz
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
disables MIP - job level
preemption will still occur.
Signed-off-by: Karol Wachowski
Reviewed-by: Jacek Lawrynowicz
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
On 10/17/2024 8:58 AM, Jacek Lawrynowicz wrote:
From: Maciej Falkowski
Add CONFIG_DRM_ACCEL_IVPU_DEBUG option that:
- Adds -DDEBUG that enables printk regardless of the kernel config
- Enables unsafe module params (that are now disabled by default)
Signed-off-by: Maciej Falkowski
Reviewed
a context.
Signed-off-by: Karol Wachowski
Reviewed-by: Jacek Lawrynowicz
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
are not reused all over. The same
can be achieved just by using appropriate Linux API.
Signed-off-by: Karol Wachowski
Reviewed-by: Jacek Lawrynowicz
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
owicz
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Jeffrey Hugo
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