Re: [PATCH v2 4/5] drm/msm/mdss: Handle the reg bus ICC path

Hi Konrad, On 18.04.23 15:10, Konrad Dybcio wrote: Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects..

Re: [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells

Hi Robert, On 5.12.22 18:37, Robert Foss wrote: Use two interconnect cells in order to optionally support a path tag. Signed-off-by: Robert Foss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++-- 1 file changed, 14 insertions(+), 14 delet

Re: [PATCH] dt-bindings: Improve phandle-array schemas

e examples need updating so that the bracketing of property values matches the schema. [..] .../bindings/interconnect/qcom,rpmh.yaml | 2 + Acked-by: Georgi Djakov

Re: [PATCH 0/3] iommu/drm/msm: Allow non-coherent masters to use system cache

On Mon, Jan 11, 2021 at 07:45:02PM +0530, Sai Prakash Ranjan wrote: > commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag") > removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went > the memory type setting required for the non-coherent masters to use > system cache.

Re: [PATCH v3 2/3] dt-bindings: Clean-up OPP binding node names in examples

On 20.07.21 17:41, Rob Herring wrote: In preparation to convert OPP bindings to DT schema, clean-up a few OPP binding node names in the binding examples. Cc: Georgi Djakov Cc: Shawn Guo Cc: Sascha Hauer Cc: Leonard Crestez Cc: dri-devel@lists.freedesktop.org Cc: linux...@vger.kernel.org

Re: [PATCH v2 1/7] iommu/io-pgtable: Introduce dynamic io-pgtable fmt registration

Hi Isaac, On 22.12.20 2:44, Isaac J. Manjarres wrote: The io-pgtable code constructs an array of init functions for each page table format at compile time. This is not ideal, as this increases the footprint of the io-pgtable code, as well as prevents io-pgtable formats from being built as kernel

Re: [PATCH v10 01/19] dt-bindings: memory: tegra20: emc: Document opp-supported-hw property

On 23.11.20 2:27, Dmitry Osipenko wrote: Document opp-supported-hw property, which is not strictly necessary to have on Tegra20, but it's very convenient to have because all other SoC core devices will use hardware versioning, and thus, it's good to maintain the consistency. Hi Dmitry, I belie

Re: [PATCH v10 06/19] memory: tegra124: Support interconnect framework

Osipenko Acked-by: Georgi Djakov Thanks, Georgi --- drivers/memory/tegra/Kconfig| 1 + drivers/memory/tegra/tegra124-emc.c | 320 +++- drivers/memory/tegra/tegra124.c | 82 ++- 3 files changed, 391 insertions(+), 12 deletions

Re: [PATCH v10 03/19] memory: tegra30: Support interconnect framework

arbitration latency, which needs to be done for ISO memory clients, like a Display client for example. Tested-by: Peter Geis Signed-off-by: Dmitry Osipenko Acked-by: Georgi Djakov Thank you for the continuous work on this patchset! BR, Georgi --- drivers/memory/tegra/Kconfig | 1

Re: [PATCH v9 01/17] memory: tegra30: Support interconnect framework

On 18.11.20 0:02, Dmitry Osipenko wrote: 17.11.2020 23:24, Georgi Djakov пишет: Hi Dmitry, Thank you working on this! On 15.11.20 23:29, Dmitry Osipenko wrote: Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning

Re: [PATCH v9 01/17] memory: tegra30: Support interconnect framework

Hi Dmitry, Thank you working on this! On 15.11.20 23:29, Dmitry Osipenko wrote: Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. MC driver now supp

Re: [PATCH v7 2/6] interconnect: Add generic interconnect driver for Exynos SoCs

Hi Sylwester, Thank you for refreshing the patchset! On 10/30/20 14:51, Sylwester Nawrocki wrote: > This patch adds a generic interconnect driver for Exynos SoCs in order > to provide interconnect functionality for each "samsung,exynos-bus" > compatible device. > > The SoC topology is a graph (o

Re: [PATCH v7 0/6] Exynos: Simple QoS for exynos-bus using interconnect

Hi Chanwoo and Sylwester, On 11/3/20 09:54, Chanwoo Choi wrote: > Hi Sylwester, > > When I tested this patchset on Odroid-U3, > After setting 0 bps by interconnect[1][2], > the frequency of devfreq devs sustain the high frequency > according to the pm qos request. > > So, I try to find the cause

[PATCH] drm/msm: Remove depends on interconnect

The dependency on interconnect in the Kconfig was introduced to avoid the case of interconnect=m and driver=y, but the interconnect framework has been converted from tristate to bool now. Remove the dependency as the framework can't be a module anymore. Signed-off-by: Georgi Djakov --- dr

Re: [PATCH RFC v6 1/6] dt-bindings: exynos-bus: Add documentation for interconnect properties

Hi Sylwester, On 9/9/20 17:47, Sylwester Nawrocki wrote: > Hi Georgi, > > On 09.09.2020 11:07, Georgi Djakov wrote: >> On 8/28/20 17:49, Sylwester Nawrocki wrote: >>> On 30.07.2020 14:28, Sylwester Nawrocki wrote: >>>> On 09.07.2020 23:04, Rob Herring wrote:

Re: [PATCH v5 27/36] memory: tegra-mc: Register as interconnect provider

On 8/14/20 03:06, Dmitry Osipenko wrote: > Now memory controller is a memory interconnection provider. This allows us > to use interconnect API in order to change memory configuration. > > Signed-off-by: Dmitry Osipenko Thanks Dmitry! Looks good to me. Acked-by: G

Re: [PATCH v5 33/36] memory: tegra30-emc: Register as interconnect provider

On 8/14/20 03:06, Dmitry Osipenko wrote: > Now external memory controller is a memory interconnection provider. > This allows us to use interconnect API to change memory configuration. > > Signed-off-by: Dmitry Osipenko Acked-by: G

Re: [PATCH v5 30/36] memory: tegra20-emc: Register as interconnect provider

On 8/14/20 03:06, Dmitry Osipenko wrote: > Now memory controller is a memory interconnection provider. This allows us > to use interconnect API in order to change memory configuration. > > Signed-off-by: Dmitry Osipenko Acked-by: G

Re: [PATCH RFC v6 1/6] dt-bindings: exynos-bus: Add documentation for interconnect properties

Hi Sylwester, On 8/28/20 17:49, Sylwester Nawrocki wrote: > On 30.07.2020 14:28, Sylwester Nawrocki wrote: >> On 09.07.2020 23:04, Rob Herring wrote: >>> On Thu, Jul 02, 2020 at 06:37:19PM +0200, Sylwester Nawrocki wrote: Add documentation for new optional properties in the exynos bus nodes:

Re: [RFC PATCH] interconnect: qcom: add functions to query addr/cmds for a path

On 7/1/20 07:25, Jonathan Marek wrote: > The a6xx GMU can vote for ddr and cnoc bandwidth, but it needs to be able > to query the interconnect driver for bcm addresses and commands. It's not very clear to me how the GMU firmware would be dealing with this? Does anyone have an idea whether the GMU

Re: [RFC PATCH v5 2/6] interconnect: Add generic interconnect driver for Exynos SoCs

Hi Sylwester, On 7/2/20 15:01, Sylwester Nawrocki wrote: > Hi Georgi, > > On 01.07.2020 14:50, Georgi Djakov wrote: >> Thanks for the patch and apologies for the delayed reply. > > Thanks, no problem. It's actually just in time as I put that patchset > aside for

Re: [PATCH v4 28/37] memory: tegra: Register as interconnect provider

Hi Dmitry, On 7/2/20 02:36, Dmitry Osipenko wrote: > 01.07.2020 20:12, Georgi Djakov пишет: >> Hi Dmitry, >> >> Thank you for updating the patches! > > Hello, Georgi! > > Thank you for the review! > >> On 6/9/20 16:13, Dmitry Osipenko wr

Re: [PATCH v4 27/37] interconnect: Relax requirement in of_icc_get_from_provider()

Hi Dmitry, On 6/9/20 16:13, Dmitry Osipenko wrote: > From: Artur Świgoń > > This patch relaxes the condition in of_icc_get_from_provider() so that it > is no longer required to set #interconnect-cells = <1> in the DT. In case > of the devfreq driver for exynos-bus, #interconnect-cells is always

Re: [RFC PATCH v5 2/6] interconnect: Add generic interconnect driver for Exynos SoCs

Hi Sylwester, Thanks for the patch and apologies for the delayed reply. On 5/29/20 19:31, Sylwester Nawrocki wrote: > This patch adds a generic interconnect driver for Exynos SoCs in order > to provide interconnect functionality for each "samsung,exynos-bus" > compatible device. > > The SoC topo

Re: [PATCH v4 28/37] memory: tegra: Register as interconnect provider

Hi Dmitry, Thank you for updating the patches! On 6/9/20 16:13, Dmitry Osipenko wrote: > Now memory controller is a memory interconnection provider. This allows us > to use interconnect API in order to change memory configuration. > > Signed-off-by: Dmitry Osipenko > --- > drivers/memory/tegra

Re: [v2 1/3] drm/msm/dpu: add support for clk and bw scaling for display

Hi Krishna, Thanks for the patch! On 4/2/20 09:52, Krishna Manikandan wrote: > This change adds support to scale src clk and bandwidth as > per composition requirements. > > Interconnect registration for bw has been moved to mdp > device node from mdss to facilitate the scaling. No Signed-off-b

Re: [PATCH v2 17/22] memory: tegra30-emc: Register as interconnect provider

Hi Dmitry, On 3/30/20 04:08, Dmitry Osipenko wrote: > Now external memory controller is a memory interconnection provider. > This allows us to use interconnect API to change memory configuration. > > Signed-off-by: Dmitry Osipenko > --- > drivers/memory/tegra/tegra30-emc.c | 115 +++

Re: [PATCH v2 11/22] memory: tegra: Register as interconnect provider

Hi Dmitry, Thank you for the patchset! On 3/30/20 04:08, Dmitry Osipenko wrote: > Now memory controller is a memory interconnection provider. This allows us > to use interconnect API in order to change memory configuration. > > Signed-off-by: Dmitry Osipenko > --- > drivers/memory/tegra/mc.c |

Re: [RFC PATCH v3 5/7] devfreq: exynos-bus: Add interconnect functionality to exynos-bus

Hi Artur, On 1/24/20 13:22, Artur Świgoń wrote: > Hi Georgi, > > On Wed, 2020-01-22 at 19:02 +0200, Georgi Djakov wrote: >> Hi Artur, >> >> On 12/20/19 13:56, Artur Świgoń wrote: >>> This patch adds interconnect functionality to the exynos-bus devfreq >&

Re: [RFC PATCH v3 4/7] arm: dts: exynos: Add interconnect bindings for Exynos4412

Hi Artur, Thank you for your continuous work on this. On 12/20/19 13:56, Artur Świgoń wrote: > This patch adds the following properties to the Exynos4412 DT: > - exynos,interconnect-parent-node: to declare connections between > nodes in order to guarantee PM QoS requirements between nodes;

Re: [RFC PATCH v3 5/7] devfreq: exynos-bus: Add interconnect functionality to exynos-bus

Hi Artur, On 12/20/19 13:56, Artur Świgoń wrote: > This patch adds interconnect functionality to the exynos-bus devfreq > driver. > > The SoC topology is a graph (or, more specifically, a tree) and its > edges are specified using the 'exynos,interconnect-parent-node' in the > DT. Due to unspecifi

Re: [RFC PATCH 09/11] devfreq: exynos-bus: Add interconnect functionality to exynos-bus

Hi Artur, On 8/1/19 10:59, Artur Świgoń wrote: > Hi Georgi, > > On Fri, 2019-07-26 at 11:05 +0300, Georgi Djakov wrote: >> Hi Artur, >> >> On 7/23/19 15:20, Artur Świgoń wrote: >>> This patch adds interconnect functionality to the exynos-bus devfreq >&

Re: [RFC PATCH 09/11] devfreq: exynos-bus: Add interconnect functionality to exynos-bus

Hi Artur, On 7/23/19 15:20, Artur Świgoń wrote: > This patch adds interconnect functionality to the exynos-bus devfreq > driver. > > The SoC topology is a graph (or, more specifically, a tree) and most of its > edges are taken from the devfreq parent-child hierarchy (cf. > Documentation/devicetre

Re: [PATCH 5/5] drm/msm/mdp5: Use the interconnect API

On 5/8/19 23:42, Rob Clark wrote: > From: Georgi Djakov > Let's put some text in the commit message: The interconnect API provides an interface for consumer drivers to express their bandwidth needs in the SoC. This data is aggregated and the on-chip interconnect hardware is config

Re: [PATCH 2/5] drm/msm/dpu: Integrate interconnect API in MDSS

hange, removal >>of extra paranthesis and variables (Matthias Kaehlcke) >> >> Changes in v4: >> - Add comments, spacings, tabs, proper port name >>and icc macro (Georgi Djakov) >> >> Changes in v5: >> - Commit text and paren

Re: [PATCH v4 1/7] dt-bindings: interconnect: Add a dma interconnect name

orm DMA through another bus, > with separate address translation rules. We therefore need to express that > relationship, through the special interconnect name "dma". s/dma/dma-mem/ > > Signed-off-by: Maxime Ripard Acked-by: Georgi Djakov > --- > Documentation/device

Re: [PATCH v3 1/7] dt-bindings: interconnect: Add a dma interconnect name

Hi, On 3/11/19 12:11, Maxime Ripard wrote: > On Fri, Mar 08, 2019 at 12:09:47AM +0800, Chen-Yu Tsai wrote: >> On Thu, Mar 7, 2019 at 11:48 PM Maxime Ripard >> wrote: >>> >>> On Thu, Mar 07, 2019 at 05:15:20PM +0200, Georgi Djakov wrote: >>>> Hi,

Re: [PATCH v3 1/7] dt-bindings: interconnect: Add a dma interconnect name

Hi, On 3/5/19 18:14, Robin Murphy wrote: > On 05/03/2019 15:53, Maxime Ripard wrote: >> Hi, >> >> On Fri, Mar 01, 2019 at 07:48:15PM +0200, Georgi Djakov wrote: >>> On 2/11/19 17:02, Maxime Ripard wrote: >>>> The current DT bindings assume that the

Re: [PATCH v3 1/7] dt-bindings: interconnect: Add a dma interconnect name

Hi Maxime, On 2/11/19 17:02, Maxime Ripard wrote: > The current DT bindings assume that the DMA will be performed by the > devices through their parent DT node, and rely on that assumption for the > address translation using dma-ranges. > > However, some SoCs have devices that will perform DMA th

Re: [PATCH v3 2/3] dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU

power for the GPU. Applicable targets: > - qcom,adreno-630.2 > @@ -68,6 +70,8 @@ Example a6xx (with GMU): > > operating-points-v2 = <&gpu_opp_table>; > > + interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EB

Re: [PATCH v3 1/3] drm/msm/a6xx: Add support for an interconnect path

Hi Rob, On 1/18/19 21:16, Rob Clark wrote: > On Fri, Jan 18, 2019 at 1:06 PM Doug Anderson wrote: >> >> Hi, >> >> On Thu, Dec 20, 2018 at 9:30 AM Jordan Crouse wrote: >>> >>> Try to get the interconnect path for the GPU and vote for the maximum >>> bandwidth to support all frequencies. This is n

Re: [PATCH v4 2/3] drm/msm/dpu: Integrate interconnect API in MDSS

(Matthias Kaehlcke) > > Changes in v4: > - Add comments, spacings, tabs, proper port name > and icc macro (Georgi Djakov) The changes should not be part of the commit text, but should move below the "---" line. > > Signed-off-by: Sravanthi Kollukudu

Re: [PATCH v4 2/3] drm/msm/dpu: Integrate interconnect API in MDSS

Hi, On 9.01.19 18:04, Doug Anderson wrote: > Hi, > > On Wed, Jan 9, 2019 at 6:38 AM Georgi Djakov wrote: >> >> Hi Jayant, >> >> On 12/21/18 08:20, Jayant Shekhar wrote: >>> From: Sravanthi Kollukuduru >>> >>> The interconnect framewo

Re: [PATCH v3 2/3] drm/msm/dpu: Integrate interconnect API in MDSS

Hi Sravanthi, Thanks for the patch! On 11/22/18 11:06, Sravanthi Kollukuduru wrote: > The interconnect framework is designed to provide a > standard kernel interface to control the settings of > the interconnects on a SoC. > > The interconnect API uses a consumer/provider-based model, > where th

Re: [PATCH v3 3/3] dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845

Hi Sravanthi, Thanks for the patch! On 11/22/18 11:06, Sravanthi Kollukuduru wrote: > Add interconnect properties such as interconnect provider specifier > , the edge source and destination ports which are required by the > interconnect API to configure interconnect path for MDSS. > > Changes in

Re: [PATCH 1/1] drm/msm/a6xx: Add support for an interconnect path

Hi Jordan, Thanks for the patch! On 11/29/18 19:26, Jordan Crouse wrote: > Try to get the interconnect path for the GPU and vote for the maximum > bandwidth to support all frequencies. This is needed for performance. > Later we will want to scale the bandwidth based on the frequency to > also opt

Re: [PATCH 6/9] PM / OPP: dt-bindings: Add opp-interconnect-bw

Hi Jordan, Thanks for the patch! On 08/27/2018 06:11 PM, Jordan Crouse wrote: > Add the "opp-interconnect-bw" property to specify the > average and peak bandwidth for an interconnect path for > a specific operating power point. A separate bandwidth > pair can be specified for each of the intercon