Added a4xx GPU support.
Signed-off-by: Aravind Ganesan
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 612
+
drivers/gpu/drm/msm/adreno/a4xx_gpu.h | 34 ++
drivers/gpu/drm/msm/adreno/adreno_device.c | 13 +
Register offsets have changed between a3xx and a4xx GPUs.
To be able access these registers in common code, we create
a lookup table, and set of read-write APIs to access the
register through the lookup table.
Signed-off-by: Aravind Ganesan
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 99 +
Updated a3xx and a4xx headers, generated from rnndb files:
https://github.com/freedreno/envytools
Signed-off-by: Aravind Ganesan
---
drivers/gpu/drm/msm/adreno/a3xx.xml.h | 50 +-
drivers/gpu/drm/msm/adreno/a4xx.xml.h | 2062
+
2 files changed, 2102 insertions(+
A set of three patches to support adreno 4xx GPUs in msm-drm:
(1) Updated the a3xx and a4xx header files.
(2) Handle register offset differences between a3xx and a4xx GPUs.
(3) Added a4xx GPU support.
Changes since v1:
Addressed review comments from Rob.
-Reworked the register offset look-up table
On 11/6/2014 2:13 PM, Rob Clark wrote:
> On Fri, Oct 31, 2014 at 11:08 AM, Ganesan, Aravind
> wrote:
>> Added a4xx GPU support.
>>
>> Signed-off-by: Aravind Ganesan
>> ---
>> Resend the patch-set with the same thread-id
>> Resend in patch-set format a
On 11/6/2014 2:11 PM, Rob Clark wrote:
> On Fri, Oct 31, 2014 at 11:08 AM, Ganesan, Aravind
> wrote:
>> Register offsets have changed between a3xx and a4xx GPUs.
>> To be able access these registers in common code, we create
>> a lookup table, and set of read-
Added a4xx GPU support.
Signed-off-by: Aravind Ganesan
---
Resend the patch-set with the same thread-id
Resend in patch-set format and with dri-devel at lists.freedesktop.org on
the CC.
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 620
+
Register offsets have changed between a3xx and a4xx GPUs.
To be able access these registers in common code, we create
a lookup table, and set of read-write APIs to access the
register through the lookup table.
Signed-off-by: Aravind Ganesan
---
Resend the patch-set with the same thread-id
Resend
Updated a3xx and a4xx headers, generated from rnndb files:
https://github.com/freedreno/envytools
Signed-off-by: Aravind Ganesan
---
Resend the patch-set with the same thread-id
Resend in patch-set format and with dri-devel at lists.freedesktop.org on
the CC.
drivers/gpu/drm/msm/adreno/a3xx.xml
Resend the patch-set with the same thread-id
A set of three patches to support adreno 4xx GPUs in msm-drm:
(1) Updated the a3xx and a4xx header files.
(2) Handle register offset differences between a3xx and a4xx GPUs.
(3) Added a4xx GPU support.
Aravind Ganesan (3):
drm/msm: Additional definitio
Splitting the command sequence for an IB1 submission at the end of
the ring buffer can hang the GPU. To fix this, if there isn't
enough contiguous space at the end to fit the full command sequence,
insert NOPs at the end, and write the sequence at the start, as space
becomes available.
Signed-off
Added a4xx GPU support.
Signed-off-by: Aravind Ganesan
---
Resend in patch-set format and with dri-devel at lists.freedesktop.org on
the CC.
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 620
+
drivers/gpu/drm/msm/adr
Register offsets have changed between a3xx and a4xx GPUs.
To be able access these registers in common code, we create
a lookup table, and set of read-write APIs to access the
register through the lookup table.
Signed-off-by: Aravind Ganesan
---
Resend in patch-set format and with dri-devel at lis
Updated a3xx and a4xx headers, generated from rnndb files:
https://github.com/freedreno/envytools
Signed-off-by: Aravind Ganesan
---
Resend in patch-set format and with dri-devel at lists.freedesktop.org on
the CC.
drivers/gpu/drm/msm/adreno/a3xx.xml.h | 50 +-
drivers/gpu/drm/msm/adreno/a4xx
A set of three patches to support adreno 4xx GPUs in msm-drm:
(1) Updated the a3xx and a4xx header files.
(2) Handle register offset differences between a3xx and a4xx GPUs.
(3) Added a4xx GPU support.
Aravind Ganesan (3):
drm/msm: Additional definitions for a3xx and a4xx
drm/msm: Handle regist
15 matches
Mail list logo