On Mon, Nov 25, 2024 at 05:33:13PM +0800, Liu Ying wrote:
> Add display controller subsystem in i.MX8qxp SoC.
>
> Signed-off-by: Liu Ying
...
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 05138326f0a5..35cc82cbbcd1 100644
> ---
Hello Neil,
On Wed, Oct 23, 2024 at 10:03:20AM +0200, Neil Armstrong wrote:
> On 26/09/2024 16:12, Francesco Dolcini wrote:
> > From: Francesco Dolcini
> >
> > Wait for the command transmission to be completed in the DSI transfer
> > function polling for the dc_s
Hello,
On Thu, Sep 26, 2024 at 04:12:46PM +0200, Francesco Dolcini wrote:
> From: Francesco Dolcini
>
> Wait for the command transmission to be completed in the DSI transfer
> function polling for the dc_start bit to go back to idle state after the
> transmission is starte
From: Francesco Dolcini
Wait for the command transmission to be completed in the DSI transfer
function polling for the dc_start bit to go back to idle state after the
transmission is started.
This is documented in the datasheet and failures to do so lead to
commands corruption.
Fixes
+Max
Hello Aradhya,
On Tue, Jul 16, 2024 at 02:12:44PM +0530, Aradhya Bhatia wrote:
> The addition of the 2nd OLDI TX (and a 2nd DSS in AM62Px) creates a need
> for some major changes for a full feature experience.
>
> 1. The OF graph needs to be updated to accurately show the data flow.
> 2. Th
Hello Liu,
On Fri, Jul 05, 2024 at 05:09:22PM +0800, Liu Ying wrote:
> This patch series aims to add Freescale i.MX8qxp Display Controller support.
I really appreciate your work here, I am looking forward for a better
support in mainline Linux for both i.MX8QXP and i.MX8QP.
With that said, would
Hello Aradhya,
On Sun, May 12, 2024 at 08:53:12PM +0530, Aradhya Bhatia wrote:
> On 12/05/24 17:18, Francesco Dolcini wrote:
> > On Sun, May 12, 2024 at 01:00:55AM +0530, Aradhya Bhatia wrote:
> >> Up till now, the OLDI support in tidss was integrated within the tidss
> &g
Hello Aradhya, thanks for you patch, I should be able to test your patch on my
hardware in the coming days.
On Sun, May 12, 2024 at 01:00:55AM +0530, Aradhya Bhatia wrote:
> Up till now, the OLDI support in tidss was integrated within the tidss dispc.
> This was fine till the OLDI was one-to-mappe
On Wed, Apr 03, 2024 at 09:32:41AM +0300, Alexandru Ardelean wrote:
> I did it like this, because I don't have a board with the P/N in the
You use this 'P/N' both here and in the binding document, to me this is
just too generic and confusing.
Just use some wording that people familiar with the to
Hello Alexandru, thanks for your patch.
On Tue, Apr 02, 2024 at 01:59:24PM +0300, Alexandru Ardelean wrote:
> On some HW designs, it's easier for the layout if the P/N pins are swapped.
> In those cases, we need to adjust (for this) by configuring the MIPI analog
> registers differently. Specifica
On Sat, Feb 03, 2024 at 10:52:46AM -0600, Adam Ford wrote:
> From: Lucas Stach
>
> The HDMI irqsteer is a secondary interrupt controller within the HDMI
> subsystem that maps all HDMI peripheral IRQs into a single upstream
> IRQ line.
>
> Signed-off-by: Lucas Stach
This is missing your signed-
On Thu, Jan 04, 2024 at 08:20:37PM +0100, Francesco Dolcini wrote:
> On Mon, Dec 18, 2023 at 11:57:15AM +0100, Alexander Stein wrote:
> > This simplifies the code and gives additional information upon deferral.
> >
> > Signed-off-by: Alexander Stein
> Reviewed-by: Fr
On Mon, Dec 18, 2023 at 11:57:15AM +0100, Alexander Stein wrote:
> This simplifies the code and gives additional information upon deferral.
>
> Signed-off-by: Alexander Stein
Reviewed-by: Francesco Dolcini
From: Stefan Eichenberger
Add supplies to the driver that can be used to turn the Lontium lt8912b
on and off. It can have up to 7 independent supplies, we add them all
and enable/disable them with bulk_enable/disable.
Signed-off-by: Stefan Eichenberger
Signed-off-by: Francesco Dolcini
From: Stefan Eichenberger
Add support for suspend and resume. The lt8912b will power off when
going into suspend and power on when resuming.
Signed-off-by: Stefan Eichenberger
Signed-off-by: Francesco Dolcini
---
drivers/gpu/drm/bridge/lontium-lt8912b.c | 28
1 file
From: Francesco Dolcini
Add support for suspend and resume, power off the bridge when going into
suspend and power on when resuming.
Stefan Eichenberger (3):
drm/bridge: lt8912b: Add suspend/resume support
dt-bindings: display: bridge: lt8912b: Add power supplies
drm/bridge: lt8912b: Add
From: Stefan Eichenberger
Add Lontium lt8912b power supplies.
Signed-off-by: Stefan Eichenberger
Signed-off-by: Francesco Dolcini
---
.../display/bridge/lontium,lt8912b.yaml | 21 +++
1 file changed, 21 insertions(+)
diff --git
a/Documentation/devicetree/bindings
On Wed, Nov 01, 2023 at 11:17:47AM +0200, Tomi Valkeinen wrote:
> tidss_crtc_atomic_flush() checks if the crtc is enabled, and if not,
> returns immediately as there's no reason to do any register changes.
>
> However, the code checks for 'crtc->state->enable', which does not
> reflect the actual
On Wed, Nov 01, 2023 at 11:17:44AM +0200, Tomi Valkeinen wrote:
> The probe function calls dispc_softreset() before runtime PM is enabled
> and without enabling any of the DSS clocks. This happens to work by
> luck, and we need to make sure the DSS HW is active and the fclk is
> enabled.
Not sure
On Mon, Apr 03, 2023 at 09:02:42PM +0200, Marek Vasut wrote:
> Do not generate the HS front and back porch gaps, the HSA gap and
> EOT packet, as per "SN65DSI83 datasheet SLLSEC1I - SEPTEMBER 2012
> - REVISED OCTOBER 2020", page 22, these packets are not required.
> This makes the TI SN65DSI83 brid
From: Francesco Dolcini
Remove unneeded stray semicolon.
Reported-by: kernel test robot
Link: https://lore.kernel.org/oe-kbuild-all/202305152341.oisjrpv6-...@intel.com/
Signed-off-by: Francesco Dolcini
---
drivers/gpu/drm/bridge/tc358768.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Francesco Dolcini
Correct computation of THS_TRAILCNT register.
This register must be set to a value that ensure that
THS_TRAIL > 60 ns + 4 x UI
and
THS_TRAIL > 8 x UI
and
THS_TRAIL < TEOT
with
TEOT = 105 ns + (12 x UI)
with the actual value of THS_TRAIL being
(1 + THS_TR
From: Francesco Dolcini
Correct computation of TCLK_TRAILCNT register.
The driver does not implement non-continuous clock mode, so the actual
value doesn't make a practical difference yet. However this change also
ensures that the value does not write to reserved registers bits in case
of
From: Francesco Dolcini
Correct computation of TXTAGOCNT register.
This register must be set to a value that ensure that the
TTA-GO period = (4 x TLPX)
with the actual value of TTA-GO being
4 x (TXTAGOCNT + 1) x (HSByteClk cycle)
Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver&quo
From: Francesco Dolcini
Remove the unused phy_delay_nsk variable, before it was wrongly used
to compute some register value, the fixed computation is no longer using
it and therefore can be removed.
Signed-off-by: Francesco Dolcini
---
drivers/gpu/drm/bridge/tc358768.c | 4 +---
1 file
From: Francesco Dolcini
Correct computation of THS_ZEROCNT register.
This register must be set to a value that ensure that
THS_PREPARE + THS_ZERO > 145ns + 10*UI
with the actual value of (THS_PREPARE + THS_ZERO) being
((1 to 2) + 1 + (TCLK_ZEROCNT + 1) + (3 to 4)) x ByteClk cy
From: Francesco Dolcini
According to Toshiba documentation the PLL input clock after the divider
should be not less than 4MHz, fix the PLL parameters computation
accordingly.
Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver")
Signed-off-by: Francesco Dolcini
---
drivers/gpu/
From: Francesco Dolcini
Always enable HS video mode setting the TXMD bit, without this change no
video output is present with DSI sinks that are setting
MIPI_DSI_MODE_LPM flag (tested with LT8912B DSI-HDMI bridge).
Previously the driver was enabling HS mode only when the DSI sink was
not
From: Francesco Dolcini
Correctly compute the PLL target frequency, the current formula works
correctly only when the input bus width is 24bit, actually to properly
compute the PLL target frequency what is relevant is the bits-per-pixel
on the DSI link.
No regression expected since the DSI
From: Francesco Dolcini
Correct computation of TCLK_ZEROCNT register.
This register must be set to a value that ensure that
(TCLK-PREPARECNT + TCLK-ZERO) > 300ns
with the actual value of (TCLK-PREPARECNT + TCLK-ZERO) being
(1 to 2) + (TCLK_ZEROCNT + 1)) x HSByteClkCycle + (PHY output de
From: Francesco Dolcini
This series includes multiple fixes on the tc358768 parallel RGB to DSI driver.
With the following changes I am able to have a stable display output using a TI
SN65DSI83 (DSI-LVDS bridge) and a 1280 x 800 LVDS display panel and the
register values are coherent with
Hello all,
On Thu, Mar 30, 2023 at 11:59:41AM +0200, Francesco Dolcini wrote:
> From: Francesco Dolcini
>
> Add atomic_get_input_bus_fmts() implementation, tc358768 has a parallel
> RGB input interface with the actual bus format depending on the amount
> of parallel i
Hello Rob and Krzysztof
On Mon, Apr 03, 2023 at 04:01:17PM -0500, Rob Herring wrote:
> On Fri, Mar 31, 2023 at 11:40:01AM +0200, Francesco Dolcini wrote:
> > On Fri, Mar 31, 2023 at 10:48:15AM +0200, Krzysztof Kozlowski wrote:
> > > On 30/03/2023 11:59, Francesco Dolcini w
Hello Aradhya,
On Fri, Apr 14, 2023 at 01:19:38PM +0530, Aradhya Bhatia wrote:
> On 30-Mar-23 22:47, Francesco Dolcini wrote:
> > Hello,
> > chiming in in this *old* email thread.
> >
> > Adding in copy a few more *@ti.com people recently involved in other tidss
>
On Mon, Apr 03, 2023 at 04:01:17PM -0500, Rob Herring wrote:
> On Fri, Mar 31, 2023 at 11:40:01AM +0200, Francesco Dolcini wrote:
> > On Fri, Mar 31, 2023 at 10:48:15AM +0200, Krzysztof Kozlowski wrote:
> > > On 30/03/2023 11:59, Francesco Dolcini wrote:
> > >
On Mon, Apr 03, 2023 at 04:06:22PM -0500, Rob Herring wrote:
> On Thu, Mar 30, 2023 at 12:17:51PM +0200, Francesco Dolcini wrote:
> > From: Francesco Dolcini
> >
> > SN65DSI8[34] device supports burst video mode and non-burst video mode
> > with sync events
On Mon, Apr 03, 2023 at 04:01:17PM -0500, Rob Herring wrote:
> On Fri, Mar 31, 2023 at 11:40:01AM +0200, Francesco Dolcini wrote:
> > On Fri, Mar 31, 2023 at 10:48:15AM +0200, Krzysztof Kozlowski wrote:
> > > On 30/03/2023 11:59, Francesco Dolcini wrote:
> > >
On Fri, Mar 31, 2023 at 11:06:44AM +0200, Neil Armstrong wrote:
> Hi,
>
> On 30/03/2023 12:17, Francesco Dolcini wrote:
> > From: Francesco Dolcini
> >
> > Enable configuration of the DSI video mode instead of hard-coding
> > MIPI_DSI_MODE_VIDEO_BURST. The
On Fri, Mar 31, 2023 at 10:48:15AM +0200, Krzysztof Kozlowski wrote:
> On 30/03/2023 11:59, Francesco Dolcini wrote:
> > From: Francesco Dolcini
> >
> > Add new toshiba,input-rgb-mode property to describe the actual signal
> > connection on the parallel RGB input int
On Fri, Mar 31, 2023 at 10:42:40AM +0200, Krzysztof Kozlowski wrote:
> On 30/03/2023 11:59, Francesco Dolcini wrote:
> > From: Francesco Dolcini
> >
> > Add TC9594, from the software point of view this is identical to
> > TC358768 with the main difference
Hello,
chiming in in this *old* email thread.
Adding in copy a few more *@ti.com people recently involved in other tidss
changes [1]
[1] https://lore.kernel.org/all/20230125113529.13952-1-a-bhat...@ti.com/
On Fri, Dec 04, 2020 at 11:50:30AM +0100, Boris Brezillon wrote:
> On Tue, 1 Dec 2020 17
On Thu, Mar 30, 2023 at 07:56:26PM +0530, Jagan Teki wrote:
> On Thu, Mar 30, 2023 at 3:48 PM Francesco Dolcini
> wrote:
> >
> > From: Francesco Dolcini
> >
> > SN65DSI8[34] device supports burst video mode and non-burst video mode
> > with sync events or wit
From: Francesco Dolcini
Enable configuration of the DSI video mode instead of hard-coding
MIPI_DSI_MODE_VIDEO_BURST. The bridge support any of burst-mode,
non-burst with sync event or non-burst with sync pulse
With this change is possible to use the bridge with host DSI
that do not support
From: Francesco Dolcini
SN65DSI8[34] device supports burst video mode and non-burst video mode
with sync events or with sync pulses packet transmission as described in
the DSI specification.
Add property to select the expected mode, this allows for example to
select a mode that is compatible
From: Francesco Dolcini
SN65DSI8[34] device supports burst video mode and non-burst video mode with
sync events or with sync pulses packet transmission as described in the DSI
specification.
Enable configuration of the DSI video mode instead of hard-coding
MIPI_DSI_MODE_VIDEO_BURST.
Francesco
From: Francesco Dolcini
Correct Toshiba spelling.
Signed-off-by: Francesco Dolcini
---
.../devicetree/bindings/display/bridge/toshiba,tc358768.yaml| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/display/bridge/toshiba,tc358768.yaml
b
From: Francesco Dolcini
Add TC9594, from the software point of view this is identical to
TC358768 with the main difference being automotive qualified.
Signed-off-by: Francesco Dolcini
---
.../devicetree/bindings/display/bridge/toshiba,tc358768.yaml | 5 +++--
1 file changed, 3 insertions
From: Francesco Dolcini
Add support for different parallel RGB input format and mapping, this enables
using the TC358768 when the parallel input width is less than 24-bit or the
input mapping is not the default one.
In addition to that this series add support for the TC9594, that is the
From: Francesco Dolcini
Add TC9594 ids, from the software point of view this is fully compatible
with tc358768, the only difference is the automotive qualification.
Signed-off-by: Francesco Dolcini
---
drivers/gpu/drm/bridge/tc358768.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a
From: Francesco Dolcini
Add configuration for parallel data format register, tc358768 supports
different mapping on the parallel input RGB interface, enable the
configuration for it.
Valid values, and the related meaning, are:
0 = R[7:0], G[7:0], B[7:0]
1 = R[1:0], G[1:0], B[1:0], R[7:2], G
From: Francesco Dolcini
Add atomic_get_input_bus_fmts() implementation, tc358768 has a parallel
RGB input interface with the actual bus format depending on the amount
of parallel input data lines.
Without this change when the tc358768 is used with less than 24bit the
color mapping is completely
From: Francesco Dolcini
Add new toshiba,input-rgb-mode property to describe the actual signal
connection on the parallel RGB input interface.
Signed-off-by: Francesco Dolcini
---
.../bindings/display/bridge/toshiba,tc358768.yaml | 15 +++
1 file changed, 15 insertions(+)
diff
From: Francesco Dolcini
LT8912 DSI port supports only Non-Burst mode video operation with Sync
Events and continuous clock on clock lane, correct dsi mode flags
according to that removing MIPI_DSI_MODE_VIDEO_BURST flag.
Cc:
Fixes: 30e2ae943c26 ("drm/bridge: Introduce LT8912B DSI to HDMI b
: 30e2ae943c26 ("drm/bridge: Introduce LT8912B DSI to HDMI bridge")
Signed-off-by: Matheus Castello
Signed-off-by: Francesco Dolcini
---
v2: use dev_err_probe() instead of dev_dbg() (Laurent)
---
drivers/gpu/drm/bridge/lontium-lt8912b.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
di
: 30e2ae943c26 ("drm/bridge: Introduce LT8912B DSI to HDMI bridge")
Signed-off-by: Matheus Castello
Signed-off-by: Francesco Dolcini
---
drivers/gpu/drm/bridge/lontium-lt8912b.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/lontium-lt8912b.c
b/drive
SI to HDMI bridge")
Signed-off-by: Stefan Eichenberger
Signed-off-by: Francesco Dolcini
---
drivers/gpu/drm/bridge/lontium-lt8912b.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/lontium-lt8912b.c
b/drivers/gpu/drm/brid
On Mon, Oct 17, 2022 at 04:18:13PM +0200, Francesco Dolcini wrote:
> On Wed, Aug 31, 2022 at 04:16:22PM +0200, Francesco Dolcini wrote:
> > From: Aishwarya Kothari
> >
> > In case bpc is not set for a panel it then throws a WARN(). Add bpc to
> > the panels lo
On Wed, Oct 19, 2022 at 06:54:59PM +0200, Francesco Dolcini wrote:
> Hello all,
> I got the following Oops, on a Apalis iMX6 Dual with 512MB RAM,
> running glmark2 tests with the system under memory pressure (OOM
> Killer!).
>
> It's not something systematic and I c
Hello all,
I got the following Oops, on a Apalis iMX6 Dual with 512MB RAM,
running glmark2 tests with the system under memory pressure (OOM
Killer!).
It's not something systematic and I cannot tell if this is a regression
or not, any suggestion? The system just froze afterward.
[0.00] Boo
On Wed, Aug 31, 2022 at 04:16:22PM +0200, Francesco Dolcini wrote:
> From: Aishwarya Kothari
>
> In case bpc is not set for a panel it then throws a WARN(). Add bpc to
> the panels logictechno_lt170410_2whc and logictechno_lt161010_2nh.
>
> Fixes: 5728fe7fa539 ("drm/pan
Hello Max, Marek, Dave et al.
On Tue, Jun 28, 2022 at 08:18:36PM +0200, Max Krummenacher wrote:
> From: Max Krummenacher
>
> The property is used to set the enum bus_format and infer the bpc
> for a panel defined by 'panel-dpi'.
> This specifies how the panel is connected to the display interfac
On Wed, Mar 23, 2022 at 09:06:18PM +0100, Max Krummenacher wrote:
> Am Mittwoch, den 23.03.2022, 16:58 +0100 schrieb Maxime Ripard:
> > On Wed, Mar 23, 2022 at 09:42:11AM +0100, Max Krummenacher wrote:
> > > I would copy the definitions of media-bus-format.h into a header in
> > > include/dt-bindin
Hello all,
just a gently ping on this patch.
Any concern? We (Toradex) added this panel long time ago and we are
using this updated timing since a long time now.
Francesco
On Thu, Jan 27, 2022 at 12:48:10PM +0100, Francesco Dolcini wrote:
> From: Oleksandr Suvorov
>
> VESA Displa
: Oleksandr Suvorov
Signed-off-by: Francesco Dolcini
---
v2: removed stale vrefresh field
---
drivers/gpu/drm/panel/panel-simple.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 0c8786ebffd1
: Oleksandr Suvorov
Signed-off-by: Francesco Dolcini
---
drivers/gpu/drm/panel/panel-simple.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 9e46db5e359c..c11427f94ac5 100644
--- a/drivers
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