gned-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
MDSS sets it only for a610 as there seems to be no UBWC support on the
display side of QCM2290.
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
From: Dmitry Baryshkov
Move several misnamed functions accessing AUX bus to dp_aux.c, further
cleaning up dp_catalog submodule.
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_aux.c | 94
From: Dmitry Baryshkov
Move all register-level functions to dp_aux.c, inlining one line
wrappers during this process.
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_aux.c | 96
From: Dmitry Baryshkov
Move CTRL-related functions to dp_ctrl.c, inlining one line wrappers
during this process. The enable/disable functions have been split to the
enable/disable or enter/exit pairs. The IRQ and HPD related functions
are left in dp_catalog.c, pending later cleanup.
Reviewed-by
From: Dmitry Baryshkov
Having I/O regions inside a msm_dp_catalog_private() results in extra
layers of one-line wrappers for accessing the data. Move I/O region base
and size to the globally visible struct msm_dp_catalog.
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
From: Dmitry Baryshkov
Now as the msm_dp_catalog module became nearly empty, drop it, accessing
registers directly from the corresponding submodules.
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
From: Dmitry Baryshkov
There is little point in rereading DP controller revision over and over
again. Read it once, after the first software reset.
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 29
From: Dmitry Baryshkov
It makes it easier to keep all interrupts-related code in dp_ctrl
submodule. Move all functions to dp_ctrl.c.
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_aux.c | 9 +--
drivers
From: Dmitry Baryshkov
It's the dp_panel's duty to clear the MMSS_DP_DSC_DTO register. Once DP
driver gets DSC support, it will handle that register in other places
too. Split a call to write 0x0 to that register to a separate function.
Reviewed-by: Stephen Boyd
Tested-by: St
Rework most of the register programming functions to be local to the
calling module rather than accessing everything through huge dp_catalog
monster.
Signed-off-by: Dmitry Baryshkov
---
Changes in v6:
- Rebased on top of the linux-next
- Link to v5:
https://lore.kernel.org/r/20241222-fd-dp
From: Dmitry Baryshkov
Move audio-related functions to dp_audio.c, following up the cleanup
done by the rest of the submodules. Inline functions with simple
register access patterns.
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
Signed-off-by: Dmitry Baryshkov
From: Dmitry Baryshkov
Move panel-related functions to dp_panel.c, following up the cleanup
done by the rest of the submodules.
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 195
From: Dmitry Baryshkov
Move msm_dp_read()/msm_write_foo() functions to the dp_catalog.h,
allowing other modules to access the data directly.
Reviewed-by: Stephen Boyd
Tested-by: Stephen Boyd # sc7180-trogdor
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 65
Both perf and hangrd make sense only for GPU devices. Bail out if we are
registering a KMS-only device.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_debugfs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_debugfs.c
b/drivers/gpu/drm/msm
(&data->lock);
> idr_init(&data->ctx_idr);
> data->domain_id = domain_id;
> - data->rpdev = rpdev;
>
> err = of_platform_populate(rdev->of_node, NULL, NULL, rdev);
> if (err)
> goto populate_error;
>
> + data->rpdev = rpdev;
> +
> return 0;
>
> populate_error:
> --
> 2.34.1
>
--
With best wishes
Dmitry
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 36 +++-
drivers/gpu/drm/msm/msm_drv.c | 91 --
drivers/gpu/drm/msm/msm_drv.h | 4 ++
3 files changed, 72 insertions(+), 59 deletions(-)
diff --git a/
IOMMU setup.
Rework the driver:
- Make it possible to disable KMS parts (if MDP4, MDP5 and DPU drivers
are disabled).
- Register GPU-only devices without an interim platform device.
- Add module param that makes msm driver register GPU and KMS devices
separately.
Signed-off-by: Dmitry Baryshkov
On Wed, May 07, 2025 at 09:45:26AM -0700, Rob Clark wrote:
> On Sat, May 3, 2025 at 12:17 AM Dmitry Baryshkov
> wrote:
> >
> > Some of the platforms don't have onboard GPU or don't provide support
> > for the GPU in the drm/msm driver. Make it possible to disa
Some of the platforms don't have onboard GPU or don't provide support
for the GPU in the drm/msm driver. Make it possible to disable the GPU
part of the driver and build the KMS-only part.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 25 +--
drive
this
setup automatically.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 3 +-
drivers/gpu/drm/msm/msm_drv.c | 47 +++---
drivers/gpu/drm/msm/msm_drv.h | 2 ++
3 files changed, 47 insertions(+), 5 deletions(-)
diff --git
Move symbol selection to be more fine grained: select DP helpers only if
DP driver is also enabled, move KMS and display helpers to the newly
introduced DRM_MSM_KMS.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 20 ++--
1 file changed, 10 insertions(+), 10
Extract two more KMS-related codepieces to msm_kms.c, removing last
pieces of KMS code from msm_drv.c.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_drv.c | 9 +++--
drivers/gpu/drm/msm/msm_kms.c | 20
drivers/gpu/drm/msm
If the Adreno device is used in a headless mode, there is no need to
build all KMS components. Build corresponding parts conditionally, only
selecting them if modeset support is actually required.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 14 +
drivers
There is no reason to store CRTC id, it's a part of the drm_crtc. Drop
this member and use drm_crtc.name for the warning message.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 7 ++-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +-
drivers/gpu/drm/msm
Data for HDMI, DSI and DP blocks only makes sense for the KMS parts of
the driver. Move corresponding data pointers from struct msm_drm_private
to struct msm_kms.
Suggested-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11
Drop superfluous msm_drm_private::num_crtcs in favour of using
drm_mode_config::num_crtc or MAX_CRCS as appropriate.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +--
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 3 ---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
The global workqueue is only used for vblanks inside KMS code. Move
allocation / flushing / deallcation of it to msm_kms.c
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 2 +-
drivers/gpu/drm/msm/disp/mdp5
gt; 4 files changed, 60 insertions(+), 87 deletions(-)
>
Acked-by: Dmitry Baryshkov
--
With best wishes
Dmitry
/qcom/ubwc_config.c | 18 ++
> 1 file changed, 18 insertions(+)
Ideally we should test this on relevant platforms, the commit LGTM
Reviewed-by: Dmitry Baryshkov
>
> diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
> index
> f
ux/soc/qcom/ubwc.h | 8
> 2 files changed, 29 insertions(+), 16 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
(the hardware doesn't care about the 2 higher
> bits, as they weren't consumed on this platform).
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/soc/qcom/ubwc_config.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov
>
--
With best wishes
Dmitry
.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
gt; + u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
Nit: UBWC_SWIZZLE_ENABLE_LVL2 ?
Reviewed-by: Dmitry Baryshkov
> bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
> bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
> u8 uavflagprd_inv = 0;
> u32
t; patchset is intended to be merged together, with a maintainer
> consensus.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
> include/linux/soc/qcom/ubwc.h | 10 ++
> 2 files changed, 11 insertions(+), 1 deletion(-)
gpu/drm/msm/adreno/a6xx_gpu.c | 15 ++-
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
| 12 +++-
> 1 file changed, 3 insertions(+), 9 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
I've started a work on splitting GPU part,
but it is not yet merged.
--
With best wishes
Dmitry
1/dpu_rm.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 +-
> drivers/gpu/drm/msm/msm_mdss.c | 327
> +---
> drivers/gpu/drm/msm/msm_mdss.h | 28 ---
> 10 files changed, 73 insertions(+), 309 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
bwc_cfg_data {
> + u32 ubwc_enc_version;
> + /* Can be read from MDSS_BASE + 0x58 */
> + u32 ubwc_dec_version;
> +
> + /**
> + * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.
> + *
> + * UBWC 1.0 always enables all three levels.
> + * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
> + * UBWC 4.0 adds the optional ability to disable levels 2 & 3.
> + *
> + * This is a bitmask where BIT(0) enables level 1, BIT(1)
> + * controls level 2, and BIT(2) enables level 3.
> + */
> + u32 ubwc_swizzle;
> +
> + /**
> + * @highest_bank_bit: Highest Bank Bit
> + *
> + * The Highest Bank Bit value represents the bit of the highest
> + * DDR bank. This should ideally use DRAM type detection.
> + */
> + int highest_bank_bit;
> + bool ubwc_bank_spread;
> +
> + /**
> + * @macrotile_mode: Macrotile Mode
> + *
> + * Whether to use 4-channel macrotiling mode or the newer
> + * 8-channel macrotiling mode introduced in UBWC 3.1. 0 is
> + * 4-channel and 1 is 8-channel.
> + */
> + bool macrotile_mode;
> +};
> +
> +#define UBWC_1_0 0x1000
> +#define UBWC_2_0 0x2000
> +#define UBWC_3_0 0x3000
> +#define UBWC_4_0 0x4000
> +#define UBWC_4_3 0x4003
> +
> +const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void);
Looking at the LKP report for the Adreno patch... Should we provide a
stub here for the platforms like iMX5 (it has a2xx, so it doesn't make
sense to pull this driver in, a stub will be enough).
> +
> +#endif /* __QCOM_UBWC_H__ */
>
> --
> 2.49.0
>
--
With best wishes
Dmitry
Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 50
> +-
> 1 file changed, 25 insertions(+), 25 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
are supported. Existing driver
doesn't support programming any other InfoFrames directly and Audio
InfoFrame seems to be programmed using individual bits and pieces rather
than programming it directly.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/b
Switch VC4 driver to using CEC helpers code, simplifying hotplug and
registration / cleanup. The existing vc4_hdmi_cec_release() is kept for
now.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/vc4/Kconfig| 1 +
drivers/gpu/drm/vc4/vc4_hdmi.c | 137
example, currently it will be either cec_notifier
or cec_adapter + drm_connector_hdmi_cec_funcs. Later cec-pin might store
platform callbacks here. DP CEC might need to store AUX pointer, etc.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/drm_connector.c | 42
kernel even if DRM_DISPLAY_HELPER is
selected to be built as a module. Move CEC_CORE selection to the latter
symbol in order to allow it to be built as a module.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/Kconfig | 2 +-
1
that would
either require a state or storing drm_connector inside a drm_bridge.
Current code stores cec_adapter instead.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
Changes in v6:
- Fixed vc4 to build with changed API (Maxime)
- Reworked helpers to use drmm to unre
WHen adding HDMI fields I didn't notice the private: declaration for HPD
fields. Move private fields to the end of the struct drm_bride to have
clear distinction between private and public fields.
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Bary
Allow HDMI DRM bridges to create CEC notifier. Physical address is
handled automatically by drm_atomic_helper_connector_hdmi_hotplug()
being called from .detect() path.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display
Implement necessary glue code to let DRM bridge drivers to implement CEC
adapters support.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/Kconfig| 1 +
drivers/gpu/drm/display/drm_bridge_connector.c | 83
interface common to all implementations, including, but
not limited to the CEC adapter, CEC notifier, CEC pin-based adapter,
etc) the struct drm_connector_hdmi_cec_adapter_ops provides callbacks
specific to the CEC adapter implementations.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry
Call HDMI CEC helpers in order to update physical address of the
adapter.
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_hdmi_state_helper.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a
By default HDMI codec registers all formats supported on the I2S bus.
Allow bridges (and connectors) to limit the list of the PCM formats
supported by the HDMI codec.
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display
On Thu, May 15, 2025 at 05:48:09PM -0700, Jessica Zhang wrote:
>
>
> On 5/14/2025 5:17 PM, Dmitry Baryshkov wrote:
> > On Thu, 15 May 2025 at 02:52, Jessica Zhang
> > wrote:
> > >
> > > Since the max mixer width is not a strict hardware limit, use the ac
On Fri, 16 May 2025 at 03:39, Jessica Zhang
wrote:
>
>
>
> On 5/14/2025 5:28 PM, Dmitry Baryshkov wrote:
> > On Wed, May 14, 2025 at 04:52:31PM -0700, Jessica Zhang wrote:
> >> Validate requested mode and topology based on the PINGPONG or DSC encoder
> &
On Thu, 15 May 2025 at 19:36, Konrad Dybcio
wrote:
>
> On 5/15/25 6:21 PM, Dmitry Baryshkov wrote:
> > On 15/05/2025 19:18, Konrad Dybcio wrote:
> >> On 5/14/25 10:33 PM, Dmitry Baryshkov wrote:
> >>> On 14/05/2025 23:05, Konrad Dybcio wrote:
> >>>
On 15/05/2025 20:56, Konrad Dybcio wrote:
On 5/15/25 7:15 PM, Dmitry Baryshkov wrote:
On Thu, 15 May 2025 at 19:36, Konrad Dybcio
wrote:
On 5/15/25 6:21 PM, Dmitry Baryshkov wrote:
On 15/05/2025 19:18, Konrad Dybcio wrote:
On 5/14/25 10:33 PM, Dmitry Baryshkov wrote:
On 14/05/2025 23:05
On 15/05/2025 19:18, Konrad Dybcio wrote:
On 5/14/25 10:33 PM, Dmitry Baryshkov wrote:
On 14/05/2025 23:05, Konrad Dybcio wrote:
On 5/14/25 9:23 PM, Dmitry Baryshkov wrote:
On Wed, May 14, 2025 at 05:10:33PM +0200, Konrad Dybcio wrote:
From: Konrad Dybcio
The value of 7 (a.k.a. GENMASK(2
h | 1 -
> 2 files changed, 5 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_c
inewidth);
> + }
Since we are skipping PINGPONG_0, wouldn't it be enough to return
max_linewidth of PP_1 ?
I think, it would be easier to follow .max_dsc_encoder_width and store
.max_pingpong_linewidth in dpu_caps (and later add special
.max_pp0_linewidth).
> +
> + return max_pingpong_width;
> +}
> +
> static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc,
> struct drm_crtc_state *state)
> {
--
With best wishes
Dmitry
1/catalog/dpu_9_2_x1e80100.h | 9 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 10 ++
This needs to be rebased on top of linux-next, otherwise you've missed
dpu_9_1_sar2130p.h .
--
With best wishes
Dmitry
On Thu, 15 May 2025 at 02:52, Jessica Zhang
wrote:
>
> Since the max mixer width is not a strict hardware limit, use the actual
Is it? What is the actual max width that the mixer can support?
> hardware limit (the writeback maxlinewidth) to filter modes.
>
> Signed-off-by: Jessica Zhang
> ---
>
On 14/05/2025 23:05, Konrad Dybcio wrote:
On 5/14/25 9:23 PM, Dmitry Baryshkov wrote:
On Wed, May 14, 2025 at 05:10:33PM +0200, Konrad Dybcio wrote:
From: Konrad Dybcio
The value of 7 (a.k.a. GENMASK(2, 0), a.k.a. disabling levels 1-3 of
swizzling) is what we want on this platform (and
On Wed, May 14, 2025 at 10:09:35PM +0200, Konrad Dybcio wrote:
> On 5/14/25 9:24 PM, Dmitry Baryshkov wrote:
> > On Wed, May 14, 2025 at 05:10:34PM +0200, Konrad Dybcio wrote:
> >> From: Konrad Dybcio
> >>
> >> Make the values a bit more meaningful.
> >
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
--
With best wishes
Dmitry
clusive highest_bank_bit value: %u (GPU) vs
> %u (UBWC_CFG)\n",
> + cfg->highest_bank_bit,
> common_cfg->highest_bank_bit);
> +
This really should come in an earlier patch...
> gpu->ubwc_config = &gpu->_ubwc_config;
>
> return 0;
>
> --
> 2.49.0
>
--
With best wishes
Dmitry
5d2e06d4aa93b64f7d2bc0e855c7a10b..2a12e054ec62ae7e76c3f3291d6963da726eee4f
> 100644
> --- a/include/linux/soc/qcom/ubwc.h
> +++ b/include/linux/soc/qcom/ubwc.h
> @@ -26,6 +26,8 @@ struct qcom_ubwc_cfg_data {
>* controls level 2, and BIT(2) enables level 3.
>*/
> u32 ubwc_swizzle;
> +#define UBWC_SWIZZLE_ENABLE_ALL GENMASK(2, 0)
> +#define UBWC_SWIZZLE_ENABLE_LVL(n) BIT(((n) - 1))
>
> /**
>* @highest_bank_bit: Highest Bank Bit
>
> --
> 2.49.0
>
--
With best wishes
Dmitry
m_ubwc_cfg_data sm6115_data = {
> static const struct qcom_ubwc_cfg_data sm6125_data = {
> .ubwc_enc_version = UBWC_1_0,
> .ubwc_dec_version = UBWC_3_0,
> - .ubwc_swizzle = 1,
> + .ubwc_swizzle = 7,
> .highest_bank_bit = 14,
> };
Add a comment and squash into the patch 1.
--
With best wishes
Dmitry
>ubwc_swizzle = 0x6;
> + cfg->highest_bank_bit = 15;
>
This begs for WARN_ON(cfg->ubwc_swizzle !=
gpu->common_ubwc_cfg->ubwc_swizzle) and similar change for HBB. Then
after testing we should be able to drop r/w part of the config.
> if (adreno_is_a610(gpu)) {
> - gpu->ubwc_config.highest_bank_bit = 13;
> - gpu->ubwc_config.ubwc_swizzle = 0x7;
> + cfg->highest_bank_bit = 13;
> + cfg->ubwc_swizzle = 0x7;
> }
>
>
--
With best wishes
Dmitry
you stopped
setting the field, but you didn't drop it from adreno_gpu.ubwc_config.
Would you mind updating the patches in this way?
With that fixed:
Reviewed-by: Dmitry Baryshkov
>
> if (adreno_is_a610(gpu)) {
> gpu->ubwc_config.highest_b
| 12 +++-
> 1 file changed, 3 insertions(+), 9 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
insertion(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov
>
--
With best wishes
Dmitry
viewing.
> bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
> u32 hbb_hi = hbb >> 2;
> u32 hbb_lo = hbb & 3;
> - u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
> u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);
>
> gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
>
> --
> 2.49.0
>
--
With best wishes
Dmitry
level2_swizzling_dis << 12 | hbb_hi << 10 |
> - adreno_gpu->ubwc_config.uavflagprd_inv << 4 |
> + uavflagprd_inv << 4 |
> adreno_gpu->ubwc_config.min_acc_len << 3 |
> hbb_lo << 1 | ubwc_mode);
>
>
> --
> 2.49.0
>
--
With best wishes
Dmitry
1/dpu_rm.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 +-
> drivers/gpu/drm/msm/msm_mdss.c | 327
> +---
> drivers/gpu/drm/msm/msm_mdss.h | 28 ---
> 10 files changed, 73 insertions(+), 309 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 50
> +-
> 1 file changed, 25 insertions(+), 25 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
qcom/Kconfig | 8 ++
> drivers/soc/qcom/Makefile | 1 +
> drivers/soc/qcom/ubwc_config.c | 235
> +
> include/linux/soc/qcom/ubwc.h | 67
> 4 files changed, 311 insertions(+)
>
With the SAR
On 5/13/25 22:23, Kim, Dongwon wrote:
> Hi Dmitry,
>
> Can you share some details about your test setup?
> How do I replicate the problem you saw? And is "suspend and resume" working
> by default in your case?
My testing setup:
- QEMU staging tree
- Guest kernel 6.14
Turn on the switch and use virtual planes by default, enhancing
utilisation of the display pipelines. It is still possible to use legacy
implementation by using `msm.dpu_use_virtual_planes=false` kernel boot
parameter.
Signed-off-by: Dmitry Baryshkov
---
This is being sent as an RFT for now
The SDM845 Cheeza runners are currently offline. Disable them until they
come back again.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/ci/test.yml | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu
The msm_mapping@shadow test fails on SM8350, which means that the write
might get through (hopefully not though). Disable the test completely
for now until we can fix the issue.
Link: https://gitlab.freedesktop.org/drm/msm/-/issues/77
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/ci
be valid until the object is
> freed as we took a reference on it in virtgpu_gem_prime_import().
>
> Fixes: 415cb45895f4 ("drm/virtio: Use dma_buf from GEM object instance")
> Cc: Dmitry Osipenko
> Cc: Thomas Zimmermann
> Signed-off-by: Vivek Kasireddy
> ---
>
On Mon, May 12, 2025 at 12:13:40AM +0300, Dmitry Baryshkov wrote:
> On Fri, May 09, 2025 at 02:28:55PM +0200, Konrad Dybcio wrote:
> > On 5/8/25 10:12 PM, Connor Abbott wrote:
> > > On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio
> > > wrote:
> > >>
> >
anything, as we're taking numbers that translate to ANYTHING_ABOVE_OFF
> or
> ANYTHING_ABOVE_OFF_PLUS_1 in most cases wrt a cpu-ipblock path.
I'd rather not do that. Let me check if I can cook it on top of your
series.
>
> >
> >> +};
> >
> > The comments should be copied over from the Adreno struct. That was
> > the main way the meaning of most of these was documented and you're
> > deleting it here.
>
> I'll do that.
>
> Konrad
--
With best wishes
Dmitry
On 09/05/2025 09:18, Jyothi Kumar Seerapu wrote:
Hi Dimitry, Thanks for providing the review comments.
On 5/6/2025 5:16 PM, Dmitry Baryshkov wrote:
On Tue, May 06, 2025 at 04:48:44PM +0530, Jyothi Kumar Seerapu wrote:
The I2C driver gets an interrupt upon transfer completion.
When handling
On 09/05/2025 04:58, Andy Yan wrote:
Hi Dmitry,
Thanks for you review.
在 2025-05-05 00:16:35，"Dmitry Baryshkov" 写道：
On Sat, May 03, 2025 at 04:42:04PM +0200, Heiko Stübner wrote:
Am Dienstag, 22. April 2025, 09:04:39 Mitteleuropäische Sommerzeit schrieb Andy
Yan:
From: Andy
On 09/05/2025 06:08, Jun Nie wrote:
Dmitry Baryshkov 于2025年5月8日周四 18:47写道：
On Tue, May 06, 2025 at 11:47:31PM +0800, Jun Nie wrote:
Some display controller support flexible CRTC and DMA, such as the display
controllers in snapdragon SoCs. CRTC can be implemented with several mixers
in
ion before 4 WB usage case is supported in future.
>
> Signed-off-by: Jun Nie
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
valid()? According to your description a better place would
be in drm_atomic_helper_check_planes().
> ret = mode_valid(state);
> if (ret)
> return ret;
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
ties in the nodes
> to define.
>
> Signed-off-by: Rob Herring (Arm)
> ---
> Documentation/devicetree/bindings/display/msm/hdmi.yaml | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Dmitry Baryshkov
I've verified, it applies on top of msm-next and produ
dss *mdss = platform_get_drvdata(pdev);
>
> - of_platform_depopulate(&pdev->dev);
> -
> msm_mdss_destroy(mdss);
Unfortunately this means that the child devices will still exist after
destroying the MDSS (IRQ domain, etc). So, it seems it can not land as
is.
> }
>
> --
> 2.45.2
>
--
With best wishes
Dmitry
On Wed, 7 May 2025 at 19:43, Rob Clark wrote:
>
> On Sat, May 3, 2025 at 12:17 AM Dmitry Baryshkov
> wrote:
> >
> > There are cases when we want to have separate DRM devices for GPU and
> > display pipelines.
> > One example is development, when it is benefici
On Wed, May 07, 2025 at 06:27:54PM +0530, Ayushi Makhija wrote:
> On 5/6/2025 5:58 PM, Dmitry Baryshkov wrote:
> > On Tue, May 06, 2025 at 05:42:50PM +0530, Ayushi Makhija wrote:
> >> Hi Dmitry,
> >>
> >> On 5/5/2025 3:32 PM, Dmitry Baryshkov wrote:
> >&
On 5/7/25 05:51, Kasireddy, Vivek wrote:
> Hi Dmitry,
>
>> Subject: Re: [PATCH] drm/virtio: Fix NULL pointer deref in
>> virtgpu_dma_buf_free_obj()
>>
>> On 5/2/25 02:24, Vivek Kasireddy wrote:
>>> There is a chance that obj->dma_buf would be NULL by
On Tue, 6 May 2025 at 17:36, Marijn Suijten
wrote:
>
> On 2025-05-06 15:53:48, Dmitry Baryshkov wrote:
> > From: Dmitry Baryshkov
> >
> > Follow the changes in the commit a2649952f66e ("drm/msm/dpu: remove
> > DPU_CTL_SPLIT_DISPLAY from CT
From: Dmitry Baryshkov
Follow the changes in the commit a2649952f66e ("drm/msm/dpu: remove
DPU_CTL_SPLIT_DISPLAY from CTL blocks on DPU >= 5.0") and remove
DPU_CTL_SPLIT_DISPLAY from the CTL blocks on the SAR2130P platform.
Single CTL is used for all interfaces used by a singl
On Mon, May 05, 2025 at 04:28:17PM -0700, Jessica Zhang wrote:
>
>
> On 4/24/2025 2:30 AM, Dmitry Baryshkov wrote:
> > Some time ago we started the process of converting HW blocks to use
> > revision-based checks instead of having feature bits (which are easy to
> >
On Tue, May 06, 2025 at 05:42:50PM +0530, Ayushi Makhija wrote:
> Hi Dmitry,
>
> On 5/5/2025 3:32 PM, Dmitry Baryshkov wrote:
> > On Mon, May 05, 2025 at 03:12:41PM +0530, Ayushi Makhija wrote:
> >> Add anx7625 DSI to DP bridge device nodes.
> >>
> >> Si
ext, thanks!
[1/1] drm/panel: simple: Update timings for AUO G101EVN010
commit: d5d283d45c85e774b64100137f34e7d55bfbe45e
Best regards,
--
With best wishes
Dmitry
ev *gi2c,
> struct i2c_msg msgs[], i
> dma_async_issue_pending(gi2c->rx_c);
> }
>
> - dma_async_issue_pending(gi2c->tx_c);
> -
> - time_left = wait_for_completion_timeout(&gi2c->done,
> XFER_TIMEOUT);
> - if (!time_left)
> - gi2c->err = -ETIMEDOUT;
> + if (!gi2c->is_tx_multi_desc_xfer) {
> + dma_async_issue_pending(gi2c->tx_c);
> + time_left = wait_for_completion_timeout(&gi2c->done,
> XFER_TIMEOUT);
> + if (!time_left) {
> + dev_err(gi2c->se.dev, "%s:I2C timeout\n",
> __func__);
> + gi2c->err = -ETIMEDOUT;
> + }
> + }
>
> if (gi2c->err) {
> ret = gi2c->err;
> goto err;
> }
>
> - geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf,
> rx_addr);
> + if (!gi2c->is_tx_multi_desc_xfer) {
> + geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr,
> rx_buf, rx_addr);
> + } else if (gi2c->tx_irq_cnt != tx_multi_xfer->irq_cnt) {
> + gi2c->tx_irq_cnt = tx_multi_xfer->irq_cnt;
> + geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral);
> + }
> }
>
> return num;
> @@ -663,7 +912,11 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c,
> struct i2c_msg msgs[], i
> dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret);
> dmaengine_terminate_sync(gi2c->rx_c);
> dmaengine_terminate_sync(gi2c->tx_c);
> - geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
> + if (gi2c->is_tx_multi_desc_xfer)
> + geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral);
> + else
> + geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf,
> rx_addr);
> +
> return ret;
> }
>
> --
> 2.17.1
>
--
With best wishes
Dmitry
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