Hey Jani,
On 8/17/23 15:05, Jani Nikula wrote:
On Thu, 17 Aug 2023, Dirk Lehmann wrote:
VESA Enhanced EDID Standard does not clearly describe how display
panel vendors should setup the Sync Signal Defintions (bit 4 & 3) in
the Detailed Timing Definition (relative offset 17, absolute of
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8146
Signed-off-by: Dirk Lehmann
---
drivers/gpu/drm/drm_edid.c | 74 --
include/drm/drm_edid.h | 12 +--
2 files changed, 73 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_ed
From: Jani Nikula
This reverts commit ca62297b2085b5b3168bd891ca24862242c635a1.
Commit ca62297b2085 ("drm/edid: Fix csync detailed mode parsing") fixed
EDID detailed mode sync parsing. Unfortunately, there are quite a few
displays out there that have bogus (zero) sync field that are broken by
th