/kernel/setup.c | 5 -
Acked-by: Dinh Nguyen
Hi Maxime,
On 5/4/23 12:04, Maxime Ripard wrote:
Hi Dinh,
On Thu, Apr 27, 2023 at 02:09:48PM -0500, Dinh Nguyen wrote:
Hi Maxime,
On 4/25/23 09:48, Maxime Ripard wrote:
Hi Dinh,
On Mon, Apr 24, 2023 at 01:32:28PM -0500, Dinh Nguyen wrote:
On 4/4/23 05:11, Maxime Ripard wrote:
The SoCFGPA
Hi Maxime,
On 4/25/23 09:48, Maxime Ripard wrote:
Hi Dinh,
On Mon, Apr 24, 2023 at 01:32:28PM -0500, Dinh Nguyen wrote:
On 4/4/23 05:11, Maxime Ripard wrote:
The SoCFGPA gate clock implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is
Hi Maxime,
On 4/4/23 05:11, Maxime Ripard wrote:
The SoCFGPA gate clock implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely ca
Hi Hean-Loong:
Please format your commit message like this:
Reviewed-by: Rob Herring
Signed-off-by: Ong, Hean Loong
---
V15:
v14:
The version history needs go after the ---
Dinh
On 6/7/19 9:30 AM, Hean-Loong, Ong wrote:
> From: "Ong, Hean Loong"
>
> Device tree binding for Intel FPGA Vi
On 08/14/2018 03:57 AM, Hean-Loong, Ong wrote:
> From: Ong, Hean Loong
>
> The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver
> patch
> here is allocating memory for information to be streamed from the ARM/Linux
> to the display port. Basically the driver just wraps th
On 08/14/2018 03:57 AM, Hean-Loong, Ong wrote:
> From: Ong Hean Loong
>
> Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II.
> The driver only supports the Intel Arria10 devkit and its variants.
Why only Arria10? That's not true is it? I remember running a version of
this
