On Sat, 2019-09-07 at 00:21 -0700, Dhinakaran Pandiyan wrote:
> Gen-12 has a new compression format, add a new modifier to indicate that.
>
> Cc: Ville Syrjälä
> Cc: Matt Roper
> Cc: Nanley G Chery
> Cc: Jason Ekstrand
Cc: dri-devel@lists.freedesktop.org
> Signed-off-by
On Wed, 2019-06-26 at 16:31 +0200, Daniel Vetter wrote:
> On Wed, Jun 26, 2019 at 04:43:28PM +0300, Ville Syrjälä wrote:
> > On Tue, Jun 25, 2019 at 04:40:45PM -0700, Dhinakaran Pandiyan wrote:
> > > Currently we restrict the number of encoders that can be linked to
>
track of the encoder IDs.
Cc: José Roberto de Souza
Cc: Ville Syrjälä
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan
---
include/drm/drm_connector.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_connector.h b/include/drm
On Thu, 2018-12-20 at 15:13 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-12-20 at 09:10 -0800, Rodrigo Vivi wrote:
> > On Thu, Dec 20, 2018 at 02:21:20PM +0100, Hans de Goede wrote:
> > > Call intel_psr_enable() and intel_edp_drrs_enable() on pipe
> > > updates
>
t enable_psr is handled
> and
> update the module parameter string to match the actual functionality.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: Ross Zwisler
> ---
> drivers/gpu/drm/i915/i915_drv.h| 1 -
> drivers/gpu/drm/i915/i915_params.c |
to do this on every encoder->update_pipe
> > callback.
> >
> > Changes in v2:
> > -Merge the patches adding the intel_psr_enable() and
> > intel_edp_drrs_enable()
> > calls into a single patch
> >
> > Reviewed-by: Maarten Lankhorst
> > Signed
On Thu, 2018-12-13 at 15:09 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-12-13 at 07:18 +0200, Ville Syrjälä wrote:
> > On Wed, Dec 12, 2018 at 04:32:02PM -0800, Dhinakaran Pandiyan
> > wrote:
> > > On Tue, 2018-11-20 at 18:13 +0200, Ville Syrjala wrote:
>
On Thu, 2018-12-13 at 07:18 +0200, Ville Syrjälä wrote:
> On Wed, Dec 12, 2018 at 04:32:02PM -0800, Dhinakaran Pandiyan wrote:
> > On Tue, 2018-11-20 at 18:13 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Fill out the AVI inf
On Tue, 2018-11-20 at 18:13 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Fill out the AVI infoframe quantization range bits using
> drm_hdmi_avi_infoframe_quant_range() for SDVO HDMI encoder as well.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_sdvo.c | 19 +
introduced here does make sense.
Reviewed-by: Dhinakaran Pandiyan
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_dp_helper.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_he
On Mon, 2018-12-10 at 23:29 +0200, Ville Syrjälä wrote:
> On Mon, Dec 10, 2018 at 01:07:49PM -0800, Dhinakaran Pandiyan wrote:
> > The Write_Status_Update_Request I2C transaction requires the MOT
> > bit to
> > be set, Change the logical AND to OR to fix what looks like a
WRITE requests")
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_dp_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 2d6c491a0542..d98805b517f0 100644
--- a/drivers/gpu/drm/drm_d
On Mon, 2018-12-10 at 18:39 +0200, Ville Syrjälä wrote:
> On Fri, Dec 07, 2018 at 12:45:25PM -0800, Dhinakaran Pandiyan wrote:
> > On Fri, 2018-09-28 at 21:03 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > We aren't supposed to
On Fri, 2018-12-07 at 16:57 -0800, Dhinakaran Pandiyan wrote:
> On Fri, 2018-09-28 at 21:04 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Decode the NAK reply fields to make it easier to parse the logs.
>
> A lot better than seeing the error code
essed,
Reviewed-by: Dhinakaran Pandiyan
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 65
> ++-
> include/drm/drm_dp_helper.h | 1 +
> 2 files changed, 65 insertions(+), 1 deletion(-)
>
> diff --g
{
> ret = -EREMOTEIO;
> goto out;
> }
> diff --git a/include/drm/drm_dp_helper.h
> b/include/drm/drm_dp_helper.h
> index 2a3843f248cf..2a0fd9d7066e 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/
g
> messages are all writes. Also check that the length of each
> message isn't too long.
Right, the syntax for i2c_remote_read allows only 8 bits for length.
Reviewed-by: Dhinakaran Pandiyan
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_dp_mst_topology
On Fri, 2018-12-07 at 12:45 -0800, Dhinakaran Pandiyan wrote:
> On Fri, 2018-09-28 at 21:03 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We aren't supposed to force a stop+start between every i2c msg
> > when performing multi message transfers. T
On Fri, 2018-09-28 at 21:03 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We aren't supposed to force a stop+start between every i2c msg
> when performing multi message transfers. This should eg. cause
> the DDC segment address to be reset back to 0 between writing
> the segment address a
CD_QUIRK_NO_PSR
>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Dhinakaran Pandiyan
> Fixes: 7c5c641a930e (drm/i915: Disable PSR in Apple panels)
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> include/drm/drm_dp_helper.h | 2 +-
> 1 file
SR2_IDLE_FRAME_MAX
>
> In the next patch the new macros will be used.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
&g
On Mon, 2018-12-03 at 12:14 -0800, Souza, Jose wrote:
> On Fri, 2018-11-30 at 15:35 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > > i915 yet don't support PSR in Apple panels, so lets keep it
> > > disa
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> According to eDP spec, sink can required specific selective update
> granularity that source must comply.
> Here caching the value if required and checking if source supports
> it.
>
> Cc: Rodrigo Vivi
> Cc
On Fri, 2018-11-30 at 15:35 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > i915 yet don't support PSR in Apple panels, so lets keep it
> > disabled
> > while we work on that.
> >
> > v2: Renamed DP_DPC
ng*
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> Source is required to comply to sink SU granularity when
> DP_PSR2_SU_GRANULARITY_REQUIRED is set in DP_PSR_CAPS,
> so adding the registers offsets.
>
> v2: Also adding DP_PSR2_SU_Y_GRANULARITY(Rodrigo)
>
> Cc
short pulse handling implemented, I think we are ready for
this.
Reviewed-by: Dhinakaran Pandiyan
>
> Cc: Dhinakaran Pandiyan
> Reviewed-by: Rodrigo Vivi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+)
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {'
> and this bit is only set for PSR1 move it to that block to make it
> more easy to read.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodr
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> For PSR2 there is no register to tell HW to keep main link enabled
Right, there is no bit in PSR2_CTL
Reviewed-by: Dhinakaran Pandiyan
> while PSR2 is active, so don't configure sink DPCD with a
> misleading
598c6cfe0690 (drm/i915/psr: Enable PSR1 on gen-9+ HW)
> Cc: Ville Syrjälä
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/drm_dp_helper.c | 2 ++
> drivers/gpu/drm/i915/intel_psr.c | 6 ++
> include/drm/drm_dp_he
ot;Apple" with specific model name?
> > > disabled
> > > while we work on that.
> > >
> > > Fixes: 598c6cfe0690 (drm/i915/psr: Enable PSR1 on gen-9+ HW)
Bugzilla please. Also Cc the bug reporter?
> > > Cc: Rodrigo Vivi
> > > Cc: Dhin
TION is for PSR only and
> > DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Rodrigo Vivi
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/intel_psr.c | 2 +-
> > 1 file changed,
cessary so this FIXME is not valid anymore.
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Rodrigo Vivi
> > Signed-off-by: José Roberto de Souza
>
> Reviewed-by: Rodrigo Vivi
Acked-by: Dhinakaran Pandiyan
>
> > ---
> > drivers/gpu/drm/i915/intel_ps
are shorter
> - they follow the exact name we have on spec
+1 for the above reason.
>
> >
> > Also taking the oportunity to improve those macros.
> >
> > Cc: Rodrigo Vivi
> > Cc: Dhinakaran Pandiyan
> > Signed-off-by: José Roberto de Souza
> &
On Tue, 2018-11-06 at 22:21 +0200, Ville Syrjälä wrote:
> On Tue, Nov 06, 2018 at 11:54:45AM -0800, Dhinakaran Pandiyan wrote:
> > On Tue, 2018-11-06 at 16:13 +0200, Ville Syrjälä wrote:
> > > On Mon, Nov 05, 2018 at 06:44:34PM -0800, Dhinakaran Pandiyan
> > > wrote:
>
On Tue, 2018-11-06 at 16:13 +0200, Ville Syrjälä wrote:
> On Mon, Nov 05, 2018 at 06:44:34PM -0800, Dhinakaran Pandiyan wrote:
> > Allows drivers to pass a larger modifier array, thereby avoiding
> > declarations of static modifier arrays that are only slight
> > differe
Allows drivers to pass a larger modifier array, thereby avoiding
declarations of static modifier arrays that are only slight different
for each plane.
Cc: dri-devel@lists.freedesktop.org
Cc: Ville Syrjälä
Suggested-by: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm
rm
> checks for different formats. The new code requires zero maintenance.
>
> v2: Nuke the modifier checks as well since the core does that too now
> v3: Call drm_any_plane_has_format() from the driver code
> v4: Rebase
>
> Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pa
On Fri, 2018-03-09 at 17:14 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace the messy framebuffer format/modifier validation code
> with a single call to drm_any_plane_has_format(). The code was
> extremely annoying to maintain as you had to have a lot of platform
> checks for diffe
the
> modifier yet, instead export the function and let drivers
> call it themselves
>
> Cc: Eric Anholt
> Signed-off-by: Ville Syrjälä
I ended up writing a similar patch for i915. Having this in the core
seems better and patch still applies cleanly.
Reviewed-by: Dhinaka
i915 will make use of this to fail early during framebuffer creation.
Suggested-by: Ville Syrjälä
Cc: dri-devel@lists.freedesktop.org
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_plane.c | 1 +
include/drm/drm_plane.h | 11 +++
2 files changed, 12
gt; Cc: Jani Nikula
> > Cc: Cooper Chiou
> > Cc: Matt Atwood
> > Cc: Maarten Lankhorst
> > Cc: Dhinakaran Pandiyan
> > Cc: Clint Taylor
> > Signed-off-by: Lee, Shawn C
>
> No access to the panel or its details, so instead of review,
>
> A
ement some changes for branch/sink device
> that really need additional WA.
>
> Cc: Jani Nikula
> Cc: Cooper Chiou
> Cc: Matt Atwood
> Cc: Maarten Lankhorst
> Cc: Dhinakaran Pandiyan
> Cc: Clint Taylor
> Signed-off-by: Lee, Shawn C
> ---
> drivers/gpu/drm/drm
On Thu, 2018-08-30 at 13:57 +0100, Lisovskiy, Stanislav wrote:
> On Wed, 2018-08-29 at 12:16 -0700, Dhinakaran Pandiyan wrote:
> >
> > On Wed, 2018-08-29 at 21:10 +0300, Ville Syrjälä wrote:
> > > On Wed, Aug 29, 2018 at 02:28:47PM +0300, Stanisl
On Wed, 2018-08-29 at 21:10 +0300, Ville Syrjälä wrote:
> On Wed, Aug 29, 2018 at 02:28:47PM +0300, Stanislav Lisovskiy wrote:
> > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> > specification.
> >
> > v2: Edited commit message, removed redundant whitespaces.
> >
> > v3: F
On Tue, 2018-07-17 at 15:34 -0700, Dhinakaran Pandiyan wrote:
> On Tue, 2018-07-17 at 14:49 -0700, matthew.s.atw...@intel.com wrote:
> >
> > From: Matt Atwood
> >
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT
On Tue, 2018-07-17 at 14:49 -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values wil
On Mon, 2018-06-25 at 14:10 +0300, Ville Syrjälä wrote:
> On Thu, Jun 21, 2018 at 06:26:04PM -0700, Dhinakaran Pandiyan wrote:
> >
> > On Fri, 2018-06-15 at 19:49 +0300, Ville Syrjala wrote:
> > >
> > > From: Ville Syrjälä
> > >
> > >
On Fri, 2018-06-15 at 19:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Don't advertize non-exisiting crtcs in the encoder possible_crtcs
> bitmask.
>
How do we end up advertising non-existing CRTCs? encoder->crtc_mask
seems to be populated in the encoder init functions based on possib
On Fri, 2018-06-15 at 21:43 +0300, Ville Syrjälä wrote:
> On Fri, Jun 15, 2018 at 11:33:01AM -0700, Dhinakaran Pandiyan wrote:
> >
> > On Fri, 2018-06-15 at 19:49 +0300, Ville Syrjala wrote:
> > >
> > > From: Ville Syrjälä
> > >
> > > Each f
On Fri, 2018-06-15 at 19:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Each fake MST encoder is tied to a specific pipe. Fix the encoder's
> crtc_mask to reflect that fact.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> 1 file changed, 1 inser
1.4a.
Fixes: 6608804b3d7f ("drm/dp: Add drm_dp_psr_setup_time()")
Cc: sta...@vger.kernel.org
Cc: Ville Syrjälä
Cc: Jose Roberto de Souza
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_dp_helper.c | 1 +
1 file changed, 1 insertion(+)
di
On Fri, 2018-05-11 at 18:03 +, Souza, Jose wrote:
> On Thu, 2018-05-10 at 17:54 -0700, Dhinakaran Pandiyan wrote:
> >
> > Entry corresponding to 220 us setup time was missing. I am not
> > aware
> > of
> > any specific bug this fixes, but this could potential
On Wed, 2018-04-11 at 18:54 -0400, Lyude Paul wrote:
> While having the modeset_retry_work in intel_connector makes sense with
> SST, this paradigm doesn't make a whole ton of sense when it comes to
> MST since we have to deal with multiple connectors. In most cases, it's
> more useful to just u
"atomic driver check for %p failed: %d\n",
> + state, ret);
> return ret;
> + }
>
nit: Would have slightly looked better if the 'ret' check was moved
inside the branch for funcs->atomic_check.
Reviewed-by: Dhinakara
;
> Since DPMS is what lets us actually bring the hub up into a state where
> sideband communications become functional again, we just need to make
> sure to enable DPMS on the display before attempting to perform sideband
> communications.
>
Matches my understanding of the p
, and only send
> DPMS on when we're enabling the first sink - dhnkrn
>
> Signed-off-by: Lyude Paul
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjälä
> Cc: Laura Abbott
> Cc: sta...@vger.kernel.org
> Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd
hub is ready
> > to accept sideband messages.
> >
> > Signed-off-by: Lyude Paul
> > Cc: Dhinakaran Pandiyan
> > Cc: Ville Syrjälä
> > Cc: Laura Abbott
> > Cc: sta...@vger.kernel.org
> > Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpc
No code changes, fixes doc build warnings and polish some doc text.
Reported-by: Daniel Vetter
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a
eturn from drm_crtc_vblank_count() explicitly to add clarity.
__drm_crtcs_state.last_vblank_count however only ever stores the value from
drm_crtc_vblank_count() and can be upgraded to u64.
Cc: Keith Packard
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_plane.c | 2 +-
i
means the registers should be read
before disabling vblank interrupts.
v2: Don't check vblank->enabled outside it's lock (Chris)
Cc: Chris Wilson
Cc: Daniel Vetter
Cc: Michel Dänzer
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Acked-by: Daniel Vetter
---
drivers/gp
u32 either fixes a potential problem or serves to add clarity in
case the implicit typecasting was already correct.
Cc: Keith Packard
Cc: Thierry Reding
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/tegra/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
xpected to be called from the driver
_enable_vblank() vfunc.
v2: drm_crtc_vblank_restore should take crtc as arg. (Chris)
Add docs and sprinkle some asserts.
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Michel Dänzer
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Acked-by:
Core returns a u64 vblank count and intel_crtc_get_vblank_counter()
expects a 32-bit value. Make the typecast explicit to add clarity.
Cc: Keith Packard
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1
the counter running.
This change is not applicable to CHV, as enabling interrupts does not
prevent the hardware from activating PSR.
v2: Added comments(Rodrigo) and rewrote commit message.
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Ack
u32 either fixes a potential problem or serves to add clarity in case
the typecasting was implicitly done.
Cc: Keith Packard
Cc: Alex Deucher
Cc: Harry Wentland
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/a
u32 either fixes a potential problem or serves to add clarity in case
the implicit typecasting was already correct.
Cc: Keith Packard
Cc: Alex Deucher
Cc: Harry Wentland
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/radeon/radeon_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
en vblank count to 64-bits [v3]")
Cc: Keith Packard
Cc: Michel Dänzer
Cc: Daniel Vetter
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
Acked-by: Daniel Vetter
---
drivers/gpu/drm/drm_vblank.c | 8
include/drm/drm_vblank.h | 2 +-
2 files changed, 5 insertions(+), 5
570e86963a51 ("drm: Widen vblank count to 64-bits [v3]") changed the
return type for drm_crtc_vblank_count() to u64, store all the bits
without truncating. There is no need to type cast this value down to
32-bits.
Cc: Keith Packard
Cc: Paulo Zanoni
Cc: Rodrigo Vivi
Signed-off-by:
Drivers can use this in their retry loops too.
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_dp_helper.c | 12 +---
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm
bit
value and gets queued like that. However, the code that checks if the
requested sequence has passed compares this against the 64-bit vblank
count.
Cc: Keith Packard
Cc: Michel Dänzer
Cc: Daniel Vetter
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 2 +-
1 file changed
hereby stalling the counter.
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_irq.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c6548e2c..db3466ec6faa 100644
--- a/drive
disabling vblank interrupts.
v2: Don't check vblank->enabled outside it's lock (Chris)
Cc: Chris Wilson
Cc: Daniel Vetter
Cc: Michel Dänzer
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
ver
_enable_vblank() vfunc.
v2: drm_crtc_vblank_restore should take crtc as arg. (Chris)
Add docs and sprinkle some asserts.
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Michel Dänzer
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 59
incl
ter
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 4 ++--
include/drm/drm_vblank.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 768a8e44d99b..f2bf1f5dbaa5 100644
--- a/drivers/gpu/
ssage
fixes the issue. I am not entirely sure if this is specific to my setup.
However, as the power state is toggled conditionally on LINK_ADDRESS
timeouts, this should not affect the working cases.
Cc: Lyude
Cc: Dave Airlie
Cc: Jani Nikula
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gp
get_if_enabled.
Modify power_domain_verify_state to check power well use count and
enabled status atomically.
Rewrite of intel_power_well_{get,put}
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_drv.h | 18
DPCD read for the eDP is complete by the time intel_psr_init() is
called, which means we can avoid initializing PSR structures and state
if there is no sink support.
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_debugfs.c | 7
Convert the power_domains->domain_use_count array that tracks per-domain
use count to atomic_t type. This is needed to be able to read/write the use
counts outside of the power domain mutex.
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
---
driv
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_irq.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3517c6548e2c..88b4ceac55d0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915
that's for the future.
Also, disable vblanks after reading the HW counter in the case where
_crtc_vblank_off() is disabling vblanks.
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 23 +--
1
This flag has become redundant since
commit 4d90f2d507ab ("drm/i915: Start tracking PSR state in crtc state")
It is set at the same place as psr.enabled, which is also exposed via
debugfs.
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gp
.
Dhinakaran Pandiyan (8):
drm/i915/psr: Kill psr.source_ok flag.
drm/i915/psr: CAN_PSR() macro to check for PSR source and sink
support.
drm/i915/psr: Avoid initializing PSR if there is no sink support.
drm/vblank: Do not update vblank counts if vblanks are already
disabled.
drm/vblank
blank interrupts because this function is expected to be called from
the driver _enable_vblank() vfunc.
Cc: Daniel Vetter
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 33 +
include/drm/drm_vblank.h | 1
ivi
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 19 ---
2 files changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 30f791f89
blank interrupts because this function is expected to be called from
the driver _enable_vblank() vfunc.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 30 ++
include/drm/drm_vblank.h | 1 +
2 files changed, 31 insertions(+)
diff --git a/driver
Disable DC states before enabling vblank interrupts and conversely
enable DC states after disabling. Since the frame counter may have got
reset between disabling and enabling, use drm_crtc_vblank_restore() to
compute the missed vblanks.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm
that's for the future.
Also, disable vblanks after reading the HW counter in the case where
_crtc_vblank_off() is disabling vblanks.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 23 +--
1 file changed, 9 insertions(+), 14 deletions(-)
diff --
Convert the power_domains->domain_use_count array that tracks per-domain
use count to atomic_t type. This is needed to be able to read/write the use
counts outside of the power domain mutex.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/
already enabled, introduce a new power domain. Since this
power domain reference needs to be acquired and released in atomic context,
the corresponding _get() and _put() methods skip the power_domain mutex.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_drv.h | 5
fall back
approach is sane and if it should be implemented in the core.
Cc: Daniel Vetter
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_vblank.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drive
: Dhinakaran Pandiyan
---
include/drm/drm_dp_helper.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 9049ef133d69..aea10f85dd4c 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -617,8 +617,8
within 80 cols.
Cc: Jani Nikula
Reviewed-by: Jani Nikula
Signed-off-by: Dhinakaran Pandiyan
---
include/drm/drm_dp_helper.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 2c412a15cfa1..11c39f15f1b3 100644
--- a/i
Link status is available in the ESI field on devices with DPCD r1.2 or
higher. DP spec also says "An MST upstream device shall use this field
instead of the Link/Sink Device Status field registers, starting from DPCD
Address 00200h."
Cc: Jani Nikula
Signed-off-by: Dhinakara
. Secondly, since the request-reply protocol waits for an
ACK, we can be sure that a downstream sink has enough time to respond to a
power up/down request.
v2: Fix memory leak (Lyude)
Cc: Lyude
Cc: Ville Syrjälä
Cc: Harry Wentland
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm
-2-2-1 --off
$ xrandr --display :0 --output DP-2-2-8 --auto #Black screen
$ xrandr --display :0 --output DP-2-2-1 --auto
Cc: Ville Syrjälä
Cc: Lyude
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_ddi.c| 6 --
drivers/gpu/drm/i915/intel_dp_mst.c | 8
2 files
. Secondly, since the request-reply protocol waits for an
ACK, we can be sure that a downstream sink has enough time to respond to a
power up/down request.
Cc: Lyude
Cc: Ville Syrjälä
Cc: Harry Wentland
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_dp_mst_topology.c | 73
MST monitor configuration that
doesn't wake up from D3 state.
v2: Use spaces instead of tabs (Jani)
Signed-off-by: Dhinakaran Pandiyan
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index b17476a
MST monitor configuration that
doesn't wake up from D3 state.
Signed-off-by: Dhinakaran Pandiyan
---
include/drm/drm_dp_helper.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index b17476a..d77e0f5 100
Resending for CI.
Pandiyan, Dhinakaran (4):
drm: Add driver-private objects to atomic state
drm/dp: Introduce MST topology state to track available link bandwidth
drm/dp: Add DP MST helpers to atomically find and release vcpi slots
drm/dp: Track MST link bandwidth
drivers/gpu/drm/drm_ato
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