On 8/21/2023 9:22 AM, Jani Nikula wrote:
On Mon, 21 Aug 2023, "Ricardo B. Marliere" wrote:
This patch fixes the following sphinx warnings in the htmldocs make target:
Documentation/gpu/i915:546: ./drivers/gpu/drm/i915/gt/uc/intel_huc.c:29: ERROR:
Unexpected indentation.
Documentation/gpu/i
thread to do the reset asynchronously.
v2: Flush the worker on suspend and shutdown. Add rate limiting to
prevent spam from a totally dead system (review feedback from Daniele).
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c
to me. Maybe trigger a re-run to be safe?
Once it's confirmed that the failures are unrelated, this is:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 18 +-
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 5 +++--
2 files change
On 7/26/2023 7:54 PM, David Reaver wrote:
Fix the following make htmldocs errors/warnings:
./drivers/gpu/drm/i915/gt/uc/intel_huc.c:29: ERROR: Unexpected indentation.
./drivers/gpu/drm/i915/gt/uc/intel_huc.c:30: WARNING: Block quote ends without
a blank line; unexpected unindent.
./drivers/g
On 6/1/2023 8:59 AM, Alan Previn wrote:
In the case of failed suspend flow or cases where the kernel does not go
into full suspend but goes from suspend_prepare back to resume_complete,
we get called for a pm_complete but without runtime_pm guaranteed.
Thus, ensure we take the runtime_pm when
Rebase to latest drm-tip.
v2: - Based on internal testing, increase the timeout for gsc-proxy
specific case to 8 seconds.
Signed-off-by: Alan Previn
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 14 +
drivers/gpu/drm/
On 6/29/2023 6:44 PM, Alan Previn wrote:
After recent discussions with Mesa folks, it was requested
that we optimize i915's GET_PARAM for the PXP_STATUS without
changing the UAPI spec.
Add these additional optimizations:
- If any PXP initializatoin flow failed, then ensure that
we c
On 7/20/2023 2:40 PM, Alan Previn wrote:
On MTL, if the GSC Proxy init flows haven't completed, submissions to the
GSC engine will fail. Those init flows are dependent on the mei's
gsc_proxy component that is loaded in parallel with i915 and a
worker that could potentially start after i915 dri
On 7/12/2023 4:12 PM, Alan Previn wrote:
On MTL, if the GSC Proxy init flows haven't completed, submissions to the
GSC engine will fail. Those init flows are dependent on the mei's
gsc_proxy component that is loaded in parallel with i915 and a
worker that could potentially start after i915 dri
On 7/12/2023 3:03 AM, Andrzej Hajda wrote:
On 11.07.2023 22:31, Daniele Ceraolo Spurio wrote:
Due to a change in the auth flow on MTL, GuC 70.7.0 and newer will only
be able to authenticate HuC 8.5.1 and newer. The plan is to update the 2
binaries sinchronously in linux-firmware so that the f
@@ -134,6 +193,8 @@ static int __run_selftests(const char *name,
{
int err = 0;
+ __wait_on_all_system_dependencies(data);
Why does this need to be top level selftests and not just a wait for
intel_gsc_uc_fw_proxy_init_done in the tests where it is relevant, via
some helper or so
On 6/16/2023 8:54 AM, Ceraolo Spurio, Daniele wrote:
On 6/15/2023 2:19 PM, Alan Previn wrote:
intel_gsc_uc_fw_proxy_init_done is used by a few code paths
and usages. However, certain paths need a wakeref while others
can't take a wakeref such as from the runtime_pm_resume callstack.
On 6/15/2023 2:19 PM, Alan Previn wrote:
intel_gsc_uc_fw_proxy_init_done is used by a few code paths
and usages. However, certain paths need a wakeref while others
can't take a wakeref such as from the runtime_pm_resume callstack.
Add a param into this helper to allow callers to direct whethe
On 6/14/2023 1:41 PM, Harshit Mogalapalli wrote:
Smatch warns:
drivers/gpu/drm/i915/gt/uc/intel_huc.c:388
intel_huc_init() warn: missing error code 'err'
When the allocation of VMAs fail: The value of err is zero at this
point and it is passed to PTR_ERR and also finally r
/)
which is why i am adding the wakeref inside the callee, not the
caller.
v2: - add a helper, 'gsc_uc_get_fw_status' for both callers
(Daniele Ceraolo)
Fixes: 99afb7cc8c44 ("drm/i915/pxp: Add ARB session creation and cleanup")
Signed-off-by: Alan Previn
Reviewed-by: Da
On 6/8/2023 11:04 AM, Alan Previn wrote:
Ensure intel_gsc_uc_fw_init_done and intel_gsc_uc_fw_proxy_init
takes a wakeref before reading GSC Shim registers.
NOTE: another patch in review also adds a call from selftest to
this same function. (https://patchwork.freedesktop.org/series/117713/)
wh
On 6/5/2023 1:54 PM, john.c.harri...@intel.com wrote:
From: John Harrison
If GuC hits an internal error (and survives long enough to report it
to the KMD), it is basically toast and will stop until a GT reset and
subsequent GuC reload is performed. Previously, the KMD just printed
an error m
On 6/5/2023 4:46 PM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-05-31 at 17:25 -0700, Ceraolo Spurio, Daniele wrote:
On 5/26/2023 3:57 PM, Teres Alexis, Alan Previn wrote:
On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
Add a new debugfs to dump information about the
:
Reviewed-by: Alan Previn
On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
Add FW definition and the matching override modparam.
The GSC FW has both a release version, based on platform and a rolling
counter, and a compatibility version, which is the one tracking
interface
On 5/26/2023 3:57 PM, Teres Alexis, Alan Previn wrote:
On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
Add a new debugfs to dump information about the GSC. This includes:
alan:snip
Actually everything looks good except for a couple of questions + asks - hope
we can close
On 5/30/2023 5:33 PM, Teres Alexis, Alan Previn wrote:
On Fri, 2023-05-26 at 17:52 -0700, Ceraolo Spurio, Daniele wrote:
The full authentication via the GSC requires an heci packet submission
to the GSC FW via the GSC CS. The GSC has new PXP command for this
(literally called NEW_HUC_AUTH
On 5/30/2023 5:20 PM, John Harrison wrote:
On 5/30/2023 17:11, Ceraolo Spurio, Daniele wrote:
On 5/30/2023 4:51 PM, John Harrison wrote:
On 5/26/2023 17:52, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC
On 5/30/2023 5:01 PM, John Harrison wrote:
On 5/30/2023 08:29, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with
On 5/30/2023 4:51 PM, John Harrison wrote:
On 5/26/2023 17:52, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that
On 5/30/2023 4:30 PM, John Harrison wrote:
On 5/26/2023 17:52, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication contain the
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
index d55a66202576..8bce2b8aed84 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
alan:snip
+struct
On 5/24/2023 10:14 PM, Teres Alexis, Alan Previn wrote:
On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
alan: snip
+int intel_gsc_fw_get_binary_info(struct intel_uc_fw *gsc_fw, const void *data,
size_t size)
+{
alan:snip
+ /*
+* The GSC binary starts
On 5/22/2023 5:13 PM, Teres Alexis, Alan Previn wrote:
On Fri, 2023-05-05 at 09:04 -0700, Ceraolo Spurio, Daniele wrote:
A few fixes/updates are required around the GSC memory allocation and it
is easier to do them all at the same time. The changes are as follows:
alan:snip
@@ -109,38
On 5/19/2023 11:45 AM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with
On 5/19/2023 11:03 AM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that
On 5/17/2023 2:04 PM, John Harrison wrote:
On 5/2/2023 08:27, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication have contain the
have contain?
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the ima
On 5/17/2023 1:59 PM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Now that each FW has its own reserved area, we can keep them always
pinned and skip the pin/unpin dance on reset. This will make things
easier for the 2-step HuC authentication, which requires the FW
flag to track table validation errors (review
feedback/discussion with Daniele).
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 3 +
drivers/gpu/drm/i915/gt/uc/intel_uc.h| 1 +
drivers/gpu/drm/i915/
On 4/28/2023 5:32 PM, John Harrison wrote:
On 4/28/2023 17:30, John Harrison wrote:
On 4/28/2023 17:26, Ceraolo Spurio, Daniele wrote:
On 4/28/2023 5:16 PM, John Harrison wrote:
On 4/28/2023 17:04, Ceraolo Spurio, Daniele wrote:
On 4/20/2023 6:15 PM, john.c.harri...@intel.com wrote:
From
On 4/28/2023 5:16 PM, John Harrison wrote:
On 4/28/2023 17:04, Ceraolo Spurio, Daniele wrote:
On 4/20/2023 6:15 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The validation of the firmware table was being done inside the code
for scanning the table for the next available
TED gt_err
+#else
+#define UNEXPECTED gt_notice
I tried to find an alternative word that had the same number of
characters as "gt_notice" so that we could avoid the indent in the diff,
but nothing came to mind, so:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+#endif
+
static in
or,
+ fw_blobs[j].blob.patch, fw_blobs[j].blob.path,
+ intel_platform_name(fw_blobs[i].p),
fw_blobs[i].rev,
nit: we could avoid printing the platform twice because you're
explicitly checking that it is the same earlier on.
On 4/20/2023 6:15 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The validation of the firmware table was being done inside the code
for scanning the table for the next available firmware blob. Which is
unnecessary. So pull it out into a separate function that is only
called once p
user if they are
missing out on that new fix.
v2: Use correct patch version number and drop redunant debug print
(review by Daniele / CI results).
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 30
On 4/27/2023 10:25 PM, Saarinen, Jani wrote:
Hi,
-Original Message-
From: Intel-gfx On Behalf Of Ye, Tony
Sent: perjantai 28. huhtikuuta 2023 6.11
To: Ceraolo Spurio, Daniele ; intel-
g...@lists.freedesktop.org
Cc: Teres Alexis, Alan Previn ; dri-
de...@lists.freedesktop.org; Zhang
On 4/26/2023 9:48 AM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-04-26 at 13:52 +0200, Daniel Vetter wrote:
On Tue, Apr 25, 2023 at 04:41:54PM +0300, Joonas Lahtinen wrote:
(+ Faith and Daniel as they have been involved in previous discussions)
Quoting Jordan Justen (2023-04-24 20:13:00)
rything
else such as input/output size verification or handling the
responses from security firmware (for example, requiring a retry).
Signed-off-by: Alan Previn
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 102 +++
On 4/20/2023 3:04 PM, Ceraolo Spurio, Daniele wrote:
On 4/18/2023 11:57 PM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
From: Alexander Usyskin
Add GSC proxy driver. It to allows messaging between GSC component
on Intel on board
On 4/17/2023 10:56 AM, Teres Alexis, Alan Previn wrote:
On Mon, 2023-04-10 at 09:10 -0700, Ceraolo Spurio, Daniele wrote:
alan:snip
+int
+intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
+struct intel_context *ce
On 4/18/2023 11:57 PM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
From: Alexander Usyskin
Add GSC proxy driver. It to allows messaging between GSC component
on Intel on board graphics card and CSE device.
alan:nit: isn't &
On 4/20/2023 11:49 AM, Teres Alexis, Alan Previn wrote:
On Wed, 2023-03-29 at 09:56 -0700, Ceraolo Spurio, Daniele wrote:
The GSC notifies us of a proxy request via the HECI2 interrupt. The
alan:snip
@@ -256,6 +262,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
u32 irqs
On 4/19/2023 10:12 AM, John Harrison wrote:
On 4/19/2023 10:02, John Harrison wrote:
On 4/18/2023 16:24, Ceraolo Spurio, Daniele wrote:
Typo doplicate in patch title
On 4/14/2023 5:57 PM, john.c.harri...@intel.com wrote:
From: John Harrison
It was noticed that duplicte entries in the
Typo doplicate in patch title
On 4/14/2023 5:57 PM, john.c.harri...@intel.com wrote:
From: John Harrison
It was noticed that duplicte entries in the firmware table could cause
typo duplicte
an infinite loop in the firmware loading code if that entry failed to
load. Duplicate entries are a
nit_early(struct intel_uc_fw *uc_fw,
{
struct drm_i915_private *i915 = uc_fw_to_gt(uc_fw, type)->i915;
+ validate_fw_table(i915);
Personal preference: IMO since we're calling intel_uc_fw_init_early per
FW type it would've been cleaner to restrict validate_fw_table() to a
sin
On 4/14/2023 5:57 PM, john.c.harri...@intel.com wrote:
From: John Harrison
When reduced version firmware files were added (matching major
component being the only strict requirement), the minor version was
still tracked and a notification reported if it was older. However,
the patch version
On 4/14/2023 5:57 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Explain another potential firmware failure mode and early exit the
long wait if hit.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/abi
-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index
On 4/17/2023 11:21 AM, Teres Alexis, Alan Previn wrote:
On Mon, 2023-04-10 at 10:14 -0700, Ceraolo Spurio, Daniele wrote:
alan:snip
@@ -354,8 +368,14 @@ int intel_pxp_start(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return -ENODEV;
- if (wait_for
On 4/14/2023 9:25 AM, Andi Shyti wrote:
MTL features a dedicated media engine that operates on its
independent GT, requiring activation of its specific interrupt
set.
Enable the necessary interrupts in a single action when the media
engine is present, bypassing the need to iterate through all
On 4/13/2023 8:52 AM, Matt Roper wrote:
On Thu, Apr 13, 2023 at 03:56:21PM +0200, Andi Shyti wrote:
Hi Tvrtko,
(I forgot to CC Daniele)
On Thu, Apr 13, 2023 at 11:41:28AM +0100, Tvrtko Ursulin wrote:
On 13/04/2023 10:20, Andi Shyti wrote:
From: Paulo Zanoni
In multitile systems IRQ need
ng as you get an ack from the
userspace drivers for this interface behavior:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+ */
+#define I915_PARAM_PXP_STATUS 58
+
/* Must be kept compact -- no holes and well documented */
/**
@@ -2096,6 +2110,14 @@ struct drm_i915_gem_context
On 4/6/2023 10:44 AM, Alan Previn wrote:
Add MTL's function for ARB session creation using PXP firmware
version 4.3 ABI structure format.
Also add MTL's function for ARB session invalidation but this
reuses PXP firmware version 4.2 ABI structure format.
For both cases, in the back-end gsccs
xec_res->host_session_handle));
Thinking back at this, maybe a possible solution to avoid randomly
generated clashing values is to check if any of the existing exec_res
already uses the generated value. Not a blocker because we only have 1
exec_res for now, so no chance of clashing.
Wi
On 4/6/2023 10:44 AM, Alan Previn wrote:
Add helper functions into a new file for heci-packet-submission.
The helpers will handle generating the MTL GSC-CS Memory-Header
and submission of the Heci-Cmd-Packet instructions to the engine.
NOTE1: These common functions for heci-packet-submission
s?
Reported-by: ...
Tested-by: ...
Can be fixed while merging.
Fixes: b762787bf767 ("drm/i915/pxp: Use drm_dbg if arb session failed due to fw
version")
Signed-off-by: Alan Previn
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
.../i915/pxp/intel_pxp_cmd_interface_cmn.h|
/8137
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 50 +--
1 file changed, 47 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
b/drivers/gpu/drm/i915/gt/uc
On 3/22/2023 12:44 PM, John Harrison wrote:
On 3/20/2023 14:10, Daniele Ceraolo Spurio wrote:
Commit 3db9d590557d ("drm/i915/gt: Reset twice") modified the code to
always hit the GDRST register twice when doing a reset, with the
reported aim to fix invalid post-reset engine state on some plat
On 3/22/2023 12:44 PM, John Harrison wrote:
On 3/20/2023 14:10, Daniele Ceraolo Spurio wrote:
The WA states that we need to alert the GSC FW before doing a GSC engine
reset and then wait for 200ms. The GuC owns engine reset, so on the i915
side we only need to apply this for full GT reset.
G
On 3/10/2023 5:01 PM, John Harrison wrote:
On 3/3/2023 11:20, Ceraolo Spurio, Daniele wrote:
On 2/17/2023 3:47 PM, john.c.harri...@intel.com wrote:
From: John Harrison
A failure to load the GuC is occasionally observed where the GuC log
actually showed that the GuC had loaded just fine
me.
v2: Add another wrapper to keep the flow balanced (Daniele)
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 97 ++-
.../gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 +-
drivers/gpu/drm/i
the helpers and wrap the enable as well as the cancel
(review feedback from Daniele).
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 38 +++
1 file changed, 23 insertions(+), 15 deletions
On 2/27/2023 6:21 PM, Alan Previn wrote:
Enable PXP with MTL-GSC-CS: add the has_pxp into device info
and increase the debugfs teardown timeouts to align with
new GSC-CS + firmware specs.
Signed-off-by: Alan Previn
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915
preference, so with or without the
change:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+ }
+ } else {
ret = intel_pxp_tee_component_init(pxp);
+ }
if (ret)
goto out_context;
@@ -239,15 +245,20 @@ int intel_pxp_ini
On 2/27/2023 6:21 PM, Alan Previn wrote:
Despite KCR subsystem being in the media-tile (close to the
GSC-CS), the IRQ controls for it are on GT-0 with other global
IRQ controls. Thus, add a helper for KCR hw interrupt
enable/disable functions to get the correct gt structure (for
uncore) for MT
On 2/27/2023 6:21 PM, Alan Previn wrote:
Add MTL's function for ARB session creation using PXP firmware
version 4.3 ABI structure format.
Also add MTL's function for ARB session invalidation but this
reuses PXP firmware version 4.2 ABI structure format.
Before checking the return status, loo
On 2/27/2023 6:21 PM, Alan Previn wrote:
Add GSC engine based method for sending PXP firmware packets
to the GSC firmware for MTL (and future) products.
Use the newly added helpers to populate the GSC-CS memory
header and send the message packet to the FW by dispatching
the GSC_HECI_CMD_PKT i
On 3/2/2023 1:50 PM, Zhanjun Dong wrote:
Add err code check for enable_communication on resume path. When resume failed,
we can no longer use the GPU, marking the GPU as wedged.
This is slightly incorrect. If we fail to enable communication, the
consequence is that we can't use the GuC. Th
On 2/3/2023 9:48 PM, Alan Previn wrote:
MESA driver is creating protected context on every driver handle
creation to query caps bits for app. So when running CI tests,
they are observing hundreds of drm_errors when enabling PXP
in .config but using SOC fusing or BIOS configuration that cannot
On 2/17/2023 3:47 PM, john.c.harri...@intel.com wrote:
From: John Harrison
A failure to load the GuC is occasionally observed where the GuC log
actually showed that the GuC had loaded just fine. The implication
being that the load just took ever so slightly longer than the 200ms
timeout. Giv
he switches below, we can end up returning false from the
wait but leaving success to true. I understand that this is used more as
a "not failed" flag rather than a success one, so it is functionally
correct, but maybe rename it? not a blocker.
Apart from the nits, the patch LGTM:
have both timeouts at 3 seconds. If the FLR fails the HW is
toast anyway, so waiting a few seconds more to detect it on driver
unload is not going to have additional consequences that we wouldn't
already have.
With the bit in the wait above fixed:
Reviewed-by: Daniele Ceraolo Spurio
On 2/23/2023 2:04 PM, Alan Previn wrote:
The Driver-FLR flow may inadvertently exit early before the full
completion of the re-init of the internal HW state if we only poll
GU_DEBUG Bit31 (polling for it to toggle from 0 -> 1). Instead
we need a two-step completion wait-for-completion flow tha
be
guaranteed that they're always there as a pair.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_ring.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c
b/drivers/gpu/drm/i915/gt/intel_ring.c
safest to just not use it.
Signed-off-by: John Harrison
Fixes: c58b735fc762 ("drm/i915: Allocate rings from stolen")
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: intel-...@lists.freedesktop.org
Cc: # v4.9+
Reviewed-by: Daniele Cera
On 2/14/2023 3:48 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Direction from hardware is that stolen memory should never be used for
ring buffer allocations. There are too many caching pitfalls due to the
way stolen memory accesses are routed. So it is safest to just not use
it.
Wajdeczko
Cc: John Harrison
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 44 ++
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers
On 1/31/2023 2:28 PM, Michal Wajdeczko wrote:
Like we did it for GuC, introduce some helper print macros for
HuC to have unified format of messages that also include GT#.
While around improve some messages and use %pe if possible.
Signed-off-by: Michal Wajdeczko
Cc: John Harrison
---
dri
While doing #2, lets create a separate registers header file for PXP
to be consistent with other i915 global subsystems.
Signed-off-by: Alan Previn
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp
pes.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -26,6 +26,14 @@ struct intel_pxp {
*/
struct intel_gt *ctrl_gt;
+ /**
+* @gsccs_res: resources for request submission for platforms that have
a GSC engine.
+*/
+ struct gsccs_session_resources {
+
Cc: Tejas Upadhyay
Cc: Chris Wilson
Cc: Bruce Chang
Cc: Alan Previn
Cc: Matthew Auld
Cc: intel-...@lists.freedesktop.org
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 +++
1 file changed, 11
On 1/11/2023 5:54 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The CI results for the 'fast request' patch set (enables error return
codes for fire-and-forget H2G messages) hit an issue with the KMD
sending context submission requests on an invalid context. That was
caused by a f
On 1/11/2023 5:54 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The stats worker thread management was mis-matched between
enable/disable call sites. Fix those up. Also, abstract the cancel
code into a helper function rather than replicating in multiple places.
Signed-off-by: Joh
to be 'guc_capture' instead
so that it is a) more consistent and b) more obvious what it is.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 8
drivers/gpu/drm/i915/i915_gpu_error.h | 2
r is a ring and the stale data will be overwritten if it gets
full), but maybe something that can be improved as a follow-up.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: John Harrison
Reviewed-by: Umesh Nerlige Ramappa
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i
os;
+ unsigned long count = 0;
+
+ list_for_each(pos, list)
+ count++;
+
+ return count;
+}
+
+void intel_execlist_dump_active_requests(struct intel_engine_cs *engine,
nit: we usually use "execlists" and not "execlist".
Apart from this the patch LG
the KMD's back.
+*/
+ for_each_engine_masked(engine, gt, reset_fail_mask, id)
+ intel_guc_find_hung_context(engine);
I double checked and AFAICS this behavior applies to all our supported
GuC versions, so:
Reviewed-by: Daniele Cera
On 1/18/2023 10:49 PM, john.c.harri...@intel.com wrote:
From: John Harrison
There was a report of error captures occurring without any hung
context being indicated despite the capture being initiated by a 'hung
context notification' from GuC. The problem was not reproducible.
However, it is
On 1/18/2023 10:49 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The debugfs dump of requests was confused about what state requires
the execlist lock versus the GuC lock. There was also a bunch of
duplicated messy code between it and the error capture code.
So refactor the hung
t_find_hung_request(engine);
+ if (hung_rq)
+ hung_rq = i915_request_get_rcu(hung_rq);
}
Not a fan of the behavior asymmetry, but given that the 2 flows are
completely different I can't think of anything cleaner, so:
Reviewed-by: Daniele Ceraolo Spur
+77,7 @@ void intel_gt_pm_fini(struct intel_gt *gt);
void intel_gt_suspend_prepare(struct intel_gt *gt);
void intel_gt_suspend_late(struct intel_gt *gt);
+
Stray newline. With this removed:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
int intel_gt_resume(struct intel_gt *gt);
On 1/11/2023 1:42 PM, Alan Previn wrote:
On legacy platforms, KCR HW enabling is done at the time the mei
component interface is bound. It's also disabled during unbind.
However, for MTL onwards, we don't depend on the tee-component
operation before we can start sending GSC-CS firmware message
On 1/11/2023 1:42 PM, Alan Previn wrote:
Despite KCR subsystem being in the media-tile (close to the
GSC-CS), the IRQ controls for it are on GT-0 with other global
IRQ controls. Thus, add a helper for KCR hw interrupt
enable/disable functions to get the correct gt structure (for
uncore) for MT
On 1/11/2023 1:42 PM, Alan Previn wrote:
Add MTL's function for ARB session creation using PXP firmware
version 4.3 ABI structure format.
Before checking the return status, look at the GSC-CS-Mem-Header's
pending-bit which means the GSC firmware is busy and we should
resubmit.
Signed-off-by:
On 1/11/2023 1:42 PM, Alan Previn wrote:
Add GSC engine based method for sending PXP firmware packets
to the GSC firmware for MTL (and future) products. Use the newly
added helpers to populate the GSC-CS memory header and send the
message packet to the FW by dispatching the GSC_HECI_CMD_PKT
in
On 1/11/2023 1:42 PM, Alan Previn wrote:
Add helper functions into (new) common heci-packet-submission files
to handle generating the MTL GSC-CS Memory-Header and emitting of
the Heci-Cmd-Packet instructions that gets submitted to the engine.
NOTE1: This common functions for heci-packet-submi
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