Convert the existing text-based DT bindings for Mediatek MT8173 RT5650
codecs to a DT schema.
Signed-off-by: Ariel D'Alessandro
---
.../sound/mediatek,mt8173-rt5650.yaml | 73 +++
.../bindings/sound/mt8173-rt5650.txt | 31
2 files changed, 73 inser
Krzysztof,
On 8/21/25 3:50 AM, Krzysztof Kozlowski wrote:
On Wed, Aug 20, 2025 at 02:12:55PM -0300, Ariel D'Alessandro wrote:
Current, the DT bindings for Mediatek UFOe (Unified Frame Optimization
engine) is missing the mediatek,gce-client-reg property. Add it and
Why is it missing? I
* melfas,mip4_ts: Dropped unnecessary quotes. Added "active high" to
ce-gpios property description.
* mediatek,jpeg: Dropped patch as it doesn't apply.
Signed-off-by: Ariel D'Alessandro
Ariel D'Alessandro (12):
dt-bindings: media: Convert MediaTek mt8173-mdp bindings t
Convert the existing text-based DT bindings for MELFAS MIP4 Touchscreen
controller to a DT schema.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Rob Herring (Arm)
---
.../input/touchscreen/melfas,mip4_ts.yaml | 56 +++
.../input/touchscreen/melfas_mip4.txt
Current, the DT bindings for MediaTek's MT65xx Pin controller is missing
the gpio-line-names property, add it to the associated schema.
Signed-off-by: Ariel D'Alessandro
---
.../devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml| 2 ++
1 file changed, 2 insertions(+)
dif
Krzysztof,
On 8/21/25 3:46 AM, Krzysztof Kozlowski wrote:
On Wed, Aug 20, 2025 at 02:12:49PM -0300, Ariel D'Alessandro wrote:
Convert the existing text-based DT bindings for MediaTek MT8173 Media Data Path
to a YAML schema.
Please wrap commit message according to Linux coding
Krzysztof,
On 8/21/25 3:43 AM, Krzysztof Kozlowski wrote:
On Wed, Aug 20, 2025 at 02:12:51PM -0300, Ariel D'Alessandro wrote:
Current, the DT bindings for MediaTek mmsys controller is missing the
assigned-clocks and assigned-clocks-rates properties. Add these and
No, they do not miss th
Hi Rob,
On 8/21/25 11:28 AM, Rob Herring wrote:
On Wed, Aug 20, 2025 at 12:15 PM Ariel D'Alessandro
wrote:
Convert the existing text-based DT bindings for Marvell 8897/8997
(sd8897/sd8997) bluetooth devices controller to a YAML schema.
While here, bindings for "usb1286,204e"
ding users are updated to use bluetooth generic name
recommendation.
[0] Documentation/devicetree/bindings/net/btusb.txt
Signed-off-by: Ariel D'Alessandro
---
.../net/bluetooth/marvell,sd8897-bt.yaml | 79 ++
.../devicetree/bindings/net/btusb.txt | 2 +-
.
Krzysztof,
On 8/21/25 3:47 AM, Krzysztof Kozlowski wrote:
On Wed, Aug 20, 2025 at 02:12:50PM -0300, Ariel D'Alessandro wrote:
Convert the existing text-based DT bindings for Mediatek MT8173 Video Processor
Unit to a YAML schema.
DT schema, not YAML. Don't say YAML at all, neither h
Krzysztof,
On 9/9/25 3:29 AM, Krzysztof Kozlowski wrote:
On 08/09/2025 21:19, Ariel D'Alessandro wrote:
Krzysztof,
On 8/21/25 3:43 AM, Krzysztof Kozlowski wrote:
On Wed, Aug 20, 2025 at 02:12:51PM -0300, Ariel D'Alessandro wrote:
Current, the DT bindings for MediaTek mmsys con
The mediatek,mt8173-thermal device tree binding schema doesn't allow
regulator supplies like the ones defined in mt8173-elm.dtsi. Drop these as
the associated driver doesn't implement them either.
Signed-off-by: Ariel D'Alessandro
---
arch/arm64/boot/dts/mediatek/mt8173-elm.dt
Convert the existing text-based DT bindings for MediaTek MT8173 Media Data
Path to a DT schema.
Signed-off-by: Ariel D'Alessandro
---
.../bindings/media/mediatek,mt8173-mdp.yaml | 169 ++
.../bindings/media/mediatek-mdp.txt | 95 --
2 files changed
Krzysztof,
On 9/9/25 3:32 AM, Krzysztof Kozlowski wrote:
On 08/09/2025 19:52, Ariel D'Alessandro wrote:
Krzysztof,
On 8/21/25 3:46 AM, Krzysztof Kozlowski wrote:
On Wed, Aug 20, 2025 at 02:12:49PM -0300, Ariel D'Alessandro wrote:
[...]
+ - enum:
+ - media
Currently, the DT bindings for Mediatek PMIC Wrapper is missing the
power-domains property, which is used in the MT8173 E1 evaluation board as
it needs USB power domain.
Signed-off-by: Ariel D'Alessandro
Acked-by: Rob Herring (Arm)
---
.../bindings/soc/mediatek/mediatek,pwrap.yaml
Convert the existing text-based DT bindings for Dialog Semiconductor DA9211
Voltage Regulators family to a DT schema. Examples are simplified, as these
are all equal.
Signed-off-by: Ariel D'Alessandro
---
.../devicetree/bindings/regulator/da9211.txt | 205 --
.../bin
he regexes: '^pinctrl-[0-9]+$'
```
This commit adds the missing node property in the DT schema and updates the
example as well.
Signed-off-by: Ariel D'Alessandro
---
.../bindings/display/mediatek/mediatek,ufoe.yaml | 15 +++
1 file changed, 15 insertions(+)
di
According to the mediatek,mt8173-pinctrl device tree binding schema, the
pinctrl node names should match pattern 'pins$'. Fix this.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Linus Walleij
Acked-by: Rob Herring (Arm)
---
.../boot/dts/mediatek/mt8173-elm-hana.dtsi| 2
7;^pinctrl-[0-9]+$'
```
This commit adds the missing node property in the DT schema and updates the
example as well.
Signed-off-by: Ariel D'Alessandro
---
.../bindings/display/mediatek/mediatek,od.yaml | 14 ++
1 file changed, 14 insertions(+)
diff --git
a/Documentation/de
Convert the existing text-based DT bindings for Mediatek MT8173 Video
Processor Unit to a DT schema.
Signed-off-by: Ariel D'Alessandro
---
.../bindings/media/mediatek,mt8173-vpu.yaml | 74 +++
.../bindings/media/mediatek-vpu.txt | 31
2 files change
Mark,
On 8/20/25 2:19 PM, Mark Brown wrote:
On Wed, Aug 20, 2025 at 02:12:48PM -0300, Ariel D'Alessandro wrote:
This patch series continues the effort to address Device Tree validation
warnings for MediaTek platforms, with a focus on MT8173. It follows the initial
cleanup series by A
Ariel D'Alessandro
wrote:
+ ce-gpios:
+description: GPIO connected to the CE (chip enable) pin of the chip
+maxItems: 1
Mention that this should always have the flag GPIO_ACTIVE_HIGH
as this is required by the hardware.
Unfortunately we have no YAML syntax for enforcing
Rob,
On 8/22/25 12:52 PM, Rob Herring wrote:
On Wed, Aug 20, 2025 at 02:13:01PM -0300, Ariel D'Alessandro wrote:
Convert the existing text-based DT bindings for MELFAS MIP4 Touchscreen
controller to a YAML schema.
Signed-off-by: Ariel D'Alessandro
---
.../input/touchscr
Krzysztof,
On 9/10/25 11:21 AM, Krzysztof Kozlowski wrote:
On 10/09/2025 16:04, Ariel D'Alessandro wrote:
Krzysztof,
On 8/21/25 3:50 AM, Krzysztof Kozlowski wrote:
On Wed, Aug 20, 2025 at 02:12:55PM -0300, Ariel D'Alessandro wrote:
Current, the DT bindings for Mediatek UFOe (Uni
Rob,
On 8/20/25 3:55 PM, Rob Herring wrote:
On Wed, Aug 20, 2025 at 02:13:02PM -0300, Ariel D'Alessandro wrote:
Commit 14176e94bb35d ("arm64: dts: mediatek: mt8195: Fix ranges for jpeg
That commit is not in any upstream tree.
Ugh, indeed. Dropping this patch.
enc/dec
Krzysztof,
On 8/21/25 3:53 AM, Krzysztof Kozlowski wrote:
On Wed, Aug 20, 2025 at 02:12:58PM -0300, Ariel D'Alessandro wrote:
Convert the existing text-based DT bindings for Dialog Semiconductor DA9211
Voltage Regulators family to a YAML schema. Examples are simplified, as
these are all
Rob,
On 8/22/25 12:14 PM, Rob Herring wrote:
On Wed, Aug 20, 2025 at 02:12:53PM -0300, Ariel D'Alessandro wrote:
Convert the existing text-based DT bindings for Mediatek MT8173 RT5650
codecs to a YAML schema.
Signed-off-by: Ariel D'Alessandro
---
.../sound/mediatek,mt8173-r
The mediatek,mt8173-thermal device tree binding schema doesn't allow
regulator supplies like the ones defined in mt8173-elm.dtsi. Drop these
as the associated driver doesn't implement them either.
Signed-off-by: Ariel D'Alessandro
---
arch/arm64/boot/dts/mediatek/mt8173-elm.dt
Current, the DT bindings for Mediatek OD (display overdrive) is missing
the mediatek,gce-client-reg property. Add it and update the example as
well.
Signed-off-by: Ariel D'Alessandro
---
.../bindings/display/mediatek/mediatek,od.yaml | 10 ++
1 file changed, 10 inser
Convert the existing text-based DT bindings for Mediatek MT8173 Video Processor
Unit to a YAML schema.
Signed-off-by: Ariel D'Alessandro
---
.../bindings/media/mediatek,mt8173-vpu.yaml | 76 +++
.../bindings/media/mediatek-vpu.txt | 31
2 files change
Currently, the DT bindings for Mediatek PMIC Wrapper is missing the
power-domains property, which is used in the MT8173 E1 evaluation board
as it needs USB power domain.
Signed-off-by: Ariel D'Alessandro
---
.../bindings/soc/mediatek/mediatek,pwrap.yaml | 15 +++
1 file ch
Commit 14176e94bb35d ("arm64: dts: mediatek: mt8195: Fix ranges for jpeg
enc/decoder nodes") redefined jpeg encoder/decoder children node ranges.
Update the related device tree binding yaml definition to match
mediatek/mt8195.dtsi, as this is currently the only one using it.
Signed-off
Convert the existing text-based DT bindings for MELFAS MIP4 Touchscreen
controller to a YAML schema.
Signed-off-by: Ariel D'Alessandro
---
.../input/touchscreen/melfas,mip4_ts.yaml | 55 +++
.../input/touchscreen/melfas_mip4.txt | 20 ---
2 files change
Current, the DT bindings for MediaTek's MT65xx Pin controller is missing
the gpio-line-names property, add it to the associated schema.
Signed-off-by: Ariel D'Alessandro
---
.../devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml| 2 ++
1 file changed, 2 insertions(+)
dif
Convert the existing text-based DT bindings for Dialog Semiconductor DA9211
Voltage Regulators family to a YAML schema. Examples are simplified, as
these are all equal.
Signed-off-by: Ariel D'Alessandro
---
.../devicetree/bindings/regulator/da9211.txt | 205 --
.../bin
According to the mediatek,mt8173-pinctrl device tree binding schema, the
pinctrl node names should match pattern 'pins$'. Fix this.
Signed-off-by: Ariel D'Alessandro
---
.../boot/dts/mediatek/mt8173-elm-hana.dtsi| 2 +-
arch/arm64/boot/dts/mediatek/mt8173
Current, the DT bindings for Mediatek UFOe (Unified Frame Optimization
engine) is missing the mediatek,gce-client-reg property. Add it and
update the example as well.
Signed-off-by: Ariel D'Alessandro
---
.../bindings/display/mediatek/mediatek,ufoe.yaml | 11 +++
1 file change
Convert the existing text-based DT bindings for Mediatek MT8173 RT5650
codecs to a YAML schema.
Signed-off-by: Ariel D'Alessandro
---
.../sound/mediatek,mt8173-rt5650.yaml | 73 +++
.../bindings/sound/mt8173-rt5650.txt | 31
2 files change
devicetree/bindings/net/btusb.txt
Signed-off-by: Ariel D'Alessandro
---
.../bindings/net/marvell,sd8897-bt.yaml | 91 +++
.../bindings/net/marvell-bt-8xxx.txt | 83 -
2 files changed, 91 insertions(+), 83 deletions(-)
create mode 100644 Documenta
Current, the DT bindings for MediaTek mmsys controller is missing the
assigned-clocks and assigned-clocks-rates properties. Add these and
update the example as well.
Signed-off-by: Ariel D'Alessandro
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 9 +
1 file chang
Convert the existing text-based DT bindings for MediaTek MT8173 Media Data Path
to a YAML schema.
Signed-off-by: Ariel D'Alessandro
---
.../bindings/media/mediatek,mt8173-mdp.yaml | 174 ++
.../bindings/media/mediatek-mdp.txt | 95 --
2 files changed
patchset
eliminates several of the remaining warnings by improving or converting DT
bindings to YAML, adding missing properties, and updating device tree files
accordingly.
Signed-off-by: Ariel D'Alessandro
Ariel D'Alessandro (14):
media: dt-bindings: Convert MediaTek mt8173-mdp b
page
table format. To achieve that, a "GPU optional quirks" field was added
to `struct panfrost_features` with the related flag.
Note that, in order to enable AARCH64_4K mode, the GPU variant must have
the HW_FEATURE_AARCH64_MMU feature flag present.
Signed-off-by: Ariel D'A
Hi Steven,
On 3/31/25 8:15 AM, Steven Price wrote:
On 24/03/2025 18:57, Ariel D'Alessandro wrote:
Currently, Panfrost only supports MMU configuration in "LEGACY" (as
Bifrost calls it) mode, a (modified) version of LPAE "Large Physical
Address Extension", which in Linu
this commit. Tested on a Mediatek (MT8395) Genio 1200 EVK board.
[0] https://github.com/glmark2/glmark2
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 +
1 file changed, 1 insertion(+)
Set this feature flag on all Mali Bifrost platforms as the MMU supports
AARCH64 4K page table format.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Adrián Larumbe
---
drivers/gpu/drm/pan
Panfrost does not support uncached mappings, so flag them properly. Also
flag the pages that are mapped as response to a page fault as cached.
Signed-off-by: Boris Brezillon
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Steven Price
Review
fined caching policy" is good enough...
```
Now that Panfrost supports AARCH64_4K page table format, let's enable it
on Mediatek MT8188 and configure the cache/shareability policies
properly.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del Regno
Reviewed
As done in panthor, define and use these GPU_MMU_FEATURES_* macros,
which makes code easier to read and reuse.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Adrián Larumbe
---
drivers/gp
ot; patch.
* Replaced `panfrost_mmu->enable()` function pointer by `cfg` struct
prepared during init time.
* Made mali_lpae/aarch64_4k name more clear.
* Added GPU_CONFIG_AARCH64_4K flag to enable AARCH64_4K page table
format.
* Enabled AARCH64_4K mode only on mediatek-mt8188.
Ariel D'Ales
Adrian,
On 3/22/25 3:48 PM, Adrian Larumbe wrote:
On 17.03.2025 11:52, Ariel D'Alessandro wrote:
Currently, Panfrost only supports MMU configuration in "LEGACY" (as
Bifrost calls it) mode, a (modified) version of LPAE "Large Physical
Address Extension", which in Linu
pointer by `cfg` struct
prepared during init time.
* Made mali_lpae/aarch64_4k name more clear.
* Added GPU_CONFIG_AARCH64_4K flag to enable AARCH64_4K page table
format.
* Enabled AARCH64_4K mode only on mediatek-mt8188.
Ariel D'Alessandro (6):
drm/panfrost: Set IOMMU_CACHE flag
drm/panfrost:
fined caching policy" is good enough...
```
Now that Panfrost supports AARCH64_4K page table format, let's enable it
on Mediatek MT8188 and configure the cache/shareability policies
properly.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del Regno
Reviewed
this commit. Tested on a Mediatek (MT8395) Genio 1200 EVK board.
[0] https://github.com/glmark2/glmark2
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 +
1 file changed, 1 insertion(+)
page
table format. To achieve that, a "GPU optional quirks" field was added
to `struct panfrost_features` with the related flag.
Note that, in order to enable AARCH64_4K mode, the GPU variant must have
the HW_FEATURE_AARCH64_MMU feature flag present.
Signed-off-by: Ariel D'A
Panfrost does not support uncached mappings, so flag them properly. Also
flag the pages that are mapped as response to a page fault as cached.
Signed-off-by: Boris Brezillon
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Steven Price
---
driver
Set this feature flag on all Mali Bifrost platforms as the MMU supports
AARCH64 4K page table format.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/panfrost/panfrost_features.h | 3 +
As done in panthor, define and use these GPU_MMU_FEATURES_* macros,
which makes code easier to read and reuse.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/panfrost/panfrost_mmu.c
Boris,
On 3/17/25 10:44 AM, Boris Brezillon wrote:
On Mon, 17 Mar 2025 09:40:42 -0300
Ariel D'Alessandro wrote:
+static int panfrost_mmu_cfg_init(struct panfrost_mmu *mmu,
+ enum io_pgtable_fmt fmt)
+{
+ struct panfrost_device *pfdev = mmu-&
this commit. Tested on a Mediatek (MT8395) Genio 1200 EVK board.
[0] https://github.com/glmark2/glmark2
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 +
1 file changed, 1 insertion(+)
As done in panthor, define and use these GPU_MMU_FEATURES_* macros,
which makes code easier to read and reuse.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/panfrost/panfrost_mmu.c
fined caching policy" is good enough...
```
Now that Panfrost supports AARCH64_4K page table format, let's enable it
on Mediatek MT8188 and configure the cache/shareability policies
properly.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del Regno
Reviewed
page
table format. To achieve that, a "GPU optional quirks" field was added
to `struct panfrost_features` with the related flag.
Note that, in order to enable AARCH64_4K mode, the GPU variant must have
the HW_FEATURE_AARCH64_MMU feature flag present.
Signed-off-by: Ariel D'A
Panfrost does not support uncached mappings, so flag them properly. Also
flag the pages that are mapped as response to a page fault as cached.
Signed-off-by: Boris Brezillon
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Steven Price
---
driver
Set this feature flag on all Mali Bifrost platforms as the MMU supports
AARCH64 4K page table format.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/panfrost/panfrost_features.h | 3 +
_4k name more clear.
* Added GPU_CONFIG_AARCH64_4K flag to enable AARCH64_4K page table
format.
* Enabled AARCH64_4K mode only on mediatek-mt8188.
Ariel D'Alessandro (6):
drm/panfrost: Set IOMMU_CACHE flag
drm/panfrost: Use GPU_MMU_FEATURES_VA_BITS/PA_BITS macros
drm/panfrost: Set HW_FEATUR
Boris,
On 3/15/25 5:43 AM, Boris Brezillon wrote:
On Fri, 14 Mar 2025 14:38:56 -0300
Ariel D'Alessandro wrote:
Currently, Panfrost only supports MMU configuration in "LEGACY" (as
Bifrost calls it) mode, a (modified) version of LPAE "Large Physical
Address Extension&qu
_4K page table
format.
* Enabled AARCH64_4K mode only on mediatek-mt8188.
Ariel D'Alessandro (6):
drm/panfrost: Set IOMMU_CACHE flag
drm/panfrost: Use GPU_MMU_FEATURES_VA_BITS/PA_BITS macros
drm/panfrost: Set HW_FEATURE_AARCH64_MMU feature flag on Bifrost
models
drm/panfrost: Add
Angelo,
On 3/11/25 6:09 AM, AngeloGioacchino Del Regno wrote:
Il 10/03/25 20:59, Ariel D'Alessandro ha scritto:
Now that Panfrost supports AARCH64_4K page table format, let's enable it
on Mediatek MT8188.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/pan
Set this feature flag on all Mali Bifrost platforms as the MMU supports
AARCH64 4K page table format.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_features.h | 3 +++
1 file changed, 3 insertions(+)
diff
Hi Steven,
On 2/27/25 11:44 AM, Steven Price wrote:
On 26/02/2025 18:30, Ariel D'Alessandro wrote:
Bifrost MMUs support AArch64 4kB granule specification. However,
panfrost only enables MMU in legacy mode, despite the presence of the
HW_FEATURE_AARCH64_MMU feature flag.
This commit
Panfrost does not support uncached mappings, so flag them properly. Also
flag the pages that are mapped as response to a page fault as cached.
Signed-off-by: Boris Brezillon
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Steven Price
---
driver
this commit. Tested on a Mediatek (MT8395) Genio 1200 EVK board.
[0] https://github.com/glmark2/glmark2
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c
b/drivers/gpu/dr
As done in panthor, define and use these GPU_MMU_FEATURES_* macros,
which makes code easier to read and reuse.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_mmu.c | 6 --
drivers/gpu/drm/pan
fined caching policy" is good enough...
```
Now that Panfrost supports AARCH64_4K page table format, let's enable it
on Mediatek MT8188 and configure the cache/shareability policies
properly.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: AngeloGioacchino Del Regno
---
driv
page
table format. To achieve that, a "GPU optional quirks" field was added
to `struct panfrost_features` with the related flag.
Note that, in order to enable AARCH64_4K mode, the GPU variant must have
the HW_FEATURE_AARCH64_MMU feature flag present.
Signed-off-by: Ariel D'Alessandr
Boris,
On 3/11/25 5:06 AM, Boris Brezillon wrote:
On Mon, 10 Mar 2025 16:59:20 -0300
Ariel D'Alessandro wrote:
Now that Panfrost supports AARCH64_4K page table format, let's enable it
on Mediatek MT8188.
Can you maybe give more details on why this is needed
(legacy sh
Boris, Angelo,
On 3/11/25 7:05 AM, Boris Brezillon wrote:
On Tue, 11 Mar 2025 10:14:44 +0100
AngeloGioacchino Del Regno
wrote:
Il 11/03/25 09:05, Boris Brezillon ha scritto:
On Mon, 10 Mar 2025 16:59:19 -0300
Ariel D'Alessandro wrote:
Currently, Panfrost only support
Boris,
On 3/11/25 5:05 AM, Boris Brezillon wrote:
On Mon, 10 Mar 2025 16:59:19 -0300
Ariel D'Alessandro wrote:
Currently, Panfrost only supports MMU configuration in "LEGACY" (as
Bifrost calls it) mode, a (modified) version of LPAE "Large Physical
Address Extension&qu
Angelo,
On 3/11/25 6:10 AM, AngeloGioacchino Del Regno wrote:
Il 10/03/25 20:59, Ariel D'Alessandro ha scritto:
Currently, Panfrost only supports MMU configuration in "LEGACY" (as
Bifrost calls it) mode, a (modified) version of LPAE "Large Physical
Address Extension&qu
Boris,
On 3/11/25 4:51 AM, Boris Brezillon wrote:
On Mon, 10 Mar 2025 16:59:18 -0300
Ariel D'Alessandro wrote:
Both these functions write to MMU_AS_CONTROL register in the same way.
Define a common _panfrost_mmu_as_control_write function with the shared
code.
Signed-off-by:
Panfrost does not support uncached mappings, so flag them properly. Also
flag the pages that are mapped as response to a page fault as cached.
Signed-off-by: Boris Brezillon
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_mmu.c | 4 ++--
1 file changed, 2 inser
e/aarch64_4k name more clear.
* Added GPU_CONFIG_AARCH64_4K flag to enable AARCH64_4K page table
format.
* Enabled AARCH64_4K mode only on mediatek-mt8188.
Ariel D'Alessandro (6):
drm/panfrost: Set IOMMU_CACHE flag
drm/panfrost: Use GPU_MMU_FEATURES_VA_BITS/PA_BITS macros
drm/panfrost: Unify p
Set this feature flag on all Mali Bifrost platforms as the MMU supports
AARCH64 4K page table format.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_features.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_features.h
b/dr
page
table format. To achieve that, a "GPU optional configurations" field was
added to `struct panfrost_features` with the related flag.
Note that, in order to enable AARCH64_4K mode, the GPU variant must have
the HW_FEATURE_AARCH64_MMU feature flag present.
Signed-off-by: Arie
As done in panthor, define and use these GPU_MMU_FEATURES_* macros,
which makes code easier to read and reuse.
Signed-off-by: Ariel D'Alessandro
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/panfrost_mmu.c | 6 --
drivers/gpu/drm/pan
Hi Boris,
On 2/27/25 11:55 AM, Boris Brezillon wrote:
On Wed, 26 Feb 2025 15:30:42 -0300
Ariel D'Alessandro wrote:
@@ -642,8 +713,15 @@ struct panfrost_mmu *panfrost_mmu_ctx_create(struct
panfrost_device *pfdev)
.iommu_dev = pfdev->dev,
};
- mmu-&g
Now that Panfrost supports AARCH64_4K page table format, let's enable it
on Mediatek MT8188.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c
b/drivers/gpu/dr
Both these functions write to MMU_AS_CONTROL register in the same way.
Define a common _panfrost_mmu_as_control_write function with the shared
code.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_mmu.c | 33 -
1 file changed, 16 insertions(+
Boris,
On 2/27/25 5:30 AM, Boris Brezillon wrote:
On Wed, 26 Feb 2025 15:30:42 -0300
Ariel D'Alessandro wrote:
Bifrost MMUs support AArch64 4kB granule specification. However,
panfrost only enables MMU in legacy mode, despite the presence of the
HW_FEATURE_AARCH64_MMU feature flag.
Boris,
On 2/27/25 5:25 AM, Boris Brezillon wrote:
On Wed, 26 Feb 2025 15:30:41 -0300
Ariel D'Alessandro wrote:
[snip]
diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h
b/drivers/gpu/drm/panfrost/panfrost_regs.h
index b5f279a19a08..4e6064d5feaa 100644
--- a/drivers/gpu/drm/pan
conditionally based on
the GPU model's HW_FEATURE_AARCH64_MMU feature flag.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
drivers/gpu/drm/panfrost/panfrost_mmu.c| 118 +
drivers/gpu/drm/panfrost/panfrost_regs.h | 29
Mali Bifrost MMU support AArch64 4kB page tables. This feature is in
panfrost based the HW_FEATURE_AARCH64_MMU feature flag.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_features.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/pan
The TRANSTAB (Translation table base address) layout is different
depending on the legacy mode configuration.
Currently, the defined values apply to the legacy mode. Let's rename
them so we can add the ones for no-legacy mode.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/dr
[0] https://lists.freedesktop.org/archives/dri-devel/2019-May/217617.html
Thanks!
Ariel D'Alessandro (4):
drm/panfrost: Use GPU_MMU_FEATURES_VA_BITS/PA_BITS macros
drm/panfrost: Split LPAE MMU TRANSTAB register values
drm/panfrost: Support ARM_64_LPAE_S1 page table
drm/panfrost: Set HW_FEAT
As done in panthor, define and use these GPU_MMU_FEATURES_* macros,
which makes code easier to read and reuse.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_mmu.c | 6 --
drivers/gpu/drm/panfrost/panfrost_regs.h | 2 ++
2 files changed, 6 insertions(
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