I have moved on to other stuff for now. Haven't been able to make time
to review bridge related work. Andrzej has been doing it by himself
for a while now.
Cc: Andrzej Hajda
Cc: Laurent Pinchart
Cc: Gustavo Padovan
Cc: Maarten Lankhorst
Cc: Sean Paul
Cc: Daniel Vetter
Signed-off-by: A
ot;);
+ return ret;
+ }
+
+ drm_connector_helper_add(&ctx->connector,
+&tc358764_connector_helper_funcs);
+ drm_mode_connector_attach_encoder(&ctx->connector, bridge->encoder);
+ drm_panel_attach(ctx->pan
Thanks, I'll give this a try.
The patch looks good, anyway. Rob's queued it for msm-next.
Archit
Therefore, I asked the X11 people where to fix:
https://www.spinics.net/lists/xorg/msg58969.html
Best regards
-Carsten
2018-07-24 19:33 GMT+02:00 Archit Taneja <mailto:arch...
On Wednesday 11 July 2018 09:18 PM, Rob Herring wrote:
On Mon, Jul 09, 2018 at 02:37:51PM +0530, Archit Taneja wrote:
Add binding info for peripherals that support dual-channel DSI. Add
corresponding optional bindings for DSI host controllers that may
be configured in this mode. Add an
On Monday 09 July 2018 02:37 PM, Archit Taneja wrote:
Add a section that describes dt-bindings for peripherals that support
MIPI DSI, but have a different bus as the primary control bus, or no
control bus at all. Add an example for a peripheral with a non-DSI
control bus.
Reviewed-by: Rob
asn't able to generate negative x/y
co-ordinates. I'm using linaro's debian userspace, running lxqt.
Thanks,
Archit
Signed-off-by: Carsten Behling
---
Changes in v2:
- fixed format specifier in debug message
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 51
, I don't think we need to change pclk_rate to u64. A u32 can
hold up to a 2.14 Ghz pixel clock, which we're still quite far away
from in real life. u64 for pclk_bpp is right, though.
Thanks,
Archit
if (!mode) {
pr_err("%s: mode not set\n", __func__);
mdss derivations to include any extensions.
Add mdss helper interface (msm_mdss_funcs) to msm_mdss
base for mdp5/dpu mdss specific implementation calls.
This change subclasses msm_mdss for mdp5, dpu specific
changes will be done separately.
Reviewed-by: Archit Taneja
Changes in v3
On Monday 09 July 2018 11:01 PM, Sean Paul wrote:
From: Rajesh Yadav
postdiv_lock spinlock was used before initialization
for 10nm pll. It causes following spin_bug:
"BUG: spinlock bad magic on CPU#0".
Initialize spinlock before its usage.
Reviewed-by: Archit Taneja
On Monday 09 July 2018 11:01 PM, Sean Paul wrote:
From: Chandan Uddaraju
For dual dsi mode, the horizontal timing needs
to be divided by half since both the dsi controllers
will be driving this panel. Adjust the pixel clock and
DSI timing accordingly.
Reviewed-by: Archit Taneja
Changes
Cornu
Reviewed-by: Sean Paul
Signed-off-by: Archit Taneja
---
.../devicetree/bindings/display/mipi-dsi-bus.txt | 71 +++---
1 file changed, 64 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
b/Documentation/devicetree
nges in v2:
- Incorported Rob's comments.
Archit Taneja (2):
dt-bindings: mipi-dsi: Add info about peripherals with non-DSI control
bus
dt-bindings: mipi-dsi: Add dual-channel DSI related info
.../devicetree/bindings/display/mipi-dsi-bus.txt | 153 +++--
1 file
Reviewed-by: Heiko Stuebner
Signed-off-by: Archit Taneja
---
.../devicetree/bindings/display/mipi-dsi-bus.txt | 80 ++
1 file changed, 80 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
b/Documentation/devicetree/bindings/display/mipi-dsi
lly be false, and avoid us trying to configure the registers
again, but I'm not entirely sure.
if (status == connector_status_connected && hpd && adv7511->powered) {
regcache_mark_dirty(adv7511->regmap);
...
In any case:
Reviewed-by: Archit Taneja
Arguabl
current implementation even inactive nodes get added
resulting in creation of redundant connectors.
Reviewed-by: Archit Taneja
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.c | 6 +-
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 10
On Saturday 16 June 2018 11:26 AM, Abhinav Kumar wrote:
Currently, DRM bridge for DPU relies on the default video
mode setting to set the encoder mode.
Add an explicit call to set the encoder mode for bridges.
Reviewed-by: Archit Taneja
Signed-off-by: Abhinav Kumar
---
drivers/gpu
On Wednesday 06 June 2018 04:16 PM, Heiko Stübner wrote:
Hi Archit,
Am Mittwoch, 6. Juni 2018, 12:21:16 CEST schrieb Archit Taneja:
On Wednesday 06 June 2018 02:00 PM, Heiko Stübner wrote:
Am Mittwoch, 6. Juni 2018, 07:59:29 CEST schrieb Archit Taneja:
On Monday 04 June 2018 05:47 PM
On Wednesday 06 June 2018 02:00 PM, Heiko Stübner wrote:
Am Mittwoch, 6. Juni 2018, 07:59:29 CEST schrieb Archit Taneja:
On Monday 04 June 2018 05:47 PM, Heiko Stuebner wrote:
Am Donnerstag, 18. Januar 2018, 05:53:55 CEST schrieb Archit Taneja:
Add binding info for peripherals that support
On Monday 04 June 2018 05:47 PM, Heiko Stuebner wrote:
Am Donnerstag, 18. Januar 2018, 05:53:55 CEST schrieb Archit Taneja:
Add binding info for peripherals that support dual-channel DSI. Add
corresponding optional bindings for DSI host controllers that may
be configured in this mode. Add an
return ret;
+}
+
+static int tc358764_probe(struct mipi_dsi_device *dsi)
+{
+ struct device *dev = &dsi->dev;
+ struct tc358764 *ctx;
+ int ret;
+
+ ctx = devm_kzalloc(dev, sizeof(struct tc358764), GFP_KERNEL);
+ if (!ctx)
+ retur
since v4.17-rc1 :
Reviewed-by: Archit Taneja
Internal error: Oops: 9607 [#1] PREEMPT SMP
[...]
CPU: 0 PID: 124 Comm: irq/32-dw_hdmi_ Not tainted 4.17.0-rc7 #2
Hardware name: Libre Technology CC (DT)
[...]
pc : osq_lock+0x54/0x188
lr : __mutex_lock.isra.0+0x74/0x530
[...]
Process irq/32
On Friday 27 April 2018 03:11 AM, Laurent Pinchart wrote:
Hi Peter,
Thank you for the patch.
On Friday, 27 April 2018 00:36:44 EEST Peter Rosin wrote:
Could perhaps prevent some confusion.
queued to drm-misc-next
Thanks,
Archit
Signed-off-by: Peter Rosin
Reviewed-by: Laurent
ge(5000, 6000);
gpiod_set_value_cansleep(adv7511->gpio_pd, 0);
}
The patch looks good to me.
Reviewed-by: Laurent Pinchart
queued to drm-misc-next
Thanks,
Archit
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On Tuesday 13 February 2018 11:18 PM, Kieran Bingham wrote:
From: Kieran Bingham
The ADV7511 has four 256-byte maps that can be accessed via the main I2C
ports. Each map has it own I2C address and acts as a standard slave
device on the I2C bus.
Extend the device tree node bindings to be able
On Tuesday 13 February 2018 11:18 PM, Kieran Bingham wrote:
From: Kieran Bingham
The ADV7511 has four 256-byte maps that can be accessed via the main I2C
ports. Each map has it own I2C address and acts as a standard slave
device on the I2C bus.
Allow a device tree node to override the defaul
On Saturday 21 April 2018 11:50 AM, Boris Brezillon wrote:
Hi Archit,
On Sun, 15 Apr 2018 13:39:44 +0530
Archit Taneja wrote:
+static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,
+struct cdns_dphy_cfg *cfg
Hi,
On Saturday 14 April 2018 12:55 PM, Abhinav Kumar wrote:
From: Archit Taneja
You can drop DPU from the subject. Also, you'd need to add
Theirry Reading for panel related patches, and Rob Herring
for an Ack on the DT bindings.
I think you can change the author to yourself. You'
V2:
-Removed Change-Id from the commit text tags.
-Remove extra parentheses
Changes in V3:
-None
Reviewed-by: Archit Taneja
Signed-off-by: Chandan Uddaraju
---
drivers/gpu/drm/msm/dsi/dsi.c | 3 +
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm
On Thursday 19 April 2018 01:15 AM, Chandan Uddaraju wrote:
For dual dsi mode, the horizontal timing needs
to be divided by half since both the dsi controllers
will be driving this panel. Adjust the pixel clock and
DSI timing accordingly.
Reviewed-by: Archit Taneja
Changes in V2
On Thursday 19 April 2018 09:20 PM, Philippe CORNU wrote:
Hi Archit & Andrzej,
May I ask you please a short review of this documentation update.
Many thanks
Philippe :-)
On 04/09/2018 05:24 PM, Philippe Cornu wrote:
This patch clarifies the adjusted_mode documentation
for bri
On Wednesday 18 April 2018 01:58 PM, Daniel Mack wrote:
On Wednesday, April 18, 2018 10:06 AM, Archit Taneja wrote:
On Tuesday 17 April 2018 05:51 PM, Daniel Mack wrote:
Thanks for debugging this so thoroughly.
It shows an underlying problem in the msm driver's clock components
t
Hi Daniel,
On Tuesday 17 April 2018 05:51 PM, Daniel Mack wrote:
(cc Stephen)
Hi Archit,
On Monday, April 16, 2018 07:06 PM, Daniel Mack wrote:
On Monday, April 09, 2018 03:08 PM, Archit Taneja wrote:
You could comment out the pm_runtime_put_sync() calls in
drivers/gpu/drm/msm/dsi
else if (dlane_bps >= 125000)
+ cfg->pll_opdiv = 1;
+ else if (dlane_bps >= 63000)
+ cfg->pll_opdiv = 2;
+ else if (dlane_bps >= 32000)
+ cfg->pll_opdiv = 4;
+ else if (dlane_bps >= 16000)
+ cfg->pll_opdiv = 8;
+
+ /*
+* Allow a deviation of 0.2% on the per-lane data rate to try to
+* recover a potential mismatch between DPI and PPI clks.
+*/
+ dlane_bps_max = dlane_bps + (dlane_bps / 500);
kbuild reported an error for 32 bit archs. I'm guessing it's because of
this divide above?
+
+ fbdiv_max = DIV_ROUND_DOWN_ULL((dlane_bps + (dlane_bps / 500)) * 2 *
You could use dlane_bps_max here instead.
Otherwise,
Reviewed-by: Archit Taneja
Thanks,
Archit
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On Monday 09 April 2018 04:28 PM, Daniel Mack wrote:
Hi Archit,
Thanks a lot for your reply.
On Friday, April 06, 2018 01:25 PM, Archit Taneja wrote:
On Thursday 05 April 2018 08:28 PM, Daniel Mack wrote:
I'm having issues with the GPU/DRM drivers on a msm8916 based platform
which is
Hi Abhinav,
Thanks for posting this driver. Some comments below.
On Saturday 07 April 2018 12:36 PM, Abhinav Kumar wrote:
From: Archit Taneja
Add support for truly dual DSI video mode panel
panel used in MSM reference platforms >
Signed-off-by: Archit Taneja
Signed-off-by: Abhinav Ku
On Saturday 07 April 2018 01:20 PM, Abhinav Kumar wrote:
Currently the DSI PHY timings are hard-coded for a specific panel
for the 10nm PHY.
Replace this with the auto PHY timing calculator which can calculate
the PHY timings for any panel.
Reviewed-by: Archit Taneja
Signed-off-by
ehow got corrupt. Is the panel initialized using DCS
commands too?
Thanks,
Archit
http://git.linaro.org/landing-teams/working/qualcomm/kernel.git/log/?h=release/qcomlt-4.9
http://git.linaro.org/landing-teams/working/qualcomm/kernel.git/log/?h=release/qcomlt-4.14
I've looked at the develo
On Thursday 29 March 2018 12:36 AM, Sean Paul wrote:
Ensure that any queued events are issued when disabling the crtc. This
avoids timeouts when we come back and wait for dependencies (like the
previous frame's flip_done).
Reviewed-by: Archit Taneja
Changes in v2:
- None
Signed-o
On Thursday 29 March 2018 12:36 AM, Sean Paul wrote:
Don't leave the event != NULL once it's consumed, this is used a signal
s/used a/used as a ?
to the atomic helpers that the event will be handled by the driver.
Reviewed-by: Archit Taneja
Changes in v2:
- None
Cc: Jeykuma
On Thursday 29 March 2018 12:36 AM, Sean Paul wrote:
Factor out the commit_tail() portions of complete_commit() into a
separate function to facilitate moving to the atomic helpers in future
patches.
Reviewed-by: Archit Taneja
Changes in v2:
- None
Cc: Jeykumar Sankaran
Signed-off-by
in disp duplicate_state callback (Jeykumar)
Changes in v3:
- Update comment describing msm_kms_state (Jeykumar)
Changes in v4:
- Rebased on msm-next
- Don't always use private state from atomic state (Archit)
- Renamed some of the state accessors
- Tested on mdp5 db410c
Changes in v5:
Signed-off-by: Stefan Agner
Reviewed-by: Archit Taneja
Archit
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 0f7324a686ca..d729b2b4b66d 1006
replaced with the corresponding
helper function.
Reviewed-by: Archit Taneja
V2:
Removes command broadcast support for DSI 6G v2.0+ controllers from
the patch series and incorporates all the suggested corrections
Sibi S (3):
drm/msm/dsi: add dsi host helper functions support
isn't referred when
configuring SMP registers, we see underruns immediately.
An easy way to reproduce this is to use modset on db410c. I think
it might occur with this patch too. It might be worth trying it
out.
Thanks,
Archit
Cc: Jeykumar Sankaran
Reviewed-by: Jeykumar Sankaran
Si
ler or the eDP panel. I don't have any strong opinion
about it, though.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Alexandru M Stan
---
Documentation/devicetree/bindings/display/bridge/analogix_dp.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documenta
streamclk is ok if we wait enough time,
it does no effect on display.
Let's change this error to warn.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Douglas Anderson
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signe
nd we
will do fast link training since we have set fast_link flag to 1. In
fact, we should do full link training now, not the fast link training.
So we should move the fast link detection at the end of set_bridge.
Is it possible to re-write this commit message? It's a bit hard to
follow.
Than
was finding AUX channel errors and eventually
reported "Failed to apply PSR", where I had a kgdb breakpoint. Presumably
the device would have eventually given up and shut down anyway, but it
seems better to fix the order to be more correct.
Reviewed-by: Archit Taneja
Thanks,
Archit
C
bug.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: 征增 王
Signed-off-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Balletbo i Serra
Tested-by: Marek Szyprowski
---
drivers/gpu/drm/bridge/analogix/analogi
could adjust
the comment, but it seems more likely that we want the same retry
behavior across all platforms.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Cc: 征增 王
Signed-off-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by:
edp phy,
BIT 7 reserved
BIT 6 RK_VID_CAP_FUNC_EN_N
BIT 5 RK_VID_FIFO_FUNC_EN_N
So, we should do some private operations to Rockchip.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Tomasz Figa
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.
Reviewed-by: Archit Taneja
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
If we failed disable psr, it would hang the display until next psr
cycle coming. So we should restore psr->state when it failed.
For the bridge part,
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Tom
EMOTEIO;
A couple of ETIMEDOUTs have been replaced with EREMOTEIOs after this
change. Maybe we set it the error no in ret and return ret?
With those changes,
Reviewed-by: Archit Taneja
Thanks,
Archit
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ht? AUX_PD
sounds like just one of the fields of the register.
With that,
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Douglas Anderson
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Balletbo i Serra
Tested
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
We need to check the dpcd write/read return value to see whether the
write/read was successful
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Kristian H. Kristensen
Signed-off-by: Lin Huang
Signed-off
, we just
enable it at the beginning of link training and then keep it on all the
time.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Tomasz Figa
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Balletbo i
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
There was a 1ms delay to detect the hpd signal, which is too short to
detect a short pulse. This patch extends this delay to 100ms.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Cc: 征
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
When panel is shut down, we should make sure edp can be disabled to avoid
undefined behavior.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
Following the correct power up sequence:
dp_pd=ff => dp_pd=7f => wait 10us => dp_pd=00
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by:
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
According to DP spec v1.3 chap 3.5.1.2 Link Training, Link Policy Maker
must first detect that the HPD signal is asserted high by the Downstream
Device before establishing a link with it.
Reviewed-by: Archit
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
When we enable bridge failed, we have to retry it, otherwise we would get
the abnormal display.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by
27;s reset fast_train_enable in
analogix_dp_bridge_disable();
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by: Enric Balletbo i Serra
Tested-by: Marek Szyprowski
---
drivers/gpu/
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
We should check AUX_EN bit to confirm the AUX CH operation is completed.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: zain wang
Signed-off
loop? Is it a consequence of calling
analogix_dp_start_video() earlier, or is this the preferred time
mentioned in the specs?
Thanks,
Archit
}
/* Set to use the register calculated M/N video */
@@ -838,6 +837,9 @@ static int analogix_dp_config_video(struct
analogix_dp_device *dp)
exiting.
With the subject fix:
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Cc: Sonny Rao
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by: Enric Balletbo i Serra
Tested-by: Marek Szyprowski
---
drivers/gpu
this patch,
you can let it stay if it happens to cause conflicts with future
patches. Other than that:
Reviewed-by: Archit Taneja
Thanks,
Archit
#include
#include
@@ -35,6 +36,8 @@
#define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
+static const
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: zain wang
There is a race between AUX CH bring-up and enabling bridge which will
cause link training to fail. To avoid hitting it, don't change psr state
while enabling the bridge.
Reviewed-by: Archit Taneja
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: Yakir Yang
Make sure the request PSR state takes effect in analogix_dp_send_psr_spd()
function, or print the sink PSR error state if we failed to apply the
requested PSR setting.
Reviewed-by: Archit Taneja
Cc: 征增 王
On Monday 12 March 2018 06:53 PM, Sibi S wrote:
From: Archit Taneja
I'm a bit uncertain about using this patch in its current state.
Some reasons below.
Add command broadcast support for DSI 6G v2.0+ controller
on SDM845
Signed-off-by: Sibi S
---
drivers/gpu/drm/msm/dsi/
On Monday 12 March 2018 06:53 PM, Sibi S wrote:
Replace version checks with the helper functions bound to
cfg_handler for DSI v2 and DSI 6G 1.x controllers
With the ops set up for DSI6G 2.x too:
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Sibi S
---
drivers/gpu/drm/msm
broadcast code as a separate patch since it
probably needs to go through more iterations.
The ops approach looks good otherwise.
Thanks,
Archit
static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
- {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, &apq8064_dsi
...
ports {
bridge1: port@0 {
...
};
bridge2: port@1 {
...
};
};
};
Thanks,
Archit
2) register a single bridge with multiple "next bridges", but when the bridge
gets attached I don't see a
ler
instead
of DSI ids so that the implementation become more generic. Thank you for
sharing
your thoughts.
Slightly unrelated: currently, the IS_DUAL_DSI() uses custom qcom
bindings, we should use more generic bindings. I'd posted a RFC for it:
https://lists.freedesktop.org/archives/dri-devel/201
default:
This fixes a long time issue on Amlogic SoCs, is it ok for you ?
Looks good to me. Feel free to queue it to drm-misc-next.
Thanks,
Archit
Thanks,
Neil
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: Philipp Zabel
queued to drm-misc-next after fixing a minor checkpatch
warning.
Thanks,
Archit
regards
Philipp
---
drivers/gpu/drm/drm_of.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
index 4c191c050e7d
_format, 1);
drm_mode_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
The sii902x driver sets the bus_formats in get_modes, but it's a fixed
value and we may as well do it in bridge's attach op.
For the bridge drivers:
Reviewed-by: Archit Taneja
Tha
On Tuesday 20 February 2018 04:44 PM, Archit Taneja wrote:
On Tuesday 20 February 2018 03:59 PM, Thierry Reding wrote:
From: Thierry Reding
DRM_DUMB_VGA_DAC is a user-visible symbol. Selecting it can cause unmet
direct dependencies such as this (on i386, randconfig):
warning
ndencies".
+Linus.
I guess this needs to go in drm-misc-fixes once it is updated to
4.16-rc2.
Thanks,
Archit
Fixes: 49f81d80ab84 ("drm/pl111: Support handling bridge timings")
Reported-by: Randy Dunlap
Cc: Laurent Pinchart
Cc: Archit Taneja
Cc: Eric Anholt
Signed-off-
structure when needed.
Idea was taken from the following commit:
8242ecbd597d ("drm/bridge/synopsys: stop clobbering drvdata")
Reviewed-by: Archit Taneja
Cc: p.za...@pengutronix.de
Cc: narmstr...@baylibre.com
Cc: laurent.pinch...@ideasonboard.com
Cc: h...@rock-chips.com
Cc: he..
reused.
Functions exported here are actually not specific to Synopsys PHYs but
to DWC HDMI controller PHY interface. This means that even if the PHY is
completely custom, i.e. not designed by Synopsys, exported functions can
be useful.
Reviewed-by: Archit Taneja
Reviewed-by: Neil Armstrong
On Thursday 15 February 2018 01:38 AM, Jernej Skrabec wrote:
Allwinner SoCs have dw hdmi controller v1.32a which exhibits same
magenta line issue as i.MX6Q and i.MX6DL. Enable workaround for it.
Tests show that one iteration is enough.
Acked-by: Laurent Pinchart
Reviewed-by: Archit Taneja
Hi Phillipe,
On Saturday 03 February 2018 03:49 AM, Philippe CORNU wrote:
Hi Archit, Andrzej, Laurent & Brian,
What is your opinion regarding this patch? Do you have any advice for
handling hw versions?
Do not hesitate to comment.
The patch looks mostly good to me. One query below.
On 01/31/2018 09:50 PM, Rob Clark wrote:
On Wed, Jan 31, 2018 at 1:40 AM, Archit Taneja wrote:
On 01/29/2018 10:45 PM, Rob Herring wrote:
On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote:
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096).
From 14nm PHY
On 01/29/2018 10:45 PM, Rob Herring wrote:
On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote:
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096).
From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required,
but "dsi_phy_lane" reg
Awesome, thanks.
Reviewed-by: Brian Norris
Queued to drm-misc-next.
Thanks,
Archit
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index
of bytes is returned for the moment.
Signed-off-by: Philippe Cornu
Assuming we're going with the current documented semantics (where we
return # of TX bytes for writes), then:
Reviewed-by: Brian Norris
I believe Archit was suggesting maybe changing that sometime, but that's
no excu
use it in dw dsi :)
Could you get the patch [1] queued on drm-misc-next? I can queue this patch
after it.
Thanks,
Archit
Philippe :-)
[1] https://patchwork.freedesktop.org/patch/200720/
"[PATCH] drm/stm: ltdc: use crtc_mode_fixup to update adjusted_mode clock"
Tested-by: Brian Nor
he 2nd chip"
Maybe the default macros can be a function of the main address?
+ adv->i2c_cec = i2c_new_secondary_device(adv->i2c_main, "cec",
+ ADV7511_REG_CEC_I2C_ADDR_DEFAULT);
Also, I'm a bit unclear on the default address values. For example, previously,
On 01/18/2018 03:25 AM, Laurent Pinchart wrote:
The plane cleanup handler currently calls drm_plane_helper_disable(),
which is a legacy helper function. Replace it with a call to
drm_atomic_helper_shutdown() at removal time.
Reviewed-by: Archit Taneja
Signed-off-by: Laurent Pinchart
Add a section that describes dt-bindings for peripherals that support
MIPI DSI, but have a different bus as the primary control bus, or no
control bus at all. Add an example for a peripheral with a non-DSI
control bus.
Signed-off-by: Archit Taneja
---
v2:
- Mentioned what to do if peripheral has
Add binding info for peripherals that support dual-channel DSI. Add
corresponding optional bindings for DSI host controllers that may
be configured in this mode. Add an example of an I2C controlled
device operating in dual-channel DSI mode.
Signed-off-by: Archit Taneja
---
v2:
- Specify that
eady started using, but didn't have properly documented anywhere.
The second patch proposes bindings for DSI hosts/peripherals that
implement dual-channel DSI.
Changes in v2:
- Incorported Rob's comments.
Archit Taneja (2):
dt-bindings: mipi-dsi: Add info about peripherals with no
address/regulator supply needs.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja
---
Documentation/devicetree/bindings/display/msm/dsi.txt | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt
b
t its rate only after we configure byte_clk.
This is required for the ancestor clocks in the CC to be
configured correctly.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/ms
er.kernel.org
Signed-off-by: Archit Taneja
---
Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt
b/Documentation/devicetree/bindings/display/msm/dsi.tx
"qcom,dsi-host-index" and "qcom,dsi-phy-index" DT props aren't
acceptable and have never been used in any DT files. Remove them.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja
---
Documentation/devicetree/bindings/display/msm/dsi.txt |
The PHY regulator supply names vary across different PHY versions.
Mention explicitly which PHYs require which supplies.
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Signed-off-by: Archit Taneja
---
Documentation/devicetree/bindings/display/msm/dsi.txt | 4
1 file changed, 4 insertions
We try to get the interface clock in dsi_get_config early during DSI's
component bind. Try getting both the "iface" and "iface_clk" clock name
variants so that we are compatible with both new and legacy DT.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi_
This series adds some of the host controller changes needed for SDM845.\
The DT patches in the series do some minor clean ups and add missing
bindings for 14nm DSI PHY (8x96) and new bindings for 10nm PHY.
Archit Taneja (7):
drm/msm/dsi: Use msm_clk_get in dsi_get_config
drm/msm/dsi: Add
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