HI Piotr，
在 2025-06-19 19:54:12，"Piotr Zalewski" 写道：
>Hi Andy
>
>>
>> The root case for the problem is now clear。
>>
>> Most of the registers in VOP need to write the cfd_done register(call
>> vop2_cfg_done)
>> after you have configured the registers. Then, they will take effect only
>> when
From: Andy Yan
Enable the Mini DisplayPort on this board.
Note that ROCKCHIP_VOP2_EP_DP0 is defined as 10 in dt-binding header,
but it will trigger a dtc warning like "graph node unit address error,
expected "a"" if we use it directly after endpoint, so we use "a"
From: Andy Yan
The DP1 is compliant with the DisplayPort Specification
Version 1.4, and share the USBDP combo PHY1 with USB 3.1
HOST1 controller.
Signed-off-by: Andy Yan
---
(no changes since v1)
.../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 30 +++
1 file changed, 30
From: Andy Yan
The RA620 is an active DP to HDMI converter chip, basically
no software is involved to drive it.
Add it to simple bridge to make it can be find by the drm bridge chain.
Signed-off-by: Andy Yan
Reviewed-by: Dmitry Baryshkov
---
(no changes since v3)
Changes in v3:
- First
From: Andy Yan
Add driver extension for Synopsys DesignWare DPTX IP used
on Rockchip RK3588 SoC.
Signed-off-by: Andy Yan
Acked-by: Dmitry Baryshkov
Tested-by: Nicolas Frattaroli
---
Changes in v4:
- Drop unused function
- Add platform_set_drvdata
Changes in v2:
- no include uapi path
From: Andy Yan
The HDMI0(Port next to Headphone Jack) is drived by DP1 on rk3588
via RA620(a dp2hdmi converter).
Add related dt nodes to enable it.
Note: ROCKCHIP_VOP2_EP_DP1 is defined as 11 in dt-binding header,
but it will trigger a dtc warning like "graph node unit address
error, exp
From: Andy Yan
The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX
controller. And this DPTX controller need share a USBDP PHY with
the USB 3.0 OTG controller during operation.
Signed-off-by: Andy Yan
Reviewed-by: Rob Herring (Arm)
---
(no changes since v2)
Changes in v2
From: Andy Yan
RA620 is a DP to HDMI bridge converter from RADXA, which first
found be used on ROCK 5 ITX.
This chip can be used without involving software.
Signed-off-by: Andy Yan
Acked-by: Krzysztof Kozlowski
---
(no changes since v3)
Changes in v3:
- First introduced in this version
From: Andy Yan
The DW DP TX Controller is compliant with the DisplayPort Specification
Version 1.4 with the following features:
* DisplayPort 1.4a
* Main Link: 1/2/4 lanes
* Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
* AUX channel 1Mbps
* Single Stream Transport(SST)
* Multistream
From: Andy Yan
The DP0 is compliant with the DisplayPort Specification
Version 1.4, and share the USBDP combo PHY0 with USB 3.1
HOST0 controller.
Signed-off-by: Andy Yan
---
(no changes since v1)
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 30 +++
1 file changed, 30
From: Andy Yan
There are two DW DPTX based DisplayPort Controller on rk3588 which
are compliant with the DisplayPort Specification Version 1.4 with
the following features:
* DisplayPort 1.4a
* Main Link: 1/2/4 lanes
* Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
* AUX channel 1Mbps
From: Andy Yan
The DSI host has different modes in prepare() and enable() functions,
prepare() is in LP command mode and enable() is in HS video mode.
>From our experience, generally the initialization sequence needs to be
sent in the LP command mode.
Move the setup init function from ena
From: Andy Yan
Add missing drm_display_mode DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC
flags. Those are used by various bridges(e.g. dw-mipi-dsi) in the
pipeline to correctly configure its sync signals polarity.
Tested on rk3568/rk3576/rk3588 EVB.
Signed-off-by: Andy Yan
---
drivers/gpu
ument the UAPI semantics
>- compute scanline pitch from for unknown color modes (Andy, Tomi)
>
>Signed-off-by: Thomas Zimmermann
>Reviewed-by: Tomi Valkeinen
Reviewed-by: Andy Yan
>---
> Documentation/gpu/todo.rst | 27 ++
> drivers/gpu/drm/drm_dumb_buffers.c
From: Andy Yan
Although the datasheet of the panel module describes that it has a
reset pin, in the actual hardware design, we often use an RC circuit
to control the reset, and rarely use GPIO to control the reset. This
is the way it is done on our numerous development boards (such as
RK3568
From: Andy Yan
Although the datasheet of the panel module describes that it has a
reset pin, in the actual hardware design, we often use an RC circuit
to control the reset, and rarely use GPIO to control the reset. This
is the way it is done on our numerous development boards (such as RK3568
the issue to light and ended in a
>null-pointer dereference further down.
>
>As we expect a primary-plane to exist for a video-port, add a check at
>the end of the window-iteration and fail probing if none was found.
>
>Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver&qu
Hi Deiderik and Piotr,
At 2025-06-11 20:26:38, "Diederik de Haas" wrote:
>Hi,
>
>On Wed Jun 11, 2025 at 2:15 PM CEST, Andy Yan wrote:
>> At 2025-06-11 18:56:31, "Diederik de Haas" wrote:
>>>On Wed Jun 11, 2025 at 9:41 AM CEST, Andy Yan wrote:
&g
Hi Diederik,
At 2025-06-11 18:56:31, "Diederik de Haas" wrote:
>Hi Andy,
>
>On Wed Jun 11, 2025 at 9:41 AM CEST, Andy Yan wrote:
>> At 2025-06-10 19:02:11, "Diederik de Haas" wrote:
>>>On Tue Jun 10, 2025 at 11:07 AM CEST, Andy Yan wrote:
>>&g
Hi Diederik，
At 2025-06-10 19:02:11, "Diederik de Haas" wrote:
>Hi Andy,
>
>On Tue Jun 10, 2025 at 11:07 AM CEST, Andy Yan wrote:
>> At 2025-06-09 20:36:41, "Diederik de Haas" wrote:
>>>On Mon Jun 9, 2025 at 11:15 AM CEST, Andy Yan wrote:
>>&g
Hi Diederik,
At 2025-06-08 20:53:37, "Diederik de Haas" wrote:
>Hi Andy,
>
>On Sun Jun 8, 2025 at 2:10 PM CEST, Andy Yan wrote:
>> At 2025-06-08 19:08:50, "Diederik de Haas" wrote:
>>>On Sat Jun 7, 2025 at 5:32 PM CEST, Piotr Zalewski wrote:
Hello，
At 2025-06-08 19:08:50, "Diederik de Haas" wrote:
>Hi Piotr,
>
>On Sat Jun 7, 2025 at 5:32 PM CEST, Piotr Zalewski wrote:
>> On Thursday, June 5th, 2025 at 10:13 PM, Diederik de Haas
>> wrote:
>>> Since kernel 6.14-rc1 I have the problem that visual output is no longer
>>> shown on my P
k you very much for your review.
>On Thursday, 3 April 2025 05:37:31 Central European Summer Time Andy Yan wrote:
>> From: Andy Yan
>>
>> Add driver extension for Synopsys DesignWare DPTX IP used
>> on Rockchip RK3588 SoC.
>>
>> Signed-off-by: An
Hello Dmitry,
在 2025-05-24 15:46:15，"Dmitry Baryshkov" 写道：
>On Wed, May 14, 2025 at 08:15:55PM +0800, Andy Yan wrote:
>> Hello Dmitry，
>>
>> Would it be convenient for you to continue reviewing this patch at your
>> convenience?
>>
Hi,
在 2025-05-22 16:45:08，"Krzysztof Kozlowski" 写道：
>On 16/05/2025 11:58, Heiko Stübner wrote:
>> Am Donnerstag, 15. Mai 2025, 17:54:20 Mitteleuropäische Sommerzeit schrieb
>> Krzysztof Kozlowski:
>>> On 15/05/2025 14:35, long.yunj...@zte.com.cn wrote:
From: Yumeng Fang
In the pr
Hello，
At 2025-05-08 17:11:01, "Daniel Stone" wrote:
>Hi Andy,
>
>On Thu, 8 May 2025 at 11:49, Andy Yan wrote:
>> Let the user know what went wrong in drm_gem_fb_afbc_init
>> failure paths.
>
>Thanks for this, and thanks also for using drm_dbg_kms() to make
Hi Chaoyi，
At 2025-05-07 11:51:48, "Chaoyi Chen" wrote:
>From: Chaoyi Chen
>
>Convert it to drm bridge driver, it will be convenient for us to
>migrate the connector part to the display driver later.
>
>Tested with RK3399 EVB IND board.
>
>Signed-off-by: Chaoyi Chen
>---
> drivers/gpu/drm/rock
Hello Jayesh,
At 2025-05-21 16:15:33, "Andy Yan" wrote:
>
>
>Hello Javesh,
>
>At 2025-05-21 15:32:35, "Jayesh Choudhary" wrote:
>>Now that we have DBANC framework, remove the connector initialisation code
>>as that piece of code is not called i
Hello Javesh,
At 2025-05-21 15:32:35, "Jayesh Choudhary" wrote:
>Now that we have DBANC framework, remove the connector initialisation code
>as that piece of code is not called if DRM_BRIDGE_ATTACH_NO_CONNECTOR flag
>is used. Only TI K3 platforms consume this driver and tidss (their display
>co
This should be one space.
Signed-off-by: Andy Yan
---
include/drm/drm_auth.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_auth.h b/include/drm/drm_auth.h
index 50131383ed81..830386804f91 100644
--- a/include/drm/drm_auth.h
+++ b/include/drm/drm_auth.h
dw_dp_has_sink_count. But there is no response on my patch try to
Pass down connector to drm bridge detect hook[0].
I don't know how to proceed with this patch at the moment.
[0]https://lore.kernel.org/dri-devel/20250321085345.136380-1-andys...@163.com/
Thank you.
At 2025-04-03 11:37:30, "Andy Y
From: Andy Yan
Convert it to drm bridge driver, it will be convenient for us to
migrate the connector part to the display driver later.
Patches that have already been merged in drm-misc-next are dropped.
PATCH 1~8 are some cleanup and refactor.
PATCH 9 converts the curren driver to drm bridge
From: Andy Yan
This function not only configure hardware reset register, but also
do some other configurations. Therefore, it is more appropriate to
name it inno_hdmi_init_hw, which will also facilitate the addition
of other functions to this function in the following patch.
Signed-off-by: Andy
From: Andy Yan
Make use of devm_clk_get_enabled() to replace devm_clk_get() and
clk_prepare_enable(), which will make the cleanup of clk code simpler.
Signed-off-by: Andy Yan
---
Changes in v5:
- Split from PATCH 9/10
drivers/gpu/drm/rockchip/inno_hdmi.c | 50
From: Andy Yan
Convert it to drm bridge driver, it will be convenient for us to
migrate the connector part to the display driver later.
Signed-off-by: Andy Yan
---
Changes in v5:
- Split cleanup code to separate patch
- Switch to devm_drm_bridge_alloc() API
Changes in v4:
- Do not store
From: Andy Yan
Putting these scattered initialization code together is helpful
for the following migration to the DRM bridge driver mode.
Signed-off-by: Andy Yan
---
Changes in v5:
- Split from PATCH 9/10
drivers/gpu/drm/rockchip/inno_hdmi.c | 30 ++--
1 file
From: Andy Yan
usleep_range is preferred over udelay.
Signed-off-by: Andy Yan
---
Changes in v5:
- Split from PATCH 9/10
drivers/gpu/drm/rockchip/inno_hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c
b/drivers/gpu/drm
From: Andy Yan
Switch from i2c_add_adapter() to resource managed
devm_i2c_add_adapter(), which will make the cleanup code more simpler.
Signed-off-by: Andy Yan
---
Changes in v5:
- Split from PATCH 9/10
drivers/gpu/drm/rockchip/inno_hdmi.c | 8 ++--
1 file changed, 2 insertions(+), 6
From: Andy Yan
Remove unnecessary parentheses to make checkpatch happy.
Signed-off-by: Andy Yan
---
Changes in v5:
- Split from PATCH 9/10
drivers/gpu/drm/rockchip/inno_hdmi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c
b
From: Andy Yan
1. Prefer using the BIT macro
2. Macro argument 'n' as '(n)' to avoid precedence issues
3. Add a blank line after enum declarations
Signed-off-by: Andy Yan
---
Changes in v5:
- Split from patch 9/10
drivers/gpu/drm/rockchip/inno_hdmi.c | 214 ++
From: Andy Yan
Since this register definition is only use in one single c
file, there is no need to put it in a separate header.
Signed-off-by: Andy Yan
---
Changes in v5:
- Split from patch 9/10
drivers/gpu/drm/rockchip/inno_hdmi.c | 343 +-
drivers/gpu/drm
From: Andy Yan
Add entry for Innosilicon hdmi bridge library
Signed-off-by: Andy Yan
---
Changes in v5:
- First included in this version
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 81b81cc68ca24..3718e570b4739 100644
--- a
From: Andy Yan
In the function drm_gem_fb_init_with_funcs, the framebuffer (fb)
and its corresponding object ID have already been registered.
So we need to cleanup the drm framebuffer if the subsequent
execution of drm_gem_fb_afbc_init fails.
Directly call drm_framebuffer_put to ensure that
Hi Dmitry,
Thanks for you review.
在 2025-05-05 00:16:35，"Dmitry Baryshkov" 写道：
>On Sat, May 03, 2025 at 04:42:04PM +0200, Heiko Stübner wrote:
>> Am Dienstag, 22. April 2025, 09:04:39 Mitteleuropäische Sommerzeit schrieb
>> Andy Yan:
>> > From: Andy Yan
&g
Let the user know what went wrong in drm_gem_fb_afbc_init
failure paths.
Signed-off-by: Andy Yan
---
drivers/gpu/drm/drm_gem_framebuffer_helper.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c
b/drivers/gpu/drm
Ping..
At 2025-04-22 15:59:27, "Andy Yan" wrote:
>
>Hi all,
>
>At 2025-03-21 17:48:04, "Maxime Ripard" wrote:
>>On Fri, Mar 21, 2025 at 04:53:38PM +0800, Andy Yan wrote:
>>> From: Andy Yan
>>>
>>> In some application s
if (!C)
> -return ERR_PTR(-ENOMEM);
> +C = devm_drm_bridge_alloc(DEV, T, BR, FUNCS);
> +if (IS_ERR(C))
> + return PTR_ERR(C);
> )
> ...
> -C->BR.funcs = FUNCS;
>
>Signed-off-by: Luca Ceresoli
>
>---
>
>Cc: Adam Ford
>Cc: Adrien Grassein
Hi,
At 2025-04-25 02:59:10, "Luca Ceresoli" wrote:
>This is the new API for allocating DRM bridges.
>
>Signed-off-by: Luca Ceresoli
Reviewed-by: Andy Yan
>
>---
>
>Cc: "Uwe Kleine-König"
>Cc: Andy Yan
>Cc: Dmitry Baryshkov
>Cc: Jani
From: Andy Yan
Convert it to drm bridge driver, it will be convenient for us to
migrate the connector part to the display driver later.
Note: I don't have the hardware to test this driver, so for now
I can only do the compilation test.
Signed-off-by: Andy Yan
---
drivers/gpu/drm/roc
ALOGIX_DP [=y]
>>
>> Rockchip platforms all depend on OF anyway, so add the dependency here
>> for compile testing.
>>
>> Fixes: d7b4936b2bc0 ("drm/rockchip: analogix_dp: Add support to get panel
>> from the DP AUX bus")
>> Signed-off-by: Arnd Berg
Hi all,
At 2025-03-21 17:48:04, "Maxime Ripard" wrote:
>On Fri, Mar 21, 2025 at 04:53:38PM +0800, Andy Yan wrote:
>> From: Andy Yan
>>
>> In some application scenarios, we hope to get the corresponding
>> connector when the bridge's detect hook is inv
From: Andy Yan
Use dev_err_probe simplify the error handle.
Signed-off-by: Andy Yan
---
(no changes since v2)
Changes in v2:
- First included in this series
drivers/gpu/drm/rockchip/inno_hdmi.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a
From: Andy Yan
HDMI on RK3036 use GRF control the HSYNC/VSYNC polarity, but this part
is missing when it first landing upstream.
Document that it is mandatory for RK3036 HDMI.
Signed-off-by: Andy Yan
Reviewed-by: Krzysztof Kozlowski
---
(no changes since v2)
Changes in v2:
- First
From: Andy Yan
Convert it to drm bridge driver, it will be convenient for us to
migrate the connector part to the display driver later.
Signed-off-by: Andy Yan
---
Changes in v4:
- Do not store colorimetry within inno_hdmi struct
Changes in v3:
- First included in v3
drivers/gpu/drm
From: Andy Yan
When preparing to convert the current inno hdmi driver into a
bridge driver, I found that there are several issues currently
existing with it:
1. When the system starts up, the first time it reads the EDID, it
will fail. This is because RK3036 HDMI DDC bus requires it's
From: Andy Yan
The RK3036 HDMI DDC bus requires it's PHY's reference clock to be
enabled first before normal DDC communication can be carried out.
Signed-off-by: Andy Yan
---
(no changes since v1)
arch/arm/boot/dts/rockchip/rk3036.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2
From: Andy Yan
The HSYNC/VSYNC polarity of rk3036 HDMI are controlled by GRF.
Without the polarity configuration in GRF, it can be observed
from the HDMI protocol analyzer that the H/V front/back timing
output by RK3036 HDMI are currently not in line with the specifications.
Signed-off-by: Andy
From: Andy Yan
This reverts commit 1580ccb6ed9dc76b8ff3e2d8912e8215c8b0fa6d.
The HSYNC/VSYNC polarity of rk3036 HDMI are controlled by GRF.
Without the polarity configuration in GRF, it can be observed from
the HDMI protocol analyzer that the H/V front/back timing output
by RK3036 HDMI are
From: Andy Yan
The RK3036 HDMI DDC bus requires it's PHY's reference clock to be enabled
first before normal DDC communication can be carried out.
Therefore, both RK3036 and RK3128 HDMI require two identical clocks.
Signed-off-by: Andy Yan
Reviewed-by: Rob Herring (Arm)
---
(
From: Andy Yan
The all video ports of rk3568/rk3588 share the same OVL_LAYER_SEL
and OVL_PORT_SEL registers, and the configuration of these two registers
can be set to take effect when the vsync signal arrives at a certain Video
Port.
If two threads for two display output choose to update these
switching works correctly in sway
>
>Signed-off-by: Konstantin Shabanov
>Cc: Daniel Stone
>Cc: Andy Yan
>Reported-by: Dan Callaghan
>Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7968
>
>[1]:
>https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Data
Hi
At 2025-04-18 17:43:19, "Daniel Stone" wrote:
>Hi Andy,
>
>On Fri, 18 Apr 2025 at 01:16, Andy Yan wrote:
>> I prefer the V1 version PATCH[0]. This is because we do not deal with
>> hardware-related
>> differences at this level. It involves a VOP-
Hi,
在 2025-04-15 15:51:31，"Thomas Zimmermann" 写道：
>Hi
>
>Am 15.04.25 um 09:15 schrieb Andy Yan:
>> Hi Thomas，
>>
>> 在 2025-04-15 14:54:21，"Thomas Zimmermann" 写道：
>>> Hi
>>>
>>> Am 15.04.25 um 06:00 schrieb Andy Yan:
&g
Hi Thomas，
在 2025-04-15 14:54:21，"Thomas Zimmermann" 写道：
>Hi
>
>Am 15.04.25 um 06:00 schrieb Andy Yan:
>>
>> Hi Thomas，
>>
>> At 2025-04-14 21:48:12, "Thomas Zimmermann" wrote:
>>> Instead of testing import_attach for imported GEM
;to make import_attach optional.
>
>Signed-off-by: Thomas Zimmermann
>Cc: Sandy Huang
>Cc: "Heiko Stübner"
>Cc: Andy Yan
>---
> drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gp
Hi Konstantin，
the Subject should be: drm/rockchip:
At 2025-04-14 17:53:31, "Konstantin Shabanov" wrote:
>As it isn't supported by hardware. At least, RK3399 doesn't support
>it. From the datasheet[1]
>("1.2.10 Video IN/OUT", "Display Interface", p. 17):
>
> Support AFBC function
From: Andy Yan
It is not recommended for drivers to include UAPI header
directly.
Signed-off-by: Andy Yan
Reviewed-by: Heiko Stuebner
---
Changes in v2:
- Collect R-b from Heiko.
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
Hello Heiko,
Could you take this series ? They have already got the necessary R-B and
Ack.
I think Damon still has some patches for connector decoupling. With this series
have been merged earlier.
His new patches can have fewer dependencies.
At 2025-03-10 18:41:01, "Damon Ding" wrote
Hi Alex，
At 2025-04-03 01:24:22, "Alex Bee" wrote:
>
>Hi Andy,
>
>> From: Andy Yan
>>
>> Convert it to drm bridge driver, it will be convenient for us to
>> migrate the connector part to the display driver later.
>>
>> Signed-off-by
gt; > > On Fri, Mar 14, 2025 at 08:45:17AM +0100, Maxime Ripard wrote:
>> > > > > > > On Fri, Mar 14, 2025 at 07:52:35AM +0200, Dmitry Baryshkov wrote:
>> > > > > > > > On Fri, Mar 14, 2025 at 08:50:29AM +0800, Andy Yan wrote:
>> > >
From: Andy Yan
The DP0 is compliant with the DisplayPort Specification
Version 1.4, and share the USBDP combo PHY0 with USB 3.1
HOST0 controller.
Signed-off-by: Andy Yan
---
(no changes since v1)
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 30 +++
1 file changed, 30
Gentle ping..
At 2025-03-27 20:54:37, "Dmitry Baryshkov"
wrote:
>On 27/03/2025 14:39, Andy Yan wrote:
>>
>> Hello Dmitry,
>> Could you take this series? If so, merging it earlier can avoid future
>> conflicts from other patches.
>> Besi
Hi Maxime，
At 2025-03-21 17:48:04, "Maxime Ripard" wrote:
>On Fri, Mar 21, 2025 at 04:53:38PM +0800, Andy Yan wrote:
>> From: Andy Yan
>>
>> In some application scenarios, we hope to get the corresponding
>> connector when the bridge's detect hook is
From: Andy Yan
The RK3036 HDMI DDC bus requires it's PHY's reference clock to be enabled
first before normal DDC communication can be carried out.
Therefore, both RK3036 and RK3128 HDMI require two identical clocks.
Signed-off-by: Andy Yan
Reviewed-by: Rob Herring (Arm)
---
(
From: Andy Yan
The HDMI0(Port next to Headphone Jack) is drived by DP1 on rk3588
via RA620(a dp2hdmi converter).
Add related dt nodes to enable it.
Note: ROCKCHIP_VOP2_EP_DP1 is defined as 11 in dt-binding header,
but it will trigger a dtc warning like "graph node unit address
error, exp
From: Andy Yan
There are two DW DPTX based DisplayPort Controller on rk3588 which
are compliant with the DisplayPort Specification Version 1.4 with
the following features:
* DisplayPort 1.4a
* Main Link: 1/2/4 lanes
* Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
* AUX channel 1Mbps
From: Andy Yan
The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX
controller. And this DPTX controller need share a USBDP PHY with
the USB 3.0 OTG controller during operation.
Signed-off-by: Andy Yan
Reviewed-by: Rob Herring (Arm)
---
(no changes since v2)
Changes in v2
From: Andy Yan
The RA620 is an active DP to HDMI converter chip, basically
no software is involved to drive it.
Add it to simple bridge to make it can be find by the drm bridge chain.
Signed-off-by: Andy Yan
---
Changes in v3:
- First introduced in this version.
drivers/gpu/drm/bridge
From: Andy Yan
Enable the Mini DisplayPort on this board.
Note that ROCKCHIP_VOP2_EP_DP0 is defined as 10 in dt-binding header,
but it will trigger a dtc warning like "graph node unit address error,
expected "a"" if we use it directly after endpoint, so we use "a"
From: Andy Yan
The DW DP TX Controller is compliant with the DisplayPort Specification
Version 1.4 with the following features:
* DisplayPort 1.4a
* Main Link: 1/2/4 lanes
* Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
* AUX channel 1Mbps
* Single Stream Transport(SST)
* Multistream
From: Andy Yan
RA620 is a DP to HDMI bridge converter from RADXA, which first
found be used on ROCK 5 ITX.
This chip can be used without involving software.
Signed-off-by: Andy Yan
---
Changes in v3:
- First introduced in this version.
.../devicetree/bindings/display/bridge/simple
From: Andy Yan
The DP1 is compliant with the DisplayPort Specification
Version 1.4, and share the USBDP combo PHY1 with USB 3.1
HOST1 controller.
Signed-off-by: Andy Yan
---
(no changes since v1)
.../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 30 +++
1 file changed, 30
From: Andy Yan
Add driver extension for Synopsys DesignWare DPTX IP used
on Rockchip RK3588 SoC.
Signed-off-by: Andy Yan
Acked-by: Dmitry Baryshkov
---
(no changes since v2)
Changes in v2:
- no include uapi path
- switch to drmm_encoder_init
drivers/gpu/drm/rockchip/Kconfig
Gentle ping..
At 2025-03-14 15:57:47, "Andy Yan" wrote:
>From: Andy Yan
>
>It is not recommended for drivers to include UAPI header
>directly.
>
>Signed-off-by: Andy Yan
>---
>
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ++--
> 1 file changed,
From: Andy Yan
HDMI on RK3036 use GRF control the HSYNC/VSYNC polarity, but this part
is missing when it first landing upstream.
Document that it is mandatory for RK3036 HDMI.
Signed-off-by: Andy Yan
---
(no changes since v2)
Changes in v2:
- First included in v2
.../bindings/display
From: Andy Yan
Convert it to drm bridge driver, it will be convenient for us to
migrate the connector part to the display driver later.
Signed-off-by: Andy Yan
---
Changes in v3:
- First included in v3
- Link to V2:
https://lore.kernel.org/dri-devel/20250325132944.17-1-andys...@163.com
From: Andy Yan
This reverts commit 1580ccb6ed9dc76b8ff3e2d8912e8215c8b0fa6d.
The HSYNC/VSYNC polarity of rk3036 HDMI are controlled by GRF.
Without the polarity configuration in GRF, it can be observed from
the HDMI protocol analyzer that the H/V front/back timing output
by RK3036 HDMI are
From: Andy Yan
The RK3036 HDMI DDC bus requires it's PHY's reference clock to be
enabled first before normal DDC communication can be carried out.
Signed-off-by: Andy Yan
---
(no changes since v1)
arch/arm/boot/dts/rockchip/rk3036.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2
From: Andy Yan
When preparing to convert the current inno hdmi driver into a
bridge driver, I found that there are several issues currently
existing with it:
1. When the system starts up, the first time it reads the EDID, it
will fail. This is because RK3036 HDMI DDC bus requires it's
From: Andy Yan
Use dev_err_probe simplify the error handle.
Signed-off-by: Andy Yan
---
(no changes since v2)
Changes in v2:
- First included in this series
drivers/gpu/drm/rockchip/inno_hdmi.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a
From: Andy Yan
The HSYNC/VSYNC polarity of rk3036 HDMI are controlled by GRF.
Without the polarity configuration in GRF, it can be observed
from the HDMI protocol analyzer that the H/V front/back timing
output by RK3036 HDMI are currently not in line with the specifications.
Signed-off-by: Andy
From: Andy Yan
In some application scenarios, we hope to get the corresponding
connector when the bridge's detect hook is invoked.
In most cases, we can get the connector by drm_atomic_get_connector_for_encoder
if the encoder attached to the bridge is enabled, however there will
still be
Hello Dmitry,
Could you take this series? If so, merging it earlier can avoid future
conflicts from other patches.
Besides, I can update my DP driver based on drm-misc-next.
At 2025-03-18 14:34:35, "Andy Yan" wrote:
>From: Andy Yan
>
>The helper functions drm_dp_link
From: Andy Yan
In some application scenarios, we hope to get the corresponding
connector when the bridge's detect hook is invoked.
For example, we may want to call drm_dp_read_sink_count_cap(which needs
a drm_connector) at the dp deteck hook, intel_dp and nouveau_dp do this
at it's c
Hi
At 2025-03-26 15:59:25, "Krzysztof Kozlowski" wrote:
>On Tue, Mar 25, 2025 at 09:29:36PM +0800, Andy Yan wrote:
>> From: Andy Yan
>>
>> HDMI on RK3036 use GRF control the HSYNC/VSYNC polarity, but this part
>> is missing when it first landing upstream.
From: Andy Yan
The RK3036 HDMI DDC bus requires it's PHY's reference clock to be enabled
first before normal DDC communication can be carried out.
Therefore, both RK3036 and RK3128 HDMI require two identical clocks.
Signed-off-by: Andy Yan
Reviewed-by: Rob Herring (Arm)
---
(
From: Andy Yan
HDMI on RK3036 use GRF control the HSYNC/VSYNC polarity, but this part
is missing when it first landing upstream.
Document that it is mandatory for RK3036 HDMI.
Signed-off-by: Andy Yan
---
(no changes since v1)
.../bindings/display/rockchip/rockchip,inno-hdmi.yaml| 9
From: Andy Yan
When preparing to convert the current inno hdmi driver into a bridge driver,
I found that there are several issues currently existing with it:
1. When the system starts up, the first time it reads the EDID, it will
fail.
This is because RK3036 HDMI DDC bus requires it&#
From: Andy Yan
The HSYNC/VSYNC polarity of rk3036 HDMI are controlled by GRF.
Without the polarity configuration in GRF, it can be observed
from the HDMI protocol analyzer that the H/V front/back timing
output by RK3036 HDMI are currently not in line with the specifications.
Signed-off-by: Andy
From: Andy Yan
The RK3036 HDMI DDC bus requires it's PHY's reference clock to be
enabled first before normal DDC communication can be carried out.
Signed-off-by: Andy Yan
---
(no changes since v1)
arch/arm/boot/dts/rockchip/rk3036.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2
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