Hi,
On Tue, May 20, 2025 at 06:01:12PM +0300, Joonas Lahtinen wrote:
> Quoting Krzysztof Niemiec (2025-05-19 18:34:14)
> > This series introduces a way for applications to read local memory
> > information via files in the sysfs. So far the only way to do this was
> > via i915_query ioctl. This is
callers such as sync_file, and our internal code paths, we can drop the
> similar protection from i915_fence_get_timeline_name().
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Tvrtko,
On Thu, May 15, 2025 at 10:50:00AM +0100, Tvrtko Ursulin wrote:
> Access the dma-fence internals via the previously added helpers.
>
> Signed-off-by: Tvrtko Ursulin
> Reviewed-by: Christian König
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Danila,
On Wed, Apr 23, 2025 at 12:31:24AM +0300, Danila Tikhonov wrote:
> Add the SM7150 CCI device string compatible.
>
> Signed-off-by: Danila Tikhonov
Acked-by: Andi Shyti
Thanks,
Andi
Hi Kees,
On Fri, Apr 25, 2025 at 11:13:58PM -0700, Kees Cook wrote:
> In preparation for making the kmalloc family of allocators type aware,
> we need to make sure that the returned type from the allocation matches
> the type of the variable being assigned. (Before, the allocator would
> always re
truct i915_wa *". The returned type, while
> > > technically matching, will be const qualified. As there is no general
> > > way to remove const qualifiers, adjust the allocation type to match
> > > the assignment.
> > >
> > > Signed-off-by: Kees Cook
be used for determining engine validity.
Signed-off-by: Andi Shyti
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 28 +--
drivers/gpu/drm/i915/gt/intel_engine_user.c | 9 --
2 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem
er into
> chunks of 8 messages internally and so interrupts are not expected for
> the first 7 message completions, only the last message triggers
> an interrupt, indicating the completion of 8 messages.
>
> This BEI mechanism enhances overall transfer efficiency.
>
> Signed-
Hi Janusz,
> Janusz Krzysztofik (3):
> drm/i915: Downgrade device register error if injected
> drm/i915: Fix PXP cleanup missing from probe error rewind
> drm/i915: Fix harmful driver register/unregister asymmetry
merged to drm-intel-next.
Thanks,
Andi
Hi,
On Fri, Mar 28, 2025 at 12:26:29AM +0100, Andi Shyti wrote:
> Replace multi-line SPDX license headers with single-line
> equivalents (// SPDX-License-Identifier: MIT or /* ... */ for
> headers), as preferred by current kernel coding style.
>
> Signed-off-by: Andi Shyti
merg
Replace multi-line SPDX license headers with single-line
equivalents (// SPDX-License-Identifier: MIT or /* ... */ for
headers), as preferred by current kernel coding style.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_busy.c | 3 +--
drivers/gpu/drm/i915/gem
On Thu, Mar 27, 2025 at 12:42:50PM +0200, Jani Nikula wrote:
> On Thu, 27 Mar 2025, Andi Shyti wrote:
> > From: Andi Shyti
> >
> > Some GPUs, like DG2, can host more than one CCS engine. Some
> > workarounds or enablements need to happen only once for all the
> &
From: Andi Shyti
Replace checks for I915_ENGINE_FIRST_RENDER_COMPUTE combined
with CCS_MASK() with the FIRST_CCS() helper. This improves
readability and ensures that certain CCS-specific actions, such
as enabling GEN12_RCU_MODE and calling xehp_enable_ccs_engines(),
are performed only once, on
From: Andi Shyti
All platforms supported by i915 have at least one RCS engine,
so there's no need to explicitly check for RCS or CCS presence.
Remove the redundant check and move the associated functions
to a more appropriate location in the code.
Signed-off-by: Andi Shyti
---
driver
to be moved earlier in
the file to avoid the need for a forward declaration.
Suggested-by: Arshad Mehmood
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 58 +++--
1 file changed, 30 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i9
From: Andi Shyti
The I915_ENGINE_FIRST_RENDER_COMPUTE flag is no longer used.
Its purpose has been replaced by the FIRST_CCS() helper, which
determines the first render or compute engine as needed.
Remove the flag definition and its assignment from
intel_engine_setup().
Suggested-by: Lucas De
checking for
FIRST_RENDER_COMPUTE, but move the logic to the CCS engine
section.
- Define the FIRST_CCS flag which checks for the CCS engine
with the lowest istance number.
- Remove the I915_ENGINE_FIRST_RENDER_COMPUTE flag and use
FIRST_CCS() instead for everyone using it.
Andi Shyti (6):
drm/
From: Andi Shyti
Enable the CCS engine when the first CCS is encountered in the
execlist setup, instead of checking for the
I915_ENGINE_FIRST_RENDER_COMPUTE flag.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Andi Shyti
Some GPUs, like DG2, can host more than one CCS engine. Some
workarounds or enablements need to happen only once for all the
engines in the GT—for example, on the engine with the lowest
instance.
The FIRST_CCS() helper first checks if the engine is a Compute
engine, and then
Hi Lucas,
> > > > @@ -2897,7 +2897,9 @@ engine_init_workarounds(struct intel_engine_cs
> > > > *engine, struct i915_wa_list *wal
> > > > */
> > > > if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) {
> > > > general_render_compute_wa_init(engine, wal);
> > > >
On Tue, Mar 25, 2025 at 01:57:42PM +0100, Chris Wilson wrote:
> Quoting Andi Shyti (2025-03-25 13:01:37)
> > When generating workarounds for the CCS engine, specifically for
> > setting the CCS mode related to compute load balancing, the
> > function 'ccs_engine_wa_mod
ute before applying
the workaround to avoid redundant programming.
Suggested-by: Arshad Mehmood
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/d
Hi Joonas,
thanks a lot for your reply!
On Tue, Mar 25, 2025 at 10:24:42AM +0200, Joonas Lahtinen wrote:
> Quoting Andi Shyti (2025-03-24 15:29:36)
> > Back in v3, this patch series was turned down due to community
> > policies regarding i915 GEM development. Since then, I ha
To support upcoming patches, we need to store the current mask
for active CCS engines.
Active engines refer to those exposed to userspace via the UABI
engine list.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 41 +++--
drivers/gpu/drm/i915/gt
when they are marked as RB_EMPTY.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.h| 12 +
drivers/gpu/drm/i915/gt/selftest_context.c| 6 +--
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 4 +-
.../drm/i915/gt/selftest_engine_heartbeat.c | 6 +--
drivers/gpu
e user can set the CCS mode to 1, 2, or 4,
depending on the desired number of exposed engines and the
required load balancing.
The interface will return -EBUSY if other clients are connected
to i915, or -EINVAL if an invalid value is set.
Signed-off-by: Andi Shyti
---
drivers/gpu/d
ure
successful compilation and maintain bisectability. This
annotation will be removed in subsequent commits.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 128
1 file changed, 128 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mod
In preparation for upcoming patches, we need the ability to
create and remove individual sysfs files. To facilitate this,
extract from the intel_engines_add_sysfs() function the creation
of individual files.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/sysfs_engines.c | 75
user whims.
To ensure thread safety and prevent race conditions, we need to
protect the engine list with a mutex, thereby serializing access
to it.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 3 +++
drivers/gpu/drm/i915/gt/intel_engine_user.c | 7
Upcoming commits will need to access engine-related kobjects to
enable the creation and destruction of sysfs interfaces at
runtime.
For this, store the "engine" directory (i915->sysfs_engine), the
engine files (gt->kobj), and the default data
(gt->kobj_defaults).
Signed
Implement a sysfs interface to show the number of available CCS
slices. The displayed number does not take into account the CCS
balancing mode.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 21 +
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 1
Following the decision to manage CCS engine creation within UABI
engines, the "cslices" variable in the "ccs" structure in the
"gt" is no longer needed. Remove it is now redundant.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c |
r.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 23 -
drivers/gpu/drm/i915/gt/intel_engine_user.c | 17 ---
2 files changed, 14 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/d
For the upcoming changes we need a cleaner way to build the list
of uabi engines.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 29 -
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm
of engines generated.
No functional changes intended.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 16 +++-
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_type
nal changes are intended yet, as no mode higher than
'0' is currently being set.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 85 +
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +-
2 files changed, 72 insertions(+), 15 deletions(-)
en using a
register value that only enables a single CCS engine, typically
with an ID of '0'.
However, in upcoming patches, we will be utilizing multiple
engines, and it's crucial that we write the new value directly
without any masking.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i9
ly different
approach to adding and removing engines. in v1 physical engines
were directly added and removed, along with the memory allocated
to them, each time the user changed the CCS mode (from the
previous cover letter).
Andi Shyti (15):
drm/i915/gt: Avoid using masked workaround for CCS_MODE
+841,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
> pci_device_id *ent)
> if (ret)
> goto out_cleanup_gem;
>
> - i915_driver_register(i915);
> + ret = i915_driver_register(i915);
> + if (ret)
> + goto out_cleanup_gem;
looks good!
Reviewed-by: Andi Shyti
Thanks,
Andi
...
on path.
>
> Fix it.
>
> Cc: Alan Previn
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Janusz Krzysztofik
Reviewed-by: Andi Shyti
Thanks,
Andi
gt; Signed-off-by: Janusz Krzysztofik
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Yuichiro,
On Mon, Feb 24, 2025 at 05:56:37PM +0900, Yuichiro Tsuji wrote:
> Fix typo in a comment.
>
> explaination -> explanation
>
> Signed-off-by: Yuichiro Tsuji
reviewed and merged, thanks.
Andi
Hi Asbjorn,
On Sat, Jun 29, 2024 at 06:25:06PM +, Asbjørn Sloth Tønnesen wrote:
> Implement i915_gem_vmap_object() and i915_gem_vunmap_object(),
> based on i915_gem_dmabuf_vmap() and i915_gem_dmabuf_vunmap().
>
> This enables a drm_client to use drm_client_buffer_vmap() and
> drm_client_buffe
Hi Nitin,
On Wed, Feb 26, 2025 at 09:25:34PM +0530, Nitin Gote wrote:
> Give the scheduler a chance to breath by calling cond_resched()
> as some of the loops may take some time on old machines (like apl/bsw/pnv),
> and so catch the attention of the watchdogs.
>
> Closes: https://gitlab.freedeskt
improved safety.
Signed-off-by: Andi Shyti
Reviewed-by: Krzysztof Karas
---
Cc: Nitin Gote
v1 -> v2:
- replaced kmap with the _local version also in the
intel_ggtt_fencing.c file. (Thanks Nitin)
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++--
drivers/gpu/drm/i915/gt/shmem_util
Hi Krzysztof,
On Thu, Jan 16, 2025 at 10:40:46AM +, Krzysztof Karas wrote:
> spin_lock/unlock() functions used in interrupt contexts could
> result in a deadlock, as seen in GitLab issue #13399:
> https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13399,
I moved this link in the tag sect
Hi Krzysztof,
On Wed, Feb 12, 2025 at 12:50:17PM +0100, Krzysztof Niemiec wrote:
> On 2025-02-10 at 14:01:19 GMT, Andi Shyti wrote:
> > On Thu, Feb 06, 2025 at 07:07:38PM +0100, Janusz Krzysztofik wrote:
> > > We return immediately from i915_driver_register() if drm_dev_regi
Hi Janusz,
On Tue, Feb 11, 2025 at 01:12:37PM +0100, Janusz Krzysztofik wrote:
> On Monday, 10 February 2025 14:01:19 CET Andi Shyti wrote:
> > On Thu, Feb 06, 2025 at 07:07:38PM +0100, Janusz Krzysztofik wrote:
> > > We return immediately from i915_driver_register() i
-off-by: Thomas Weißschuh
Reviewed-by: Andi Shyti
Thanks,
Andi
-off-by: Thomas Weißschuh
Reviewed-by: Andi Shyti
Andi
-off-by: Thomas Weißschuh
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Janusz,
On Thu, Feb 06, 2025 at 07:07:38PM +0100, Janusz Krzysztofik wrote:
> We return immediately from i915_driver_register() if drm_dev_register()
> fails, skipping remaining registration steps. However, the _unregister()
> counterpart called at device remove knows nothing about that skip a
> > - if (!folio)
> > + if (IS_ERR(folio))
>
> I don't see this patch yet in -next yet (and of course not in
> drm-tip), which branch is it based on?
To be precise, not this patch, but the patch(*) that this is fixing :-)
Andi
(*) "drm/i915/gem: Convert __shmem_writeback() t
Hi Dan,
On Thu, Feb 06, 2025 at 11:17:02AM +0300, Dan Carpenter wrote:
> The filemap_lock_folio() function doesn't return NULL, it returns error
> pointers.
>
> Fixes: 25dd342f0cc8 ("drm/i915/gem: convert __shmem_writeback() to folios")
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/i91
Hi Krzysztof,
On Thu, Jan 30, 2025 at 09:19:31AM +, Krzysztof Karas wrote:
> There is an error path in igt_ppgtt_alloc(), which leads
> to ww object being passed down to i915_gem_ww_ctx_fini() without
> initialization. Correct that by only putting ppgtt->vm and
> returning early.
>
> Fixes: 4
folio = filemap_lock_folio(mapping, i);
> - if (!folio)
> + if (IS_ERR(folio))
ops! Thanks, Dan
Reviewed-by: Andi Shyti
Andi
Hi,
> > Please, next time, do not remove the mailing and the other folks
> > you cc'ed.
> >
> > I'm adding back the mailing list and Daniele who has commented
> > before.
>
> Thanks, I also found my previous response click on "reply", not the "reply
> all".
no worries, happens :-)
> > > > > Cl
t address the four different fixes?
> Sure, will split it in next rev.
First of all we need to understand if those Fixes are really
needed or not. Daniele in his review has pointed out that...
> > >
> >
> > No blank lines in the tag section, please.
> >
page
> flag bit with PG_readahead.
>
> Signed-off-by: Kirill A. Shutemov
> Acked-by: David Hildenbrand
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Kirill,
On Thu, Jan 30, 2025 at 12:00:40PM +0200, Kirill A. Shutemov wrote:
> Use folios instead of pages.
>
> This is preparation for removing PG_reclaim.
>
> Signed-off-by: Kirill A. Shutemov
> Acked-by: David Hildenbrand
looks good:
Reviewed-by: Andi Shyti
Thanks,
Andi
)
Cc: # v4.10+
Could you please split this patch in the four different patches
that address the four different fixes?
>
No blank lines in the tag section, please.
> Signed-off-by: Zhanjun Dong
>
> ---
> Cc: Alan Previn
> Cc: Daniele Ceraolo Spurio
> Cc: Rodrigo Vivi
improved safety.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/shmem_utils.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c
b/drivers/gpu/drm/i915/gt/shmem_utils.c
index bb696b29ee2c..365c4b8b04f4 100644
--- a/drivers/gpu
Hi,
this patch has been hanging here for a while, can we please have
someone from DMA and Qualcomm look at it?
Thanks,
Andi
On Tue, Dec 17, 2024 at 10:34:22PM +0530, Jyothi Kumar Seerapu wrote:
> The I2C driver gets an interrupt upon transfer completion.
> When handling multiple messages in a si
Hi Carlos,
On Mon, Nov 25, 2024 at 10:29:09PM +0800, carlos.s...@nxp.com wrote:
> From: Carlos Song
>
> Add eDMA mode support for LPI2C.
>
> There are some differences between TX DMA mode and RX DMA mode.
> LPI2C MTDR register is Controller Transmit Data Register.
> When lpi2c send data, it is
Hi Janusz,
> > > > > > +
> > > > > > cond_resched();
> > > > > >
> > > > > > - if (intel_gt_wait_for_idle(gt, HZ * 3) == -ETIME) {
> > > > > > + if (intel_gt_wait_for_idle(gt, HZ * timeout_ms / 500)
> > > > > > == -ETIME) {
> > > > >
> > > > > where is this 500
from a single failing test case. Let
> me verify if that works for the linked case.
As we agreed offline, I'm going to add this comment you suggested
to your change as a justification to the "/ 500":
/* 2x longest preempt timeout, experimentally determined */
With this:
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Janusz,
...
> > > +
> > > cond_resched();
> > >
> > > - if (intel_gt_wait_for_idle(gt, HZ * 3) == -ETIME) {
> > > + if (intel_gt_wait_for_idle(gt, HZ * timeout_ms / 500) == -
> ETIME) {
> >
> > where is this 500 coming from?
>
> / 1000 would convert it to seconds
Hi Janusz,
...
> for_each_gt(gt, i915, i) {
> + struct intel_engine_cs *engine;
> + unsigned long timeout_ms = 0;
> + unsigned int id;
> +
> if (intel_gt_is_wedged(gt))
> ret = -EIO;
>
> + for_each_engine(
Hi Jani,
On Thu, Dec 05, 2024 at 11:49:35AM +0200, Jani Nikula wrote:
> Use the drm_printer based printer to get the device specific printing of
> the hex dump, and avoid the manual loglevel hacking.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Andi Shyti
Thanks,
Andi
8 *buf, size_t len)
> -{
> - if (!drm_debug_enabled(DRM_UT_KMS))
> - return;
We lose this check now, anyway,
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Jani,
On Thu, Dec 05, 2024 at 11:49:33AM +0200, Jani Nikula wrote:
> Add a helper to print a hex dump to a struct drm_printer. There's no
> fancy formatting stuff, just 16 space-separated bytes per line, with an
> optional prefix.
>
> Signed-off-by: Jani Nikula
Rev
Hi Jiasheng,
On Wed, Nov 27, 2024 at 08:10:42PM +, Jiasheng Jiang wrote:
> From: Jiasheng Jiang
>
> Replace "slab_priorities" with "slab_dependencies" in the error handler
> to avoid memory leak.
>
> Fixes: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
> Cc: # v5.2+
> Re
st allocation caches global")
> Cc: # v5.2+
> Reviewed-by: Nirmoy Das
> Signed-off-by: Jiasheng Jiang
Reviewed-by: Andi Shyti
Thanks,
Andi
Ping, Vinod :-)
Andi
On Mon, Nov 11, 2024 at 07:32:42PM +0530, Jyothi Kumar Seerapu wrote:
> GSI hardware generates an interrupt for each transfer completion.
> For multiple messages within a single transfer, this results
> in receiving N interrupts for N messages, which can introduce
> significa
Hi Jyothi,
...
> @@ -523,26 +576,49 @@ static int geni_i2c_gpi(struct geni_i2c_dev *gi2c,
> struct i2c_msg *msg,
> enum dma_transfer_direction dma_dirn;
> struct dma_async_tx_descriptor *desc;
> int ret;
> + struct gpi_multi_xfer *gi2c_gpi_xfer;
> + dma_cookie_t cookie;
Hi Nitin,
On Thu, Oct 03, 2024 at 07:40:44PM +0530, Nitin Gote wrote:
> From: Chris Wilson
>
> On Haswell, in particular, we see an issue where resets fails because
> the engine resumes from an incorrect RING_HEAD. Since the RING_HEAD
> doesn't point to the remaining requests to re-run, but may
fixes are part of it. Unless someone wants it
strongly.
Without the Fixes tag:
Reviewed-by: Andi Shyti
Andi
(*) 3de5774cb8c0 ("drm/i915/irq: Rename suspend/resume functions")
> ---
> Noticed that Stephen also reported this so added a Closes URL.
> ---
> Documentation/gpu/i
Hi Andrew,
On Sun, Sep 15, 2024 at 03:01:55PM GMT, Andrew Kreimer wrote:
> Fix typos in documentation.
>
> Reported-by: Matthew Wilcox
> Signed-off-by: Andrew Kreimer
Reviewed-by: Andi Shyti
Because we are receiving lots of typos patches in this period,
it's nice to have th
e' in the comment &
> replace 'droping' with 'dropping' in the comment &
> replace 'sacrifical' with 'sacrificial' in the comment.
>
> Signed-off-by: Yan Zhen
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Yan,
On Fri, Sep 13, 2024 at 02:17:27PM GMT, Yan Zhen wrote:
> Correctly spelled comments make it easier for the reader to understand
> the code.
>
> Replace 'platformas' with 'platforms' in the comment &
> replace 'prefere' with 'prefer' in the comment &
> replace 'corresponsding' with 'corre
Hi Shen,
On Fri, Sep 13, 2024 at 10:16:12AM GMT, Shen Lichuan wrote:
> Fixed some spelling errors, the details are as follows:
>
> -in the code comments:
> addess->address
> trasitions->transitions
> furture->future
> unsubmited->unsubmitted
>
> Signed-off-by: Shen Lichua
Hi Yuesong,
On Fri, Aug 23, 2024 at 10:36:12AM GMT, Yuesong Li wrote:
> cocci report a double assignment warning. 'as_sdp->duration_incr_ms'
> was assigned twice in intel_dp_compute_as_sdp().
>
> Signed-off-by: Yuesong Li
reviewed and merged to drm-intel-next.
Thanks,
Andi
Hi Zhang He,
I merged your previous patch so that you don't need to resend it
anymore.
I already asked you not to resend it in the past version. Please,
read carefully the comments you receive.
I repeat: add the versioning. When you do:
git format patch ...
you get:
[PATCH 1/1] drm/
se of your correct
name as Author and as Signer.
3. Add the tags that you collected in the previous version of the
patch. I did review your change, so that you should have added
my:
Reviewed-by: Andi Shyti
For now it's OK, your patch is accepted, I will merge it and then
I will notify
s from reviewers.
Said that, I asked you:
1. include the proper mailing lists when you send patches (use
get_maintainers.pl)
2. Do you really want to use "zhanghe9702" as a name rather than
your real "Name Surname" as everyone does?
Andi
> At 2024-09-10 17:24:32, "
fective Ring
> freq (MHz)\n");
> + seq_puts(m, "GPU freq (MHz)\tEffective GPU freq (MHz)\tEffective Ring
> freq (MHz)\n");
This is correct:
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Carlos,
Thanks for your patch, sorry for having taken so much time, looks
good, just some nitpicks.
...
> diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c
> b/drivers/i2c/busses/i2c-imx-lpi2c.c
> index 976d43f73f38..530ca5d76403 100644
> --- a/drivers/i2c/busses/i2c-imx-lpi2c.c
> +++ b/driver
Hi Sima,
On Tue, Aug 27, 2024 at 07:05:05PM +0200, Daniel Vetter wrote:
> On Mon, Aug 19, 2024 at 01:31:40PM +0200, Andi Shyti wrote:
> > The i915 driver generates sysfs entries for each engine of the
> > GPU in /sys/class/drm/cardX/engines/.
> >
> > The process is st
Hi Heiko,
On Tue, Sep 03, 2024 at 11:59:12PM GMT, Heiko Stübner wrote:
> Am Dienstag, 3. September 2024, 18:47:17 CEST schrieb Andi Shyti:
> > On Tue, Sep 03, 2024 at 11:59:34AM GMT, Detlev Casanova wrote:
> > > On Tuesday, 3 September 2024 11:46:00 EDT Andi Shyti
Hi,
On Tue, Sep 03, 2024 at 11:22:33AM GMT, Detlev Casanova wrote:
> Just like RK356x and RK3588, RK3576 is compatible to the existing
> rk3399 binding.
>
> Signed-off-by: Detlev Casanova
> Acked-by: Krzysztof Kozlowski
> Acked-by: Heiko Stuebner
merged to i2c/i2c-host.
Thanks,
Andi
BTW, just as a self reminder,
Reviewed-by: Andi Shyti
Thanks,
Andi
On Tue, Sep 03, 2024 at 11:22:33AM GMT, Detlev Casanova wrote:
> Just like RK356x and RK3588, RK3576 is compatible to the existing
> rk3399 binding.
>
> Signed-off-by: Detlev Casanova
> Acked-by: Krzysztof Koz
Hi,
On Tue, Sep 03, 2024 at 11:59:34AM GMT, Detlev Casanova wrote:
> On Tuesday, 3 September 2024 11:46:00 EDT Andi Shyti wrote:
> > Hi,
> >
> > On Tue, Sep 03, 2024 at 11:22:33AM GMT, Detlev Casanova wrote:
> > > Just like RK356x and RK3588, RK3576 is compatibl
Hi,
On Tue, Sep 03, 2024 at 11:22:33AM GMT, Detlev Casanova wrote:
> Just like RK356x and RK3588, RK3576 is compatible to the existing
> rk3399 binding.
>
> Signed-off-by: Detlev Casanova
> Acked-by: Krzysztof Kozlowski
> Acked-by: Heiko Stuebner
I will apply this after 1 and 2 have been merg
Hi Sima,
On Wed, Aug 28, 2024 at 03:47:21PM +0200, Daniel Vetter wrote:
> On Wed, Aug 28, 2024 at 10:20:15AM +0200, Andi Shyti wrote:
> > Hi Sima,
> >
> > first of all, thanks for looking into this series.
> >
> > On Tue, Aug 27, 2024 at 07:31:21PM +0200, Danie
Hi Sima,
first of all, thanks for looking into this series.
On Tue, Aug 27, 2024 at 07:31:21PM +0200, Daniel Vetter wrote:
> On Fri, Aug 23, 2024 at 03:08:40PM +0200, Andi Shyti wrote:
> > Hi,
> >
> > This patch series introduces static load balancing for GPUs with
> &g
Hi Chris,
just a kind ping: any chance you can take a look at this? I would
really appreciate.
Thanks,
Andi
On Fri, Aug 23, 2024 at 03:08:40PM +0200, Andi Shyti wrote:
> Hi,
>
> This patch series introduces static load balancing for GPUs with
> multiple compute engines. It's
Hi Renjun,
On Sat, Aug 24, 2024 at 04:36:34PM +0800, renjun wang wrote:
> The blank line between title "Returns:" and detail description is not
> allowed, otherwise the title will goes under the description block in
> generated .html file after running `make htmldocs`.
>
> There are a few example
ssue
>
> v3:
> - Fix code alignment
> - Apply the patch on a clean drm-tip
>
> Signed-off-by: Yu Jiaoliang
> Reviewed-by: Jani Nikula
> Reviewed-by: Andi Shyti
merged to drm-intel-gt-next.
Thanks,
Andi
Hi Rodrigo,
On Fri, Aug 23, 2024 at 09:41:31AM -0400, Rodrigo Vivi wrote:
> On Wed, Aug 21, 2024 at 09:32:48AM +0200, Andi Shyti wrote:
> > On Tue, Aug 20, 2024 at 05:22:40PM -0400, Rodrigo Vivi wrote:
> > > On Mon, Aug 19, 2024 at 01:31:40PM +0200, Andi Shyti wrote:
...
>
e user can set the CCS mode to 1, 2, or 4,
depending on the desired number of exposed engines and the
required load balancing.
The interface will return -EBUSY if other clients are connected
to i915, or -EINVAL if an invalid value is set.
Signed-off-by: Andi Shyti
---
drivers/gpu/d
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