On Thu, Nov 21, 2024 at 9:39 PM Ying Liu wrote:
>
> On 11/22/24, Marek Vasut wrote:
> > On 11/20/24 7:38 AM, Ying Liu wrote:
> >
> > [...]
> >
> > >>> If the DP monitors support typical video modes like 1080p60 with
> > >>> 148.5MHz pixel clock rate, I assume these typical video modes work
> > >>>
g.com/media/en/technical-documentation/data-sheets/ADV7533.pdf
Thanks for doing that. I never noticed it only supported 2,3 or 4
lanes, but this patch makes sense to me.
>
> Fixes: 1e4d58cd7f88 ("drm/bridge: adv7533: Create a MIPI DSI device")
> Reported-by: Hien Huynh
> Cc:
On Wed, Oct 30, 2024 at 4:01 AM Frieder Schrempf
wrote:
>
> Hi Johannes,
>
> On 25.10.24 10:05 AM, mailingli...@johanneskirchmair.de wrote:
> > [Sie erhalten nicht häufig E-Mails von mailingli...@johanneskirchmair.de.
> > Weitere Informationen, warum dies wichtig ist, finden Sie unter
> > https:
I have been testing various settings on the HDMI out of the i.MX8MP.
I noticed that sometimes my monitor would not sync, but sometimes it
would on the same resolution/refresh rate. Frieder noted the LCDIF
was sometimes underflowing, so read up on it a little bit.
In the comments of the LCDIF dri
K monitor to 31. Of
those 31, three did not appear to sync, but not all the frequencies in
the LUT sync for me either, so I have no objection to moving forward
with this, but I wonder if we should have a note in there about why we
have a 5% tolerance.
> Signed-off-by: Dominique Martinet
Tes
On Wed, Aug 21, 2024 at 8:59 PM Adam Ford wrote:
>
> On Wed, Aug 21, 2024 at 7:45 AM Adam Ford wrote:
> >
> > On Tue, Aug 20, 2024 at 10:58 PM Dominique MARTINET
> > wrote:
> > >
> > > Adam Ford wrote on Tue, Aug 20, 2024 at 09:49:03PM -0500
On Wed, Aug 21, 2024 at 7:45 AM Adam Ford wrote:
>
> On Tue, Aug 20, 2024 at 10:58 PM Dominique MARTINET
> wrote:
> >
> > Adam Ford wrote on Tue, Aug 20, 2024 at 09:49:03PM -0500:
> > > > > However, this check is a bit overcautious in that it only allows exa
On Tue, Aug 20, 2024 at 10:58 PM Dominique MARTINET
wrote:
>
> Adam Ford wrote on Tue, Aug 20, 2024 at 09:49:03PM -0500:
> > > > However, this check is a bit overcautious in that it only allows exact
> > > > rate matches. IIRC HDMI allows a rate mismatch of +- 0.5%,
On Thu, Aug 15, 2024 at 3:19 AM Frieder Schrempf
wrote:
>
> Hi Dominique, hi Lucas,
>
> On 17.06.24 6:32 PM, Lucas Stach wrote:
> > Hi Dominique,
> >
> > Am Montag, dem 17.06.2024 um 15:16 +0900 schrieb Dominique MARTINET:
> >> Adam Ford wrote on Sat, Feb 0
On Sun, Jun 30, 2024 at 5:19 PM Adam Ford wrote:
>
> In the process of adding support for shared IRQ pins, a scenario
> was accidentally created where adv7511_irq_process returned
> prematurely causing the EDID to fail randomly.
>
> Since the interrupt handler is broken up in
while still returning proper values of either IRQ_HANDLED or IRQ_NONE.
Reported-by: Liu Ying
Fixes: f3d9683346d6 ("drm/bridge: adv7511: Allow IRQ to share GPIO pins")
Signed-off-by: Adam Ford
Tested-by: Liu Ying # i.MX8MP EVK ADV7535 EDID retrieval
w/o IRQ
Reviewed-by: Dmitry Ba
On Mon, Jun 17, 2024 at 8:29 AM Linux regression tracking (Thorsten
Leemhuis) wrote:
>
> On 17.06.24 15:14, Adam Ford wrote:
> > On Mon, Jun 17, 2024 at 8:00 AM Linux regression tracking (Thorsten
> > Leemhuis) wrote:
> >>
> >> [CCing the regression l
On Mon, Jun 17, 2024 at 1:17 AM Dominique MARTINET
wrote:
>
> Adam Ford wrote on Sat, Feb 03, 2024 at 10:52:50AM -0600:
> > From: Lucas Stach
> >
> > Add a simple wrapper driver for the DWC HDMI bridge driver that
> > implements the few bits that are necessary t
nfo/about/#tldr
> If I did something stupid, please tell me, as explained on that page.
>
> #regzbot poke
>
> On 01.06.24 15:24, Adam Ford wrote:
> > In the process of adding support for shared IRQ pins, a scenario
> > was accidentally created where adv7511_irq_process returned
-Yu Tsai wrote:
> > > > The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one
> > > > of the Series6XT GPUs, another sub-family of the Rogue family.
> > >
> > > I've added Adam Ford who sent out some DT related patches [1] for the
> &g
On Sat, Jun 1, 2024 at 8:25 AM Adam Ford wrote:
>
> In the process of adding support for shared IRQ pins, a scenario
> was accidentally created where adv7511_irq_process returned
> prematurely causing the EDID to fail randomly.
>
> Since the interrupt handler is broken up in
On Fri, May 31, 2024 at 6:23 AM Frank Binns wrote:
>
> Hi ChenYu,
>
> On Fri, 2024-05-31 at 12:00 +0800, Chen-Yu Tsai wrote:
> > On Thu, May 30, 2024 at 4:35 PM Chen-Yu Tsai wrote:
> > > Hi everyone,
> > >
> > > This series enables the PowerVR GPU found in the MT8173 SoC, found in
> > > some Chro
instances, adjust htotal
and hsync to round the HFP up, and recalculate the htotal.
This allows 720P-60 to operation on an i.MX8MP with a four-lane
configuration.
Tested-by: Frieder Schrempf # Kontron BL i.MX8MM
with HDMI monitor
Signed-off-by: Adam Ford
---
V2: No changes
V3: Remove the
307185f0f ("drm/bridge: samsung-dsim: update PLL reference clock")
Signed-off-by: Adam Ford
Reviewed-by: Frieder Schrempf
Tested-by: Frieder Schrempf
Reviewed-by: Marek Vasut
Tested-by: Marek Szyprowski
---
V2: Only update the commit message to reflect why these values
wer
while still returning proper values of either IRQ_HANDLED or IRQ_NONE.
Reported-by: Liu Ying
Fixes: f3d9683346d6 ("drm/bridge: adv7511: Allow IRQ to share GPIO pins")
Signed-off-by: Adam Ford
Tested-by: Liu Ying # i.MX8MP EVK ADV7535 EDID retrieval
w/o IRQ
---
V2: Fix uninitial
On Fri, May 31, 2024 at 8:37 AM Frank Binns wrote:
>
> Hi ChenYu,
>
> On Thu, 2024-05-30 at 16:35 +0800, Chen-Yu Tsai wrote:
> > The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is one
> > of the Series6XT GPUs, another sub-family of the Rogue family.
>
>
On Mon, May 20, 2024 at 8:16 PM Adam Ford wrote:
>
> In the process of adding support for shared IRQ pins, a scenario
> was accidentally created where adv7511_irq_process returned
> prematurely causing the EDID to fail randomly.
>
> Since the interrupt handler is broken up in
On Mon, May 20, 2024 at 4:16 PM Dmitry Baryshkov
wrote:
>
> On Mon, May 20, 2024 at 07:46:05AM -0500, Adam Ford wrote:
> > On Mon, May 20, 2024 at 7:00 AM Dmitry Baryshkov
> > wrote:
> > >
> > > On Mon, 20 May 2024 at 14:48, Sui Jingfeng wrote:
> > &g
while still returning proper values of either IRQ_HANDLED or IRQ_NONE.
Reported by: Liu Ying
Fixes: f3d9683346d6 ("drm/bridge: adv7511: Allow IRQ to share GPIO pins")
Signed-off-by: Adam Ford
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h
b/drivers/gpu/drm/bridge/adv7511/
On Mon, May 20, 2024 at 7:00 AM Dmitry Baryshkov
wrote:
>
> On Mon, 20 May 2024 at 14:48, Sui Jingfeng wrote:
> >
> > Hi,
> >
> >
> > On 5/20/24 19:13, Dmitry Baryshkov wrote:
> > > On Mon, 20 May 2024 at 14:11, Sui Jingfeng wrote:
> > >>
> > >> Hi,
> > >>
> > >> On 5/20/24 06:11, Dmitry Baryshk
gt;
> Fix the issue by checking adv7511->i2c_main->irq before exiting interrupt
> handling from adv7511_irq_process().
>
> Fixes: f3d9683346d6 ("drm/bridge: adv7511: Allow IRQ to share GPIO pins")
> Signed-off-by: Liu Ying
Acked-by: Adam Ford
> ---
> driv
On Tue, Apr 16, 2024 at 4:18 PM Adam Ford wrote:
>
> On Mon, Mar 4, 2024 at 6:49 PM Adam Ford wrote:
> >
> > The DSI to HDMI bridge supports hot-plut-detect, but the
> > driver didn't previously support a shared IRQ GPIO. With
> > the driver updated, the i
On Thu, Apr 25, 2024 at 4:19 AM Marek Szyprowski
wrote:
>
> On 12.02.2024 00:09, Adam Ford wrote:
> > When using video sync pulses, the HFP, HBP, and HSA are divided between
> > the available lanes if there is more than one lane. For certain
> > timings and lane configu
On Mon, Apr 22, 2024 at 8:01 AM Marek Vasut wrote:
>
> On 4/22/24 2:09 PM, Adam Ford wrote:
> > On Sun, Apr 21, 2024 at 9:36 AM Marek Vasut wrote:
> >>
> >> On 2/12/24 12:09 AM, Adam Ford wrote:
> >>> When using video sync pulses, the HFP, HBP, and H
On Sun, Apr 21, 2024 at 9:36 AM Marek Vasut wrote:
>
> On 2/12/24 12:09 AM, Adam Ford wrote:
> > When using video sync pulses, the HFP, HBP, and HSA are divided between
> > the available lanes if there is more than one lane. For certain
> > timings and lane configurat
h the DRM_IMX8MP_HDMI_PVI, also
imply it instead of selecting it.
Fixes: 1f36d634670d ("drm/bridge: imx: add bridge wrapper driver for i.MX8MP
DWC HDMI")
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202404190103.llm8ltup-...@intel.com/
Signed-off-by: Ad
: imx: add bridge wrapper driver for i.MX8MP
DWC HDMI")
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202404190103.llm8ltup-...@intel.com/
Signed-off-by: Adam Ford
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig
b/drivers/gpu/drm/bridge/imx/Kconfig
ind
On Mon, Mar 4, 2024 at 6:49 PM Adam Ford wrote:
>
> The DSI to HDMI bridge supports hot-plut-detect, but the
> driver didn't previously support a shared IRQ GPIO. With
> the driver updated, the interrupt can be added to the bridge.
>
> Signed-off-by: Adam Ford
> Rev
On Sun, Feb 11, 2024 at 5:09 PM Adam Ford wrote:
>
> When using video sync pulses, the HFP, HBP, and HSA are divided between
> the available lanes if there is more than one lane. For certain
> timings and lane configurations, the HFP may not be evenly divisible.
> If the HFP is r
On Tue, Mar 5, 2024 at 2:18 AM Laurent Pinchart
wrote:
>
> Hello Adam,
>
> Thank you for the patch.
>
> On Mon, Mar 04, 2024 at 06:48:57PM -0600, Adam Ford wrote:
> > The IRQ registration currently assumes that the GPIO is dedicated
> > to it, but that may not n
e confusion. I was confused by the versioning too when
I pulled from different parts of Lucas' stuff. Since varying
components were applied at different times, and the remaining part was
based on the wrong starting point and not applied, I reverted back to
the versioning of the PHY which was t
On Thu, Mar 7, 2024 at 6:41 AM Frank Binns wrote:
>
> Hi Adam,
>
> On Mon, 2024-02-26 at 21:45 -0600, Adam Ford wrote:
> > Update the binding to add support for various Renesas SoC's with PowerVR
> > Rogue GX6250 and GX6650 GPUs. These devices only need one cloc
On Thu, Mar 7, 2024 at 6:37 AM Frank Binns wrote:
>
> On Thu, 2024-03-07 at 12:26 +, Frank Binns wrote:
> > On Tue, 2024-02-27 at 05:50 -0600, Adam Ford wrote:
> > > On Tue, Feb 27, 2024 at 3:31 AM Matt Coster
> > > wrote:
> > > > Hi Adam,
> >
On Tue, Mar 5, 2024 at 5:58 AM Frank Binns wrote:
>
> Hi Adam,
>
> Sorry for not responding sooner. I've recently just returned from paternity
> leave, so just catching up on everything.
Congratulations!
>
> On Thu, 2024-02-15 at 11:22 -0600, Adam Ford wrote:
>
The DSI to HDMI bridge supports hot-plut-detect, but the
driver didn't previously support a shared IRQ GPIO. With
the driver updated, the interrupt can be added to the bridge.
Signed-off-by: Adam Ford
Reviewed-by: Laurent Pinchart
---
V2: No Change
diff --git a/arch/arm64/boot/dts/free
r not it there
was an IRQ, the IRQF_SHARED can be set to share a GPIO IRQ.
Signed-off-by: Adam Ford
---
V2: Add check to see if there is IRQ data to handle
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index b5518ff97165..f3b4616a8fb6 1
On Wed, Feb 28, 2024 at 10:31 AM Laurent Pinchart
wrote:
>
> Hi Adam,
>
> Thank you for the patch.
>
> On Wed, Feb 28, 2024 at 05:37:35AM -0600, Adam Ford wrote:
> > The IRQ registration currently assumes that the GPIO is
> > dedicated to it, but that may not neces
The DSI to HDMI bridge supports hot-plut-detect, but the
driver didn't previously support a shared IRQ GPIO. With
the driver updated, the interrupt can be added to the bridge.
Signed-off-by: Adam Ford
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
b/arch/arm64/boo
The IRQ registration currently assumes that the GPIO is
dedicated to it, but that may not necessarily be the case.
If the board has another device sharing the IRQ, it won't be
registered and the hot-plug detect fails. This is easily
fixed by add the IRQF_SHARED flag.
Signed-off-by: Adam
On Sun, Feb 11, 2024 at 5:09 PM Adam Ford wrote:
>
> The P divider should be set based on the min and max values of
> the fin pll which may vary between different platforms.
> These ranges are defined per platform, but hard-coded values
> were used instead which resulted in
On Tue, Feb 27, 2024 at 2:11 AM Geert Uytterhoeven wrote:
>
> Hi Adam,
>
> Thanks for your patch!
>
> On Tue, Feb 27, 2024 at 4:46 AM Adam Ford wrote:
> > The GPU on the R-Car H3 is a Rogue GX6650 which uses firmware
> > rogue_4.46.6.61_v1.fw available
On Tue, Feb 27, 2024 at 5:04 AM Geert Uytterhoeven wrote:
>
> Hi Matt,
>
> On Tue, Feb 27, 2024 at 10:31 AM Matt Coster wrote:
> >
> > Hi Adam,
> >
> > Thanks for these patches! I'll just reply to this one patch, but my
> > comments apply to them al
On Tue, Feb 27, 2024 at 3:31 AM Matt Coster wrote:
>
> Hi Adam,
>
> Thanks for these patches! I'll just reply to this one patch, but my
> comments apply to them all.
>
> On 27/02/2024 03:45, Adam Ford wrote:
> > The GPU on the RZ/G2M is a Rogue GX6250 which uses fi
: Adam Ford
diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
index bea4edd17d53..3e9defaeb00f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
@@ -2771,6 +2771,16 @@ gic: interrupt-controller
: Adam Ford
diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
index 7846fea8e40d..0f17bc3f2d9a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
@@ -2558,6 +2558,16 @@ gic: interrupt-controller
-by: Adam Ford
diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
index 58f9286a5ab5..cc17e624c069 100644
--- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
@@ -2438,6 +2438,16 @@ gic: interrupt-controller
: Adam Ford
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index be55ae83944c..398c9df1577b 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -2464,6 +2464,16 @@ gic: interrupt-controller
Update the binding to add support for various Renesas SoC's with PowerVR
Rogue GX6250 and GX6650 GPUs. These devices only need one clock, so update
the table to indicate such like what was done for the ti,am62-gpu.
Signed-off-by: Adam Ford
diff --git a/Documentation/devicetree/bindings/gp
/imagination/linux-firmware/-/tree/powervr/powervr?ref_type=heads
Adam Ford (6):
dt-bindings: gpu: powervr-rogue: Add PowerVR support for some Renesas
GPUs
arm64: dts: renesas: r8a774a1: Enable GPU
arm64: dts: renesas: r8a774e1: Enable GPU
arm64: dts: renesas: r8a77951: Enable GPU
arm64: dts
: Adam Ford
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index a8a44fe5e83b..8923d9624b39 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -2352,6 +2352,16 @@ gic: interrupt-controller
On Tue, Feb 20, 2024 at 5:55 AM Erico Nunes wrote:
>
> Hi,
>
> On Mon, Feb 19, 2024 at 9:38 PM Adam Ford wrote:
> > /usr/share/vulkan/explicit_layer.d/VkLayer_MESA_overlay.json
> > ERROR:loader_validate_instance_extensions: Instance
> > extension VK_KHR
On Tue, Feb 20, 2024 at 5:26 AM Adam Ford wrote:
>
> On Tue, Feb 20, 2024 at 3:21 AM Matt Coster wrote:
> >
> > Hi Adam,
> >
> > On 19/02/2024 20:38, Adam Ford wrote:
> > > On Mon, Feb 19, 2024 at 3:00 AM Matt Coster
> > > wrote:
> > >
On Tue, Feb 20, 2024 at 3:21 AM Matt Coster wrote:
>
> Hi Adam,
>
> On 19/02/2024 20:38, Adam Ford wrote:
> > On Mon, Feb 19, 2024 at 3:00 AM Matt Coster wrote:
> >>
> >> Hi Adam,
> >>
> >> On 18/02/2024 23:26, Adam Ford wrote:
>
On Mon, Feb 19, 2024 at 3:00 AM Matt Coster wrote:
>
> Hi Adam,
>
> On 18/02/2024 23:26, Adam Ford wrote:
> > On Fri, Feb 16, 2024 at 8:14 AM Maxime Ripard wrote:
> >>
> >> On Fri, Feb 16, 2024 at 09:13:14AM +, Biju Das wrote:
> >>> Hi M
On Mon, Feb 19, 2024 at 1:45 AM Biju Das wrote:
>
> Hi Adam,
>
> > -Original Message-
> > From: Adam Ford
> > Sent: Sunday, February 18, 2024 11:26 PM
> > Subject: Re: RE: RE: [PATCH v2] drm/imagination: DRM_POWERVR should depend
> > on ARCH_K3
> > Subject: Re: RE: [PATCH v2] drm/imagination: DRM_POWERVR should depend on
> > > ARCH_K3
> > >
> > > On Fri, Feb 16, 2024 at 08:47:46AM +, Biju Das wrote:
> > > > Hi Adam Ford,
> > > >
> > > > > -Original Message---
On Fri, Feb 16, 2024 at 3:05 AM Alexander Stein
wrote:
>
> Hi all,
>
> Am Samstag, 3. Februar 2024, 17:52:49 CET schrieb Adam Ford:
> > From: Lucas Stach
> >
> > The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP
> > core with a lit
On Thu, Feb 15, 2024 at 11:22 AM Adam Ford wrote:
>
> On Thu, Feb 15, 2024 at 11:10 AM Adam Ford wrote:
> >
> > On Thu, Feb 15, 2024 at 10:54 AM Geert Uytterhoeven
> > wrote:
> > >
> > > Hi Maxime,
> > >
> > > On Thu, Feb 15, 2024 at 5
On Thu, Feb 15, 2024 at 11:10 AM Adam Ford wrote:
>
> On Thu, Feb 15, 2024 at 10:54 AM Geert Uytterhoeven
> wrote:
> >
> > Hi Maxime,
> >
> > On Thu, Feb 15, 2024 at 5:18 PM Maxime Ripard wrote:
> > > On Thu, Feb 15, 2024 at 01:50:09PM +0100, G
On Thu, Feb 15, 2024 at 10:54 AM Geert Uytterhoeven
wrote:
>
> Hi Maxime,
>
> On Thu, Feb 15, 2024 at 5:18 PM Maxime Ripard wrote:
> > On Thu, Feb 15, 2024 at 01:50:09PM +0100, Geert Uytterhoeven wrote:
> > > Using the Imagination Technologies PowerVR Series 6 GPU requires a
> > > proprietary fir
sync properly. In these instances, adjust htotal
and hsync to round the HFP up, and recalculate the htotal.
Tested-by: Frieder Schrempf # Kontron BL i.MX8MM
with HDMI monitor
Signed-off-by: Adam Ford
---
V2: No changes
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c
b/drivers/gpu/drm
307185f0f ("drm/bridge: samsung-dsim: update PLL reference clock")
Signed-off-by: Adam Ford
Reviewed-by: Frieder Schrempf
Tested-by: Frieder Schrempf
---
V2: Only update the commit message to reflect why these values
were chosen. No code change present
diff --git a/drivers/gpu/
On Mon, Jan 29, 2024 at 2:17 AM Frieder Schrempf
wrote:
>
> On 25.01.24 19:44, Adam Ford wrote:
> > On Mon, Dec 11, 2023 at 9:33 PM Adam Ford wrote:
> >>
> >> When using video sync pulses, the HFP, HBP, and HSA are divided between
> >> the available lan
On Wed, Feb 7, 2024 at 3:24 AM Neil Armstrong wrote:
>
> On 07/02/2024 10:22, Fabio Estevam wrote:
> > Hi Adam,
> >
> > On Tue, Feb 6, 2024 at 9:23 PM Adam Ford wrote:
> >>
> >> Two separate build warnings were reported. One from an
> >> uni
test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202402062134.a6cqat3s-...@intel.com/
Signed-off-by: Adam Ford
diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
index a76b7669fe8a..f2a09c879e3d 100644
--- a/drivers/gpu/drm/bridge/imx/i
On Tue, Feb 6, 2024 at 11:06 AM Nathan Chancellor wrote:
>
> Hi all,
>
> On Sat, Feb 03, 2024 at 10:52:48AM -0600, Adam Ford wrote:
> > From: Lucas Stach
> >
> > This IP block is found in the HDMI subsystem of the i.MX8MP SoC. It has a
> > full timing genera
On Mon, Feb 5, 2024 at 2:17 AM Marco Felsch wrote:
>
> On 24-02-04, Dmitry Baryshkov wrote:
> > On Sat, 3 Feb 2024 at 17:53, Adam Ford wrote:
> > >
> > > From: Lucas Stach
> > >
> > > This adds the driver for the Samsung HDMI PHY found on the
>
On Mon, Feb 5, 2024 at 1:26 AM Alexander Stein
wrote:
>
> Hi Adam,
>
> thanks for working on this.
>
> Am Samstag, 3. Februar 2024, 17:52:45 CET schrieb Adam Ford:
> > From: Lucas Stach
> >
> > This adds the PGC and HDMI blk-ctrl nodes providing power contro
On Sun, Feb 4, 2024 at 6:00 AM Francesco Dolcini wrote:
>
> On Sat, Feb 03, 2024 at 10:52:46AM -0600, Adam Ford wrote:
> > From: Lucas Stach
> >
> > The HDMI irqsteer is a secondary interrupt controller within the HDMI
> > subsystem that maps all HDMI peripher
The i.MX8M Plus has support for an HDMI transmitter. The
video is genereated by lcdif3, routed to the hdmi parallel
video interface, then fed to a DW HDMI bridge to support
up to 4K video output.
Signed-off-by: Adam Ford
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion
From: Lucas Stach
This adds the DT nodes for all the peripherals that make up the
HDMI display pipeline.
Signed-off-by: Lucas Stach
Signed-off-by: Adam Ford
---
V2: I took this from Lucas' original submission with the following:
Removed extra clock from HDMI-TX since it is now pa
From: Lucas Stach
Add a simple wrapper driver for the DWC HDMI bridge driver that
implements the few bits that are necessary to abstract the i.MX8MP
SoC integration.
Signed-off-by: Lucas Stach
Reviewed-by: Laurent Pinchart
Tested-by: Marek Vasut
Tested-by: Adam Ford #imx8mp-beacon
Tested-by
From: Lucas Stach
The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP
core with a little bit of SoC integration around it.
Signed-off-by: Lucas Stach
Signed-off-by: Adam Ford
---
V3: Change name and location to better idenfity as a bridge and
HDMI 2.0a transmitter
Tested-by: Luca Ceresoli
Tested-by: Fabio Estevam
Signed-off-by: Adam Ford
---
V8: No Change
V7: Re-do some includes to address build issues after rebasing from
Linux-next
V6: No change.
V5: I (Adam) tried to help move this along, so I took Lucas' patch and
attempted to apply
From: Lucas Stach
Add binding for the i.MX8MP HDMI parallel video interface block.
Signed-off-by: Lucas Stach
Reviewed-by: Laurent Pinchart
Reviewed-by: Conor Dooley
Signed-off-by: Adam Ford
---
V8: Add interrupt-parent
V7: No Change
V6: Add s-o-b message for myself (Adam)
V5: I
From: Lucas Stach
This adds the PGC and HDMI blk-ctrl nodes providing power control for
HDMI subsystem peripherals.
Signed-off-by: Adam Ford
Signed-off-by: Lucas Stach
---
V2: Add missing power-domains hdcp and hrv
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38
From: Lucas Stach
The HDMI irqsteer is a secondary interrupt controller within the HDMI
subsystem that maps all HDMI peripheral IRQs into a single upstream
IRQ line.
Signed-off-by: Lucas Stach
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 13 +
1 file changed, 13 insertions(+)
d
WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_atomic_helper.c:1634
drm_atomic_helper_wait_for_vblanks.part.0+0x23c/0x260
Add fdcc clock to LCDIF and HDMI TX power domains to fix the issue.
Signed-off-by: Adam Ford
Reviewed-by: Jacky Bai
Signed-off-by: Sandor Yu
---
V2: No Change
---
drivers
t for HDMITX
in desgin, but it is part of HDMI domain that needed by HDMITX.
So I think it is reasonable added it to the power domain driver."
The driver also supports two power domains which are missing from the binding
that also fix an issue with resuming from suspend.
Signed-off-by: Adam Fo
From: Lucas Stach
Add a DT binding for the HDMI PHY found on the i.MX8MP SoC.
Signed-off-by: Lucas Stach
Signed-off-by: Adam Ford
Reviewed-by: Krzysztof Kozlowski
---
V3: Removed mintems at the request of Krzysztof and add his
reviewed-by
V2: I tried to help move this along, so I
From: Lucas Stach
This adds the driver for the Samsung HDMI PHY found on the
i.MX8MP SoC.
Signed-off-by: Lucas Stach
Signed-off-by: Adam Ford
Tested-by: Alexander Stein
---
V4: Make lookup table hex values lower case.
V3: Re-order the Makefile to keep it alphabetical
Remove unused
t to merge them
I used the highest version attempt.
Adam Ford (3):
dt-bindings: soc: imx: add missing clock and power-domains to
imx8mp-hdmi-blk-ctrl
pmdomain: imx8mp-blk-ctrl: imx8mp_blk: Add fdcc clock to hdmimix
domain
arm64: defconfig: Enable DRM_IMX8MP_DW_HDMI_BRIDGE as module
L
On Fri, Feb 2, 2024 at 5:20 AM Luca Ceresoli wrote:
>
> Hello Adam,
>
> On Sat, 6 Jan 2024 16:19:05 -0600
> Adam Ford wrote:
>
> > From: Lucas Stach
> >
> > This adds the driver for the Samsung HDMI PHY found on the
> > i.MX8MP SoC.
> >
> &g
On Tue, Jan 30, 2024 at 11:00 AM Vinod Koul wrote:
>
> Hi Adam,
>
> On 06-01-24, 16:19, Adam Ford wrote:
> > From: Lucas Stach
> >
> > This adds the driver for the Samsung HDMI PHY found on the
> > i.MX8MP SoC.
> >
> > Signed-off-by: Lucas Sta
c 15, 2023 at 05:09:41PM -0300, Fabio Estevam wrote:
> > > > On Fri, Dec 15, 2023 at 4:01 PM Adam Ford wrote:
> > > > > Thanks for the list. I was able to successfully build the stable 6.6
> > > > > branch with those patches applied and I have the
On Mon, Jan 8, 2024 at 9:03 AM Alexander Stein
wrote:
>
> Hi Adam,
>
> thanks for pushing this forward.
>
> Am Samstag, 6. Januar 2024, 23:19:05 CET schrieb Adam Ford:
> > From: Lucas Stach
> >
> > This adds the driver for the Samsung HDMI PHY found on the
&g
On Mon, Dec 11, 2023 at 9:33 PM Adam Ford wrote:
>
> When using video sync pulses, the HFP, HBP, and HSA are divided between
> the available lanes if there is more than one lane. For certain
> timings and lane configurations, the HFP may not be evenly divisible.
> If the HFP is r
On Wed, Jan 10, 2024 at 5:48 AM Alexander Stein
wrote:
>
> Hi Adam,
>
> thanks for pushing this forward.
>
> Am Samstag, 6. Januar 2024, 22:51:44 CET schrieb Adam Ford:
> > From: Lucas Stach
> >
> > Add binding for the i.MX8MP HDMI parallel video interface
From: Lucas Stach
This adds the driver for the Samsung HDMI PHY found on the
i.MX8MP SoC.
Signed-off-by: Lucas Stach
Signed-off-by: Adam Ford
---
V2: Fixed some whitespace found from checkpatch
Change error handling when enabling apbclk to use dev_err_probe
Rebase on Linux-Next
From: Lucas Stach
Add a DT binding for the HDMI PHY found on the i.MX8MP SoC.
Signed-off-by: Lucas Stach
Signed-off-by: Adam Ford
---
V2: Rebase on Linux-Next
Fix bot error due to the word 'binding' being in the description
Add phy-cells to the required list
di
Tested-by: Luca Ceresoli
Tested-by: Fabio Estevam
Signed-off-by: Adam Ford
---
V7: Re-do some includes to address build issues after rebasing from
Linux-next
V6: No change.
V5: I (Adam) tried to help move this along, so I took Lucas' patch and
attempted to apply fixes bas
From: Lucas Stach
Add binding for the i.MX8MP HDMI parallel video interface block.
Signed-off-by: Lucas Stach
Reviewed-by: Laurent Pinchart
Reviewed-by: Conor Dooley
Signed-off-by: Adam Ford
---
V7: No Change
V6: Add s-o-b message for myself (Adam)
V5: I tried to help move this along
Tested-by: Luca Ceresoli
Tested-by: Fabio Estevam
Signed-off-by: Adam Ford
---
V6: No change.
V5: I (Adam) tried to help move this along, so I took Lucas' patch and
attempted to apply fixes based on feedback. I don't have
all the history, so apologies for that.
No chang
From: Lucas Stach
Add binding for the i.MX8MP HDMI parallel video interface block.
Signed-off-by: Lucas Stach
Reviewed-by: Laurent Pinchart
Reviewed-by: Conor Dooley
Signed-off-by: Adam Ford
---
V6: Add s-o-b message for myself (Adam)
V5: I tried to help move this along, so I took Lucas
Tested-by: Luca Ceresoli
Tested-by: Fabio Estevam
Signed-off-by: Adam Ford
---
V5: I (Adam) tried to help move this along, so I took Lucas' patch and
attempted to apply fixes based on feedback. I don't have
all the history, so apologies for that.
No changes from V4 t
1 - 100 of 364 matches
Mail list logo
