FYI this patch got feedback at
https://lore.kernel.org/dri-devel/805acaca-3b91-438d-b842-25c055fd8...@amd.com/
Preferably the problem should be addressed on GEM/PRIME code instead of
dma-buf.
Best regards
Thomas
Am 14.08.25 um 09:34 schrieb Thomas Zimmermann:
Imported dma-buf objects need t
Hi Prabhakar,
Thanks for the patch.
> -Original Message-
> From: Prabhakar
> Sent: 28 July 2025 21:15
> Subject: [PATCH v7 3/6] clk: renesas: r9a09g057: Add clock and reset entries
> for DSI and LCDC
>
> From: Lad Prabhakar
>
> Add clock and reset entries for the DSI and LCDC periphe
Hi Prabhakar,
> -Original Message-
> From: Prabhakar
> Sent: 28 July 2025 21:15
> Subject: [PATCH v7 2/6] clk: renesas: rzv2h-cpg: Add support for DSI clocks
>
> From: Lad Prabhakar
>
> Add support for PLLDSI and PLLDSI divider clocks.
>
> Introduce the `renesas-rzv2h-cpg-pll.h` heade
> -Original Message-
> From: Prabhakar
> Sent: 28 July 2025 21:15
> Subject: [PATCH v7 1/6] clk: renesas: rzv2h-cpg: Add instance field to struct
> pll
>
> From: Lad Prabhakar
>
> Add a two-bit "instance" member to struct pll and extend the PLL_PACK() macro
> to accept an instance
On Fri Aug 15, 2025 at 7:52 AM JST, Lyude Paul wrote:
> For the series:
>
> Reviewed-by: Lyude Paul
Thanks! Pushed the series to nova-next.
On 8/14/25 13:43, Limonciello, Mario wrote:
On 8/14/25 3:29 PM, Lizhi Hou wrote:
Walking hardware contexts created by a process is duplicated in multiple
spots. Add a function, amdxdna_hwctx_walk(), and replace all spots.
hwctx_srcu and dev_lock are good enough to protect hardware context lis
The degamma is to be handled by Color pipeline API.
Signed-off-by: Alex Hung
---
v11:
- Merged enable condition for drm_crtc_enable_color_mgmt (Melissa Wen)
v10:
- Disable CRTC degamma when color pipeline is enabled (Melissa Wen)
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 26 +
Check dpp.hw_3d_lut before creating shaper tf/lut and 3dlut colorops in
colorpipeline and handling these colorops.
Signed-off-by: Alex Hung
---
v10:
- Check dpp.hw_3d_lut before creating shaper tf/lut and 3dlut colorops
(Melissa Wen)
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 47 -
From: Harry Wentland
Add kernel doc for AMD color pipeline.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 122 +++---
1 file changed, 102 insertions(+), 20 deletions(-
This adds support for a 3D LUT.
The color pipeline now consists of the following colorops:
1. 1D curve colorop
2. Multiplier
3. 3x4 CTM
4. 1D curve colorop
5. 1D LUT
6. 3D LUT
7. 1D curve colorop
8. 1D LUT
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
---
v11:
- Update names from *_lut_32
It is to be used to enable HDR by allowing userpace to create and pass
3D LUTs to kernel and hardware.
new drm_colorop_type: DRM_COLOROP_3D_LUT.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v11:
- Update names from *_lut_32_* to *_lut
From: Harry Wentland
Not all HW will be able to do bypass on all color
operations. Introduce an 32 bits 'flags' for all colorop
init functions and DRM_COLOROP_FLAG_ALLOW_BYPASS for creating
the BYPASS property when it's true.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by:
From: Harry Wentland
We want to make sure userspace is aware of the 1D LUT
interpolation. While linear interpolation is common it
might not be supported on all HW. Give driver implementers
a way to specify their interpolation.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harr
Swap the order of matrix and multiplier as designed in hardware.
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v9:
- Update function names by _plane_ (Chaitanya Kumar Borah)
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 12 ++--
.../drm/amd/
This adds support for a multiplier. This multiplier is
programmed via the HDR Multiplier in DCN.
With this change the following IGT tests pass:
kms_colorop --run plane-XR30-XR30-multiply_125
kms_colorop --run plane-XR30-XR30-multiply_inv_125
The color pipeline now consists of the following coloro
This introduces a new drm_colorop_type: DRM_COLOROP_MULTIPLIER.
It's a simple multiplier to all pixel values. The value is
specified via a S31.32 fixed point provided via the
"MULTIPLIER" property.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Melissa W
This adds support for a 3x4 color transformation matrix.
With this change the following IGT tests pass:
kms_colorop --run plane-XR30-XR30-ctm_3x4_50_desat
kms_colorop --run plane-XR30-XR30-ctm_3x4_overdrive
kms_colorop --run plane-XR30-XR30-ctm_3x4_oversaturate
kms_colorop --run plane-XR30-XR30-ct
This patch adds colorops for custom 1D LUTs in the SHAPER and
BLND HW blocks.
With this change the following IGT tests pass:
kms_colorop --run plane-XR30-XR30-srgb_inv_eotf_lut
kms_colorop --run plane-XR30-XR30-srgb_inv_eotf_lut-srgb_eotf_lut
The color pipeline now consists of the following color
We've previously introduced DRM_COLOROP_1D_CURVE for
pre-defined 1D curves. But we also have HW that supports
custom curves and userspace needs the ability to pass
custom curves, aka LUTs.
This patch introduces a new colorop type, called
DRM_COLOROP_1D_LUT that provides a SIZE property which
is us
From: Chaitanya Kumar Borah
Add helper to extract lut values in 32-bit precision needed by
hardware.
Signed-off-by: Alex Hung
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
v11:
- Include help function drm_color_lut32_extract (Uma Shankar)
include/drm/drm_color_mgmt.h
From: Uma Shankar
Existing LUT precision structure drm_color_lut has only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values.
Signed-off-by: Alex Hung
Signed-off-by: Uma Shankar
From: Harry Wentland
This adds support for the BT.709/BT.2020 transfer functions
on all current 1D curve plane colorops, i.e., on DEGAM, SHAPER,
and BLND blocks.
With this change the following IGT subtests pass:
kms_colorop --run plane-XR30-XR30-bt2020_inv_oetf
kms_colorop --run plane-XR30-XR30-
From: Harry Wentland
The BT.709 and BT.2020 OETFs are the same, the only difference
being that the BT.2020 variant is defined with more precision
for 10 and 12-bit per color encodings.
Both are used as encoding functions for video content, and are
therefore defined as OETF (opto-electronic trans
From: Harry Wentland
This patchset enables support for the PQ_125 EOTF and its inverse
on all existing plane 1D curve colorops, i.e., on DEGAM, SHAPER,
and BLND blocks.
With this patchset the following IGT subtests are passing:
kms_colorop --run plane-XR30-XR30-pq_125_eotf
kms_colorop --run plan
From: Harry Wentland
The PQ function defines a mapping of code values to nits (cd/m^2).
The max code value maps to 10,000 nits.
Windows DWM's canonical composition color space (CCCS) defaults
to composing SDR contents to 80 nits and uses a float value of
1.0 to represent this. For this reason A
Expose a 3rd 1D curve colorop, with support for
DRM_COLOROP_1D_CURVE_SRGB_EOTF and program the BLND block
to perform the sRGB transform when the colorop is not in
bypass
With this change the following IGT test passes:
kms_colorop --run plane-XR30-XR30-srgb_eotf-srgb_inv_eotf-srgb_eotf
The color p
Expose a 2nd curve colorop with support for
DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF and program HW to
perform the sRGB Inverse EOTF on the shaper block
when the colorop is not in bypass.
With this change the follow IGT tests pass:
kms_colorop --run plane-XR30-XR30-srgb_inv_eotf
kms_colorop --run plane-
Expose one 1D curve colorop with support for
DRM_COLOROP_1D_CURVE_SRGB_EOTF and program HW to perform
the sRGB transform when the colorop is not in bypass.
With this change the following IGT test passes:
kms_colorop --run plane-XR30-XR30-srgb_eotf
The color pipeline now consists of a single color
cursor plane does not need to have color pipeline.
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v7:
- Add a commit messages
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/di
From: Harry Wentland
Add the default Bypass pipeline and ensure it passes the
kms_colorop test plane-XR30-XR30-bypass.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
---
v10:
- guard "dm_plane_init_colorops" function when !AMD_PRIVATE_COLOR (Melissa Wen)
.
From: Harry Wentland
When the plane_color_pipeline bit is set we should ignore
deprecated properties, such as COLOR_RANGE and COLOR_ENCODING.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/a
Create a new macro for_each_new_colorop_in_state to access new
drm_colorop_state updated from uapi.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v10:
- remove duplicated "is useful" in comments
include/drm/drm_atomic.h | 20 +
From: Harry Wentland
Drivers will need to know whether an atomic check/commit
originated from a client with DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE
so they can ignore deprecated properties, like COLOR_ENCODING
and COLOR_RANGE.
Pass the plane_color_pipeline bit to drm_atomic_state.
Reviewed-by: Simo
From: Harry Wentland
A whole slew of tests for CTM handling that greatly helped in
debugging the CTM code. The extent of tests might seem a bit
silly but they're fast and might someday help save someone
else's day when debugging this.
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-
From: Harry Wentland
While working on the CTM implementation of VKMS I had to ascertain
myself of a few assumptions. One of those is whether drm_fixed.h
treats its numbers using signed-magnitude or twos-complement. It is
twos-complement.
In order to make someone else's day easier I am adding the
From: Harry Wentland
We add two 3x4 matrices into the VKMS color pipeline. The reason
we're adding matrices is so that we can test that application
of a matrix and its inverse yields an output equal to the input
image.
One complication with the matrix implementation has to do with
the fact that
From: Harry Wentland
Certain operations require us to preserve values below 0.0 and
above 1.0 (0x0 and 0x respectively in 16 bpc unorm). One
such operation is a BT709 encoding operation followed by its
decoding operation, or the reverse.
We'll use s32 values as intermediate in and outputs of
From: Harry Wentland
This type is used to support a 3x4 matrix in colorops. A 3x4
matrix uses the last column as a "bias" column. Some HW exposes
support for 3x4. The calculation looks like:
out matrixin
|R| |0 1 2 3 | | R |
|G| = |4 5 6 7 | x | G |
|B| |8 9 10 11| | B
From: Harry Wentland
Two tests are added to VKMS LUT handling:
- linear
- inv_srgb
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
---
v7:
- Fix checkpatch warnings (Louis Chauvet)
- Adde a commit messages
- Fix code styles by
From: Harry Wentland
This patch introduces a VKMS color pipeline that includes two
drm_colorops for named transfer functions. For now the only ones
supported are sRGB EOTF, sRGB Inverse EOTF, and a Linear TF.
We will expand this in the future but I don't want to do so
without accompanying IGT tes
The functions are to clean up color pipeline when a device driver
fails to create its color pipeline.
Signed-off-by: Alex Hung
Reviewed-by: Daniel Stone
Reviewed-by: Simon Ser
Reviewed-by: Melissa Wen
---
v11:
- destroy function takes drm_device *dev instead of drm_plane *plane
(Nícolas Pr
From: Harry Wentland
Add kernel doc for drm_colorop objects.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v8:
- Move this after "drm/colorop: Introduce DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE"
(Simon Ser)
From: Harry Wentland
With the introduction of the pre-blending color pipeline we
can no longer have color operations that don't have a clear
position in the color pipeline. We deprecate all existing
plane properties. For upstream drivers those are:
- COLOR_ENCODING
- COLOR_RANGE
Drivers are ex
From: Harry Wentland
We're adding a new enum COLOR PIPELINE property. This
property will have entries for each COLOR PIPELINE by
referencing the DRM object ID of the first drm_colorop
of the pipeline. 0 disables the entire COLOR PIPELINE.
Userspace can use this to discover the available color
pi
From: Harry Wentland
Print atomic state for drm_colorop in debugfs
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v8:
- Add switch statement to print colorop type (Simon Ser)
v7:
- Add a commit messages
From: Harry Wentland
We'll construct color pipelines out of drm_colorop by
chaining them via the NEXT pointer. NEXT will point to
the next drm_colorop in the pipeline, or by 0 if we're
at the end of the pipeline.
Reviewed-by: Simon Ser
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Re
From: Harry Wentland
We want to be able to bypass each colorop at all times.
Introduce a new BYPASS boolean property for this.
Reviewed-by: Simon Ser
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Melissa Wen
---
v6:
From: Harry Wentland
Add a new drm_colorop with DRM_COLOROP_1D_CURVE with two subtypes:
DRM_COLOROP_1D_CURVE_SRGB_EOTF and DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF.
Reviewed-by: Simon Ser
Reviewed-by: Louis Chauvet
Signed-off-by: Harry Wentland
Co-developed-by: Alex Hung
Signed-off-by: Alex Hung
From: Harry Wentland
Add a read-only TYPE property. The TYPE specifies the colorop
type, such as enumerated curve, 1D LUT, CTM, 3D LUT, PWL LUT,
etc.
For now we're only introducing an enumerated 1D LUT type to
illustrate the concept.
Reviewed-by: Simon Ser
Reviewed-by: Louis Chauvet
Signed-of
From: Harry Wentland
This patches introduces a new drm_colorop mode object. This
object represents color transformations and can be used to
define color pipelines.
We also introduce the drm_colorop_state here, as well as
various helpers and state tracking bits.
Reviewed-by: Simon Ser
Signed-of
From: Harry Wentland
Add documentation for color pipeline API.
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Simon Ser
Reviewed-by: Melissa Wen
---
V9:
- Update documents according to new 3DLUT changes (Simon Ser)
- Spell out the behaviours
From: Harry Wentland
Debugging LUT math is much easier when we can unit test
it. Add kunit functionality to VKMS and add tests for
- get_lut_index
- lerp_u16
Reviewed-by: Louis Chauvet
Signed-off-by: Alex Hung
Signed-off-by: Harry Wentland
Cc: Arthur Grillo
Reviewed-by: Daniel Stone
---
v
From: Harry Wentland
CTM values are defined as signed-magnitude values. Add
a helper that converts from CTM signed-magnitude fixed
point value to the twos-complement value used by
drm_fixed.
Reviewed-by: Louis Chauvet
Signed-off-by: Harry Wentland
Reviewed-by: Daniel Stone
Reviewed-by: Meliss
This is an RFC set for a color pipeline API, along with implementations
in VKMS and amdgpu. It is tested with a set of IGT tests that can be
found at [1]. The IGT tests run a pixel-by-pixel comparison with an
allowable delta variation as the goal for these transformations is
perceptual correctness,
在 2025-08-14星期四的 17:04 -0500，Rob Herring写道：
> On Fri, Aug 15, 2025 at 12:40:42AM +0800, Icenowy Zheng wrote:
> > Verisilicon has a series of display controllers prefixed with DC
> > and
> > with self-identification facility like their GC series GPUs.
> >
> > Add a device tree binding for it.
> >
Add a new ite,it66122 compatible string to the IT66121 binding
documentation, since the two chips are practically same except for id
register difference.
Signed-off-by: Nishanth Menon
Acked-by: Krzysztof Kozlowski
---
Changes in V3:
* None.
V2: https://lore.kernel.org/all/20250813204106.580141-
Hi,
Add initial support for IT66122, which seems to be compatible to it66121
but probably has additional functionality.
BeagleY-AI uses this it66122 as the old part is no longer in production
as far as I understand.
Now, BeaglePlay uses it66121 at the moment, but at some point, it might
end up f
Drop the ftrace like dev_dbg() that checkpatch --strict complains about:
WARNING: Unnecessary ftrace-like logging - prefer using ftrace
+ dev_dbg(dev, "%s\n", __func__);
WARNING: Unnecessary ftrace-like logging - prefer using ftrace
+ dev_dbg(dev, "%s\n", __func__);
WARNING: Unnecess
The IT66122 is a pin compatible replacement for the IT66122. Based on
empirical testing, the new device looks to be compatible with IT66121.
However due to a lack of public data sheet at this time beyond overall
feature list[1] (which seems to add additional features vs ITT66121),
it is hard to det
The driver knows exactly which version of the chip is present since
the vid/pid is used to enforce a compatibility. Given that some
devices like IT66121 has potentially been replaced with IT66122 mid
production for many platforms, it makes no sense to use the vid/pid as
an enforcement for compatibi
On 8/6/25 17:52, Liu Ying wrote:
> devm_drm_bridge_alloc() returns ERR_PTR on failure instead of a
> NULL pointer, so use IS_ERR() to check the returned pointer.
> While at it, on failure, return ERR_CAST(dp) instead of
> ERR_PTR(-ENOMEM) in order not to depend on devm_drm_bridge_alloc()
> error co
Hi Marek,
On 2025/8/15 5:16, Marek Szyprowski wrote:
On 14.08.2025 16:33, Marek Szyprowski wrote:
On 14.08.2025 12:47, Damon Ding wrote:
PATCH 1 is a small format optimization for struct analogid_dp_device.
PATCH 2 is to perform mode setting in &drm_bridge_funcs.atomic_enable.
PATCH 3-6 are p
Hi Marek,
On 2025/8/14 22:33, Marek Szyprowski wrote:
On 14.08.2025 12:47, Damon Ding wrote:
PATCH 1 is a small format optimization for struct analogid_dp_device.
PATCH 2 is to perform mode setting in &drm_bridge_funcs.atomic_enable.
PATCH 3-6 are preparations for apply drm_bridge_connector hel
Hi,
On Wed, Aug 13, 2025 at 5:51 AM Pin-yen Lin wrote:
>
> Introduce a new HID quirk to indicate that this device has to be enabled
> after the panel's backlight is enabled, and update the driver data for
> the elan devices to enable this quirk. This cannot be a I2C HID quirk
> because the kernel
Hi,
On Wed, Aug 13, 2025 at 5:51 AM Pin-yen Lin wrote:
>
> @@ -230,6 +239,18 @@ void drm_panel_enable(struct drm_panel *panel)
> if (ret < 0)
> DRM_DEV_INFO(panel->dev, "failed to enable backlight: %d\n",
> ret);
> +
> + list_for_each_ent
On Fri, Aug 15, 2025 at 08:51:21AM +1000, Balbir Singh wrote:
> On 8/13/25 10:07, Mika Penttilä wrote:
> >
> > On 8/13/25 02:36, Balbir Singh wrote:
> >
> >> On 8/12/25 15:35, Mika Penttilä wrote:
> >>> Hi,
> >>>
> >>> On 8/12/25 05:40, Balbir Singh wrote:
> >>>
> MIGRATE_VMA_SELECT_COMPOUND
On Thu, Aug 07, 2025 at 09:10:58AM -0400, Sasha Levin wrote:
> Split the vmbind case into a separate helper function
> submit_lock_objects_vmbind() to fix objtool warning:
>
> drivers/gpu/drm/msm/msm.o: warning: objtool: submit_lock_objects+0x451:
> sibling call from callable instruction with
On Wed, Aug 13, 2025 at 11:13 PM Sumit Garg wrote:
>
> On Wed, Aug 13, 2025 at 08:02:51AM +0200, Jens Wiklander wrote:
> > Export the dma-buf heap functions to allow them to be used by the OP-TEE
> > driver. The OP-TEE driver wants to register and manage specific secure
> > DMA heaps with it.
> >
Hi,
On Wed, Jul 30, 2025 at 8:23 PM Brigham Campbell
wrote:
>
> Update driver to use the "multi" variants of MIPI functions which
> facilitate improved error handling and cleaner driver code.
>
> Remove information from a comment which was made obsolete by commit
> 994ea402c767 ("drm/panel: Rena
Hi,
On Wed, Jul 30, 2025 at 8:23 PM Brigham Campbell
wrote:
>
> Create mipi_dsi_dcs_read_multi(), which accepts a mipi_dsi_multi_context
> struct for improved error handling and cleaner panel driver code.
>
> Create mipi_dsi_dcs_write_var_seq_multi() and
> mipi_dsi_generic_write_var_seq_multi()
On Fri, Aug 08, 2025 at 11:50:27AM +0100, Daniel Stone wrote:
> Hi Karunika,
>
>
> On Thu, 7 Aug 2025 at 17:27, Karunika Choo wrote:
> > @@ -585,6 +615,9 @@ static int mmu_hw_do_operation_locked(struct
> > panthor_device *ptdev, int as_nr,
> > if (op != AS_COMMAND_UNLOCK)
> >
For the series:
Reviewed-by: Lyude Paul
On Fri, 2025-07-18 at 16:26 +0900, Alexandre Courbot wrote:
> This patch series introduces a number of improvements to nova-core's
> register!() macro in order to make it more useful to Nova itself, and to
> bring it closer to graduation into the wider ker
On 8/13/25 10:07, Mika Penttilä wrote:
>
> On 8/13/25 02:36, Balbir Singh wrote:
>
>> On 8/12/25 15:35, Mika Penttilä wrote:
>>> Hi,
>>>
>>> On 8/12/25 05:40, Balbir Singh wrote:
>>>
MIGRATE_VMA_SELECT_COMPOUND will be used to select THP pages during
migrate_vma_setup() and MIGRATE_PFN_
On Sat, Aug 09, 2025 at 12:16:19PM +0300, Dmitry Baryshkov wrote:
> From: Abhinav Kumar
>
> On a vast majority of Qualcomm chipsets DisplayPort controller can
> support several MST streams (up to 4x). To support MST these chipsets
> use up to 4 stream pixel clocks for the DisplayPort controller.
On Sat, 09 Aug 2025 12:16:18 +0300, Dmitry Baryshkov wrote:
> From: Abhinav Kumar
>
> DP controller schema documents assigned-clocks and
> assigned-clock-parents. However these assignments should not be a part
> of the ABI: there are no actual requirements on the order of the
> assignments, MST
On Sat, 09 Aug 2025 12:16:17 +0300, Dmitry Baryshkov wrote:
> From: Abhinav Kumar
>
> Add X1E80100 to the dp-controller bindings, it has DisplayPort
> controller similar to other platforms, but it uses its own compatible
> string.
>
> Signed-off-by: Abhinav Kumar
> Signed-off-by: Jessica Zhan
On Fri, Aug 15, 2025 at 12:40:42AM +0800, Icenowy Zheng wrote:
> Verisilicon has a series of display controllers prefixed with DC and
> with self-identification facility like their GC series GPUs.
>
> Add a device tree binding for it.
>
> Depends on the specific DC model, it can have either one o
On 14.08.2025 16:33, Marek Szyprowski wrote:
> On 14.08.2025 12:47, Damon Ding wrote:
>> PATCH 1 is a small format optimization for struct analogid_dp_device.
>> PATCH 2 is to perform mode setting in &drm_bridge_funcs.atomic_enable.
>> PATCH 3-6 are preparations for apply drm_bridge_connector hel
On 8/14/25 3:29 PM, Lizhi Hou wrote:
> Walking hardware contexts created by a process is duplicated in multiple
> spots. Add a function, amdxdna_hwctx_walk(), and replace all spots.
>
> hwctx_srcu and dev_lock are good enough to protect hardware context list.
> Remove hwctx_lock.
>
> Signed-off-b
Walking hardware contexts created by a process is duplicated in multiple
spots. Add a function, amdxdna_hwctx_walk(), and replace all spots.
hwctx_srcu and dev_lock are good enough to protect hardware context list.
Remove hwctx_lock.
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/aie2_ctx.c
://lore.kernel.org/linux-arm-msm/20250814-x1e80100-add-edp-hpd-v1-0-a52804db5...@linaro.org/
[1]:
https://lore.kernel.org/all/20250814-topic-x1e80100-t14s-oled-dp-brightness-v7-1-b3d7b4dfe...@linaro.org/
---
Changes in v7:
- Remove patch adding edp_hpd_active since now handled in Stephan's seri
X1 devices upstream earlier [1],
> so you could also just send v7 with just the second patch of your
> series.
Sure. I will do so and base my next version on your patchset.
> The bias-disable is really somewhat device-specific (what if there is no
> pull down on the device side and someone disconnects the panel
> entirely?), so I put it into each board DT separately like Johan
> requested on v5. We have the same for the PCIe pinctrl.
>
> Thanks,
> Stephan
>
> [1]:
> https://lore.kernel.org/linux-arm-msm/20250814-x1e80100-add-edp-hpd-v1-0-a52804db5...@linaro.org/T/
Hi Neil,
On Thu, 14 Aug 2025 at 15:16, Neil Armstrong wrote:
>
> From: Christopher Obbard
>
> According to the eDP specification (VESA Embedded DisplayPort Standard
> v1.4b, Section 3.3.10.2), if the value of DP_EDP_PWMGEN_BIT_COUNT is
> less than DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, the sink is req
On Fri, 15 Aug 2025 00:40:44 +0800, Icenowy Zheng wrote:
> T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired
> with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock
> and two reset controls.
>
> Add a device tree binding to it.
>
> Signed-off-by: Icenowy
On Fri, 15 Aug 2025 00:40:42 +0800, Icenowy Zheng wrote:
> Verisilicon has a series of display controllers prefixed with DC and
> with self-identification facility like their GC series GPUs.
>
> Add a device tree binding for it.
>
> Depends on the specific DC model, it can have either one or tw
On 8/14/25 6:38 PM, Akhil P Oommen wrote:
> On 8/14/2025 7:56 PM, Neil Armstrong wrote:
>> Hi,
>>
>> On 14/08/2025 13:22, Konrad Dybcio wrote:
>>> On 8/14/25 1:21 PM, Konrad Dybcio wrote:
On 7/31/25 12:19 PM, Konrad Dybcio wrote:
> On 7/25/25 10:35 AM, Neil Armstrong wrote:
>> The Adre
Hi Tvrtko,
On Wed, Aug 13, 2025 at 10:43:30PM +0100, Tvrtko Ursulin wrote:
> Hi Dave, Sima,
>
> Two display fixes for the RC cycle this week - one for FBC and one for PSR
> handling.
The following commits in drm-intel-next are for stable, so should be
also sent for -rc:
6cb52cba474b drm/i915/ic
As I am the author of this rewritten driver, it makes sense for me to be
the maintainer.
Confirm this in MAINTAINERS file.
Signed-off-by: Icenowy Zheng
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index eb84e36ded6d5..8c604de979680 100644
Lichee Pi 4A board features a HDMI Type-A connector connected to the
HDMI TX controller of TH1520 SoC.
Add a device tree node describing the connector, connect it to the HDMI
controller, and enable everything on this display pipeline.
Signed-off-by: Icenowy Zheng
---
.../boot/dts/thead/th1520-l
T-Head TH1520 SoC contains a Verisilicon DC8200 display controller
(called DPU in manual) and a Synopsys DesignWare HDMI TX controller.
Add device tree nodes to them.
Signed-off-by: Icenowy Zheng
---
arch/riscv/boot/dts/thead/th1520.dtsi | 70 +++
1 file changed, 70 inse
T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller (paired
with DesignWare HDMI TX PHY Gen2) that takes the "DP" output from the
display controller.
Add a driver for this controller utilizing the common DesignWare HDMI
code in the kernel.
Signed-off-by: Icenowy Zheng
---
MAINTAINE
T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired
with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock
and two reset controls.
Add a device tree binding to it.
Signed-off-by: Icenowy Zheng
---
.../display/bridge/thead,th1520-dw-hdmi.yaml | 120 +
This is a from-scratch driver targeting Verisilicon DC-series display
controllers, which feature self-identification functionality like their
GC-series GPUs.
Only DC8200 is being supported now, and only the main framebuffer is set
up (as the DRM primary plane). Support for more DC models and more
Verisilicon has a series of display controllers prefixed with DC and
with self-identification facility like their GC series GPUs.
Add a device tree binding for it.
Depends on the specific DC model, it can have either one or two display
outputs, and each display output could be set to DPI signal o
VeriSilicon is a Silicon IP vendor, which is the current owner of
Vivante series video-related IPs and Hantro series video codec IPs.
Add a vendor prefix for this company.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertion
This patchset tries to add a driver for Verisilicon DC8200 driver, and
demonstrates the driver on T-Head TH1520 with its HDMI output.
This display controller IP is used on StarFive JH7110 too, but as the
HDMI controller used there isn't as common as the DesignWare one, I
choose to use TH1520 in th
On 8/14/2025 7:56 PM, Neil Armstrong wrote:
> Hi,
>
> On 14/08/2025 13:22, Konrad Dybcio wrote:
>> On 8/14/25 1:21 PM, Konrad Dybcio wrote:
>>> On 7/31/25 12:19 PM, Konrad Dybcio wrote:
On 7/25/25 10:35 AM, Neil Armstrong wrote:
> The Adreno GPU Management Unit (GMU) can also scale DDR Ba
On 8/11/25 1:45 AM, Brian Masney wrote:
> The round_rate() clk ops is deprecated, so migrate this driver from
> round_rate() to determine_rate() using the Coccinelle semantic patch
> on the cover letter of this series.
>
> Signed-off-by: Brian Masney
> ---
> drivers/phy/rockchip/phy-rockchip-sam
Hello relevant maintainers,
On Wed, 6 Aug 2025 00:55:02 +0300
Andy Shevchenko wrote:
> On Fri, Aug 01, 2025 at 07:05:23PM +0200, Luca Ceresoli wrote:
> > Add an equivalent of list_first_entry_or_null() to obtain the last element
> > of a list.
>
> Acked-by: Andy Shevchenko
Thanks Andy!
How
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