On 7/3/2025 12:10 PM, Raag Jadav wrote:
On Thu, Jul 03, 2025 at 10:50:53AM +0530, Riana Tauro wrote:
On 7/3/2025 9:36 AM, Raag Jadav wrote:
On Wed, Jul 02, 2025 at 07:41:11PM +0530, Riana Tauro wrote:
Certain errors can cause the device to be wedged and may
require a vendor specific recover
On 02/07/2025 17:56, Gregory Williams wrote:
> From: Ronak Jain
>
> Add IOCTL support for the AIE run time operations listed below
> - Column Reset
> - Shim Reset
> - Enabling of column clock buffer
> - Zeroisation of Program and data memories
> - Disabling of column clock buffer
> - Enabling AXI
On 02/07/2025 17:56, Gregory Williams wrote:
> In the device tree, there will be device node for the AI engine device,
> and device nodes for the statically configured AI engine apertures.
No, describe the hardware, not DTS.
> Apertures are an isolated set of columns with in the AI engine device
Hi
Am 02.07.25 um 22:43 schrieb Krzysztof Kozlowski:
On 30/06/2025 10:40, Hans de Goede wrote:
No one asks to drop them from the driver. I only want specific front
compatible which will list and constrain the properties. It is not
contradictory to your statements, U-boot support, driver support
On 02/07/2025 17:56, Gregory Williams wrote:
> Define Versal power domain value macros.
>
> Signed-off-by: Gregory Williams
> ---
> include/dt-bindings/power/xlnx-versal-power.h | 55 +++
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC (an
On Thu, Jul 03, 2025 at 10:50:53AM +0530, Riana Tauro wrote:
> On 7/3/2025 9:36 AM, Raag Jadav wrote:
> > On Wed, Jul 02, 2025 at 07:41:11PM +0530, Riana Tauro wrote:
> > > Certain errors can cause the device to be wedged and may
> > > require a vendor specific recovery method to restore normal
> >
On Wed, Jun 18, 2025 at 09:03:00AM +0200, Jens Wiklander wrote:
> On Tue, Jun 17, 2025 at 1:32 PM Sumit Garg wrote:
> >
> > On Tue, Jun 10, 2025 at 03:13:50PM +0200, Jens Wiklander wrote:
> > > Add tee_shm_alloc_dma_mem() to allocate DMA memory. The memory is
> > > represented by a tee_shm object
On Wed, Jul 2, 2025 at 6:24 PM Christian König wrote:
>
> On 02.07.25 09:57, David Airlie wrote:
> >>>
> >>> It makes it easier now, but when we have to solve swapping, step one
> >>> will be moving all this code around to what I have now, and starting
> >>> from there.
> >>>
> >>> This just raise
On Thu, Jul 3, 2025 at 2:06 AM Shakeel Butt wrote:
>
> On Mon, Jun 30, 2025 at 02:49:27PM +1000, Dave Airlie wrote:
> > From: Dave Airlie
> >
> > This introduces 2 new statistics and 3 new memcontrol APIs for dealing
> > with GPU system memory allocations.
> >
> > The stats corresponds to the sam
Hi Dave & Sima,
Here's drm-intel-fixes towards 6.16-rc5.
Fix for mei interrupt handling on RT builds, two NULL deref fixes
and one memory leak fix.
Regards, Joonas
***
drm-intel-fixes-2025-07-03:
- Make mei interrupt top half irq disabled to fix RT builds
- Fix timeline left held on VMA alloc
On 7/3/2025 9:36 AM, Raag Jadav wrote:
On Wed, Jul 02, 2025 at 07:41:11PM +0530, Riana Tauro wrote:
Certain errors can cause the device to be wedged and may
require a vendor specific recovery method to restore normal
operation.
Add a recovery method 'WEDGED=vendor-specific' for such errors.
On Wed, Jul 02, 2025 at 07:41:11PM +0530, Riana Tauro wrote:
> Certain errors can cause the device to be wedged and may
> require a vendor specific recovery method to restore normal
> operation.
>
> Add a recovery method 'WEDGED=vendor-specific' for such errors. Vendors
> must provide additional r
On Thu, Jul 3, 2025 at 2:03 AM Shakeel Butt wrote:
>
> On Mon, Jun 30, 2025 at 02:49:36PM +1000, Dave Airlie wrote:
> > From: Dave Airlie
> >
> > This adds support for adding a obj cgroup to a buffer object,
> > and passing in the placement flags to make sure it's accounted
> > properly.
> >
> >
On 7/2/25 6:23 PM, Al Viro wrote:
> On Wed, Jul 02, 2025 at 05:19:12PM -0600, Jens Axboe wrote:
>>
>> On Wed, 02 Jul 2025 22:14:08 +0100, Al Viro wrote:
>>> When debugfs file has been created by debugfs_create_file_unsafe(),
>>> we do need the file_operations methods to use debugfs_file_{get,put}()
On Wed, Jul 02, 2025 at 08:00:44PM +0900, Alexandre Courbot wrote:
> diff --git a/Documentation/gpu/nova/core/falcon.rst
> b/Documentation/gpu/nova/core/falcon.rst
> new file mode 100644
> index
> ..33137082eb6c14cecda2fbe6fdb79e63ee9ca2e6
> --- /dev/null
>
On Wed, Jul 02, 2025 at 08:00:41PM +0900, Alexandre Courbot wrote:
> diff --git a/Documentation/gpu/nova/core/vbios.rst
> b/Documentation/gpu/nova/core/vbios.rst
> new file mode 100644
> index
> ..55d7dd4a6658c2a20cc5617f96b278bc4ec2ba17
> --- /dev/null
> +
On Wed, Jul 02, 2025 at 08:00:43PM +0900, Alexandre Courbot wrote:
> +FWSEC Memory Layout
> +---
> +The memory layout of the FWSEC image is as follows (this is using an GA-102
> +Ampere GPU as an example and could vary for future GPUs and is subject to
> change
> +completely, it is
On Wed, Jul 02, 2025 at 05:19:12PM -0600, Jens Axboe wrote:
>
> On Wed, 02 Jul 2025 22:14:08 +0100, Al Viro wrote:
> > When debugfs file has been created by debugfs_create_file_unsafe(),
> > we do need the file_operations methods to use debugfs_file_{get,put}()
> > to prevent concurrent removal; f
On Wed, Jul 02, 2025 at 08:00:42PM +0900, Alexandre Courbot wrote:
> diff --git a/Documentation/gpu/nova/core/devinit.rst
> b/Documentation/gpu/nova/core/devinit.rst
> new file mode 100644
> index
> ..70c819a96a00a0a27846e7e96525470d07721a10
> --- /dev/null
On 7/2/2025 9:52 AM, Badal Nilawar wrote:
Introduce a debug filesystem node to disable late binding fw reload
during the system or runtime resume. This is intended for situations
where the late binding fw needs to be loaded from user mode,
perticularly for validation purpose.
Note that xe kmd
On 7/2/2025 9:52 AM, Badal Nilawar wrote:
Search for late binding firmware binaries and populate the meta data of
firmware structures.
v2 (Daniele):
- drm_err if firmware size is more than max pay load size
- s/request_firmware/firmware_request_nowarn/ as firmware will
not be availabl
From: Boris Brezillon
We are going to add flags/properties that will impact the VA merging
ability. Instead of sprinkling tests all over the place in
__drm_gpuvm_sm_map(), let's add a helper aggregating all these checks
can call it for every existing VA we walk through in the
__drm_gpuvm_sm_map()
From: Boris Brezillon
We are about to pass more arguments to drm_gpuvm_sm_map[_ops_create](),
so, before we do that, let's pass arguments through a struct instead
of changing each call site every time a new optional argument is added.
Signed-off-by: Boris Brezillon
Signed-off-by: Caterina Shabl
From: Boris Brezillon
drm_gpuva_init() only has one internal user, and given we are about to
add new optional fields, it only add maintenance burden for no real
benefit, so let's kill the thing now.
Signed-off-by: Boris Brezillon
Signed-off-by: Caterina Shablia
---
include/drm/drm_gpuvm.h | 1
From: Boris Brezillon
Move the lock/flush_mem operations around the gpuvm_sm_map() calls so
we can implement true atomic page updates, where any access in the
locked range done by the GPU has to wait for the page table updates
to land before proceeding.
This is needed for vkQueueBindSparse(), so
From: Dave Airlie
This fixes a bunch of command hangs after runtime suspend/resume.
This fixes a regression caused by code movement in the commit below,
the commit seems to just change timings enough to cause this to happen
now, and adding the sleep seems to avoid it.
I've spent some time tryin
We want to use drmm_alloc_ordered_workqueue in Xe, let's make this work
a little better.
Matthew Brost (1):
drm: Simplify drmm_alloc_ordered_workqueue return
drivers/gpu/drm/vkms/vkms_crtc.c | 2 --
include/drm/drm_managed.h| 15 +--
2 files changed, 13 insertions(+), 4 de
Rather than returning ERR_PTR or NULL on failure, replace the NULL
return with ERR_PTR(-ENOMEM). This simplifies error handling at the
caller. While here, add kernel documentation for
drmm_alloc_ordered_workqueue.
Cc: Louis Chauvet
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/vkms/vkms_crtc
On Wed, 02 Jul 2025 22:14:08 +0100, Al Viro wrote:
> When debugfs file has been created by debugfs_create_file_unsafe(),
> we do need the file_operations methods to use debugfs_file_{get,put}()
> to prevent concurrent removal; for files created by debugfs_create_file()
> that is done in the wrapp
On Wed, Jul 02, 2025 at 07:14:43PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> Make the dp/hdmi_audio_* callback maintain the same parameter order as
> get_modes and edid_read: first the bridge, then the connector.
>
> Signed-off-by: Andy Yan
>
> Signed-off-by: Andy Yan
No extra empty line b
Several Link Layer tests (4.2.2.1-2, 4.2.2.7-9) fail because DPTX doesn't
read DPCD ADAPTER_CAP addresses (0x000F and 0x220F).
4.2.2.1 test states [1]:
"Fail1: Source DUT failed to read the DPCD Receiver Capability field
(DPCD:0h:Fh) through AUX_CH before link training."
4.2.2.2 test stat
From: Dongwon Kim
Host KVM/QEMU loses all graphics resources submitted by the guest OS
upon resumption from sleep or hibernation. This results in invalid
resource errors when the guest OS attempts to interact with the host
regarding those resources.
To address this issue, the virtio-gpu driver n
From: Dongwon Kim
This patch series introduces a freeze and restore mechanism for
the virtio-gpu driver:
First patch adds `virtgpu_freeze` and `virtgpu_restore` functions.
These functions handle the deletion of virtio queues before suspension and
their recreation during the restoration process.
From: Dongwon Kim
virtio device needs to delete before VM suspend happens
then reinitialize all virtqueues again upon resume
v2: 10ms sleep is added in virtgpu_freeze to avoid the situation
the driver is locked up during resumption.
v3: Plain 10ms delay (v2) is replaced with wait calls whic
On 28/06/25 19:42, Maíra Canal wrote:
Currently, an interrupt can be triggered during a GPU reset, which can
lead to GPU hangs and NULL pointer dereference in an interrupt context
as shown in the following trace:
[ 314.035040] Unable to handle kernel NULL pointer dereference at virtual
addre
On Wed, Jul 02, 2025 at 01:00:27PM +0200, Christian König wrote:
> Give TTM BOs a separate cleanup function.
>
> The next step in removing the TTM BO reference counting and replacing it
> with the GEM object reference counting.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdg
在 2025/6/27 23:45, Matthew Wilcox 写道:
On Fri, Jun 27, 2025 at 11:03:11AM +, 陈涛涛 Taotao Chen wrote:
diff --git a/fs/exfat/file.c b/fs/exfat/file.c
index 841a5b18e3df..fdc2fa1e5c41 100644
--- a/fs/exfat/file.c
+++ b/fs/exfat/file.c
@@ -532,10 +532,12 @@ int exfat_file_fsync(struct file *filp
在 2025/6/27 23:52, Matthew Wilcox 写道:
On Fri, Jun 27, 2025 at 11:03:11AM +, 陈涛涛 Taotao Chen wrote:
@@ -1399,13 +1400,10 @@ static int write_end_fn(handle_t *handle, struct inode
*inode,
}
/*
- * We need to pick up the new inode size which generic_commit_write gave us
- * `file' c
On Wed, Jul 02, 2025 at 10:22:16PM +0530, Badal Nilawar wrote:
> Do not review
Why?
Why don't we add this dependency here?
>
> Signed-off-by: Badal Nilawar
> ---
> drivers/gpu/drm/xe/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm
On Wed, Jul 02, 2025 at 10:22:12PM +0530, Badal Nilawar wrote:
> Reload late binding fw during runtime resume.
>
> Signed-off-by: Badal Nilawar
> ---
> v5: Flush worker in rpm suspend is not needed any more as
> xe_late_bind_fw_load gets the rpm ref before queuing worker
> to ensure worke
On Wed, Jul 02, 2025 at 10:22:13PM +0530, Badal Nilawar wrote:
> Reload late binding fw during resume from system suspend
>
> v2:
> - Unconditionally reload late binding fw (Rodrigo)
> - Flush worker during system suspend
>
> Cc: Rodrigo Vivi
> Signed-off-by: Badal Nilawar
Reviewed-by: Rod
All users outside of fs/debugfs/file.c are gone, in there we can just
fully split the wrappers for full and short cases and be done with that.
Signed-off-by: Al Viro
---
fs/debugfs/file.c | 87 ++---
include/linux/debugfs.h | 2 -
2 files changed, 38 in
When debugfs file has been created by debugfs_create_file_unsafe(),
we do need the file_operations methods to use debugfs_file_{get,put}()
to prevent concurrent removal; for files created by debugfs_create_file()
that is done in the wrappers that call underlying methods, so there's
no point whatsoe
On 30/06/2025 10:40, Hans de Goede wrote:
>>
>> No one asks to drop them from the driver. I only want specific front
>> compatible which will list and constrain the properties. It is not
>> contradictory to your statements, U-boot support, driver support. I
>> really do not see ANY argument why thi
On Mon, Jun 30, 2025 at 04:41:08PM +0200, Jocelyn Falempe wrote:
There is an unneeded blank line in the documentation of the function
ttm_bo_kmap_try_from_panic().
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202506290453.netxab7s-...@intel.com/
Fixes: 718370ff2
Hi Clement,
On Mon, Jun 30, 2025 at 02:55:15PM +0200, Clément Le Goffic wrote:
> Use the i2c-core-base APIs to allocate a DMA safe buffer when needed.
same here, I don't understand anything... you could have written
"do some coding" and it would have been the same :-)
Thanks,
Andi
Hi Clement,
On Mon, Jun 30, 2025 at 02:55:14PM +0200, Clément Le Goffic wrote:
> Fix an issue where the mapped DMA buffer was not unmapped.
"Fix an issue..." is too generic. Can you be more specific? Where
was it mapped? Where was it left unmapped?
Please, do consider that the user needs to unde
Hi Clement,
...
> @@ -118,7 +118,7 @@ int stm32_i2c_prep_dma_xfer(struct device *dev, struct
> stm32_i2c_dma *dma,
> dma->dma_len = len;
> chan_dev = dma->chan_using->device->dev;
>
> - dma->dma_buf = dma_map_single(chan_dev, buf, dma->dma_len,
> + dma->dma_buf = dma_map_si
Reload late binding fw during resume from system suspend
v2:
- Unconditionally reload late binding fw (Rodrigo)
- Flush worker during system suspend
Cc: Rodrigo Vivi
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/
On 24/06/2025 16:01, Alessio Belle wrote:
> The runtime PM might be left in error state if one of the callbacks
> returned an error, e.g. if the (auto)suspend callback failed following
> a firmware crash.
>
> When that happens, any further attempt to acquire or release a power
> reference will the
Adds AI Engine hardware reset functionality. Adds call to
initialize and teardown partitions. Partition initialize resets
columns, resets shim tiles, sets up AXIMM error reporting, ungates column
clocks, sets up partition isolation, and zeroizes all tile memories.
Teardown resets columns, resets sh
On 24/06/2025 15:22, Alessio Belle wrote:
> The GPU hard reset sequence calls pm_runtime_force_suspend() and
> pm_runtime_force_resume(), which according to their documentation should
> only be used during system-wide PM transitions to sleep states.
>
> The main issue though is that depending on s
Do not review
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
index f66e6d39e319..ef3f4807b0b3 100644
--- a/drivers/gpu/drm/xe/Kconfig
+++ b/drivers/gpu/drm/xe/Kconfig
@@ -45,6
Extract and print version info of the late binding binary.
v2: Some refinements (Daniele)
Signed-off-by: Badal Nilawar
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/xe/xe_late_bind_fw.c | 124 +
drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 3 +
drivers/gpu
From: Alexander Usyskin
Allow to bus client to obtain client mtu.
Signed-off-by: Alexander Usyskin
Signed-off-by: Badal Nilawar
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/misc/mei/bus.c | 13 +
include/linux/mei_cl_bus.h | 1 +
2 files changed, 14 insertions(+)
diff --g
Introduce a debug filesystem node to disable late binding fw reload
during the system or runtime resume. This is intended for situations
where the late binding fw needs to be loaded from user mode,
perticularly for validation purpose.
Note that xe kmd doesn't participate in late binding flow from u
Load late binding firmware
v2:
- s/EAGAIN/EBUSY/
- Flush worker in suspend and driver unload (Daniele)
v3:
- Use retry interval of 6s, in steps of 200ms, to allow
other OS components release MEI CL handle (Sasha)
v4:
- return -ENODEV if component not added (Daniele)
- parse and print statu
Reload late binding fw during runtime resume.
Signed-off-by: Badal Nilawar
---
v5: Flush worker in rpm suspend is not needed any more as
xe_late_bind_fw_load gets the rpm ref before queuing worker
to ensure worker completes lb fw loading.
---
drivers/gpu/drm/xe/xe_late_bind_fw.c | 2 +-
Search for late binding firmware binaries and populate the meta data of
firmware structures.
v2 (Daniele):
- drm_err if firmware size is more than max pay load size
- s/request_firmware/firmware_request_nowarn/ as firmware will
not be available for all possible cards
v3 (Daniele):
- init fir
Introducing xe_late_bind_fw to enable firmware loading for the devices,
such as the fan controller, during the driver probe. Typically,
firmware for such devices are part of IFWI flash image but can be
replaced at probe after OEM tuning.
This patch binds mei late binding component to enable firmwar
Introducing firmware late binding feature to enable firmware loading
for the devices, such as the fan controller and voltage regulator,
during the driver probe.
Typically, firmware for these devices are part of IFWI flash image but
can be replaced at probe after OEM tuning.
v2:
- Dropped voltage
From: Alexander Usyskin
Add late binding component driver.
It allows pushing the late binding configuration from, for example,
the Xe graphics driver to the Intel discrete graphics card's CSE device.
Signed-off-by: Alexander Usyskin
Signed-off-by: Badal Nilawar
Reviewed-by: Anshuman Gupta
---
On Mon, Jun 30, 2025 at 02:49:32PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> This enables all the backend code to use the list lru in memcg mode,
> and set the shrinker to be memcg aware.
>
> It adds the loop case for when pooled pages end up being reparented
> to a higher memcg group, t
The rationale for this change is that it's preferable to return
non-cleared memory instead of splitting up higher-order blocks as
this leads to more fragmented memory.
The driver will be able to clear the memory by itself if required
and the clear tracking will avoid the need for useless clearing
Functions drm_format_info, drm_modeset_lock, drm_ioctl_flags are not being
indexed in the documentation because there are structs with the same name
and sphinx is only indexing one of them, Added them to namespaces as a
workaround for suppressing the warnings and indexing the functions
This is a b
AFAICT the rationale for the loop is to:
1) try to allocate from the preferred order
2) if it fails, try higher orders (order + 1 -> max order)
3) if it fails, try smaller orders (order - 1 -> min order)
Steps 1 and 2 are covered by the loop going through [order, max_order].
Currently step 3 tries
On Wed, Jul 02, 2025 at 01:00:26PM +0200, Christian König wrote:
> Hi everyone,
>
> v2 of this patch set. I've either pushed or removed the other
> patches from v1, so only two remain.
>
> Pretty straight forward conversation and shouldn't result in any visible
> technical difference.
>
> Please
A vkcts test case is triggering a case where the drm buddy allocator
wastes lots of memory and performs badly:
dEQP-VK.memory.allocation.basic.size_8KiB.reverse.count_4000
For each memory pool type, the test will allocate 4000 8kB objects,
and then will release them. The alignment request is 25
Hi,
The first patch fixes a performance issue caused by a change in
drm_buddy ("drm/buddy: Implement tracking clear page feature").
It may be related to https://gitlab.freedesktop.org/drm/amd/-/issues/4260.
The other 2 patches are improvements based on my limited understanding
of the code and tha
On Mon, Jun 30, 2025 at 02:49:36PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> This adds support for adding a obj cgroup to a buffer object,
> and passing in the placement flags to make sure it's accounted
> properly.
>
> Signed-off-by: Dave Airlie
> ---
> drivers/gpu/drm/amd/amdgpu/amdg
On Mon, Jun 30, 2025 at 02:49:21PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> This uses the newly introduced per-node gpu tracking stats,
> to track GPU memory allocated via TTM and reclaimable memory in
> the TTM page pools.
>
> These stats will be useful later for system information and
Add support for AMD AI Engine on AMD Versal devices. AMD AI Engine is an
array based accelerator for applications like beamforming and machine
learning inference [1].
AI Engine device handle can have multiple apertures (groups of AI engine
columns) that are isolated from one another. At runtime, a
On Mon, Jun 30, 2025 at 02:49:27PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> This introduces 2 new statistics and 3 new memcontrol APIs for dealing
> with GPU system memory allocations.
>
> The stats corresponds to the same stats in the global vmstat,
> for number of active GPU pages, an
Creates tile memory information structure to store size and offsets for
core data and program memory and memory tile memory for AIEML.
Signed-off-by: Gregory Williams
---
drivers/accel/amd-ai-engine/ai-engine-aie.c | 39 +
drivers/accel/amd-ai-engine/ai-engine-aieml.c | 47 ++
From: Ronak Jain
Add IOCTL support for the AIE run time operations listed below
- Column Reset
- Shim Reset
- Enabling of column clock buffer
- Zeroisation of Program and data memories
- Disabling of column clock buffer
- Enabling AXI-MM error event
- Set L2 controller NPI INTR
Signed-off-by: Ro
Adds driver support for AIEML generation devices. The following modules
are enabled:
- Get tile type from location (support for new memory tile type)
- Clock state tracking and request and release of tiles
Signed-off-by: Gregory Williams
---
drivers/accel/amd-ai-engine/Makefile | 1 +
Adds support for getting current and setting AI engine array frequency.
Frequency values are validated by the driver then passed to the Versal
firmware driver. Support is also added to request and release tiles.
Requesting tiles will enable the clocks of the tiles requested,
releasing tiles will di
Define Versal power domain value macros.
Signed-off-by: Gregory Williams
---
include/dt-bindings/power/xlnx-versal-power.h | 55 +++
1 file changed, 55 insertions(+)
create mode 100644 include/dt-bindings/power/xlnx-versal-power.h
diff --git a/include/dt-bindings/power/xlnx-ver
From: Ronak Jain
Add support to query the QoS value on a device by using the PM IOCTL
EEMI API.
The caller only passes the node ID of the given device node and IOCTL
API will return the default QoS value as well as the current QoS
value.
Signed-off-by: Ronak Jain
Signed-off-by: Amanda Baze
--
Hi,
AI engine is a tile array based acceleration engine provided by AMD.
These engines provide high compute density for vector-based algorithms
and flexible custom compute and data movement. It has core tiles for
compute, memory tiles for local storage, and shim tiles to interface the
FPGA fabric
In the device tree, there will be device node for the AI engine device,
and device nodes for the statically configured AI engine apertures.
Apertures are an isolated set of columns with in the AI engine device
with their own address space and interrupt.
Signed-off-by: Gregory Williams
---
.../bi
> -Original Message-
> From: Dan Carpenter
> Sent: Wednesday, July 2, 2025 6:25 PM
> To: Kandpal, Suraj ; Maarten Lankhorst
>
> Cc: Maxime Ripard ; Thomas Zimmermann
> ; David Airlie ; Simona Vetter
> ; Nikula, Jani ; Deak, Imre
> ; Murthy, Arun R ; Dmitry
> Baryshkov ; Andy Yan ; Dave
https://bugzilla.kernel.org/show_bug.cgi?id=220304
Artem S. Tashkinov (a...@gmx.com) changed:
What|Removed |Added
Status|NEW |RESOLVED
Reso
Since commit 172efbb40333 ("AGP: Try unsupported AGP chipsets on x86-64
by default"), the AGP driver for AMD Opteron/Athlon64 CPUs has attempted
to bind to any PCI device possessing an AGP Capability.
Commit 6fd024893911 ("amd64-agp: Probe unknown AGP devices the right
way") subsequently reworked
On Wed, Jun 25, 2025 at 08:43:45PM +0200, Hans de Goede wrote:
> On 25-Jun-25 4:33 PM, Lukas Wunner wrote:
> > So how do you know that all of these unsupported devices have
> > PCI_CLASS_BRIDGE_HOST?
>
> The top of the driver says
>
> * This is a GART driver for the AMD Opteron/Athlon64 on-CPU n
Change the default register settings for Gen7 to mach Gen4 and
later. Gen7 currently uses the settings for Gen1, which is most
likely incorrect.
Using Gen4+ settings enables E2M linear-access modes in VGACRA2.
It appears to be related to the chip's PCIE2MBOX feature, which
is unused.
Signed-off-b
Move the POST code for each hardware generation into a separate source
file. Split some functions per gen, as necessary. Makes the code more
maintainable. Support for future hardware generations can now be added
easily in a new source file without interfering with existing code.
Gen3 and Gen5 shar
On Mon, 2025-06-30 at 11:04 -0300, Maíra Canal wrote:
> Hi Philipp,
>
> On 30/06/25 09:20, Philipp Stanner wrote:
> > On Mon, 2025-06-30 at 09:05 -0300, Maíra Canal wrote:
> > > Hi Philipp,
> > >
> > > On 30/06/25 08:53, Philipp Stanner wrote:
> > > > On Wed, 2025-06-18 at 11:47 -0300, Maíra Cana
On 7/2/2025 7:24 PM, Alex Deucher wrote:
> On Wed, Jul 2, 2025 at 3:24 AM Sam wrote:
>>
>>
>> On 2025/7/2 00:07, Alex Deucher wrote:
>>> On Tue, Jul 1, 2025 at 4:32 AM Christian König
>>> wrote:
On 01.07.25 10:03, Zhang, GuoQing (Sam) wrote:
> thaw() is called before writing the hibe
On Wed, Jul 2, 2025 at 3:24 AM Sam wrote:
>
>
> On 2025/7/2 00:07, Alex Deucher wrote:
> > On Tue, Jul 1, 2025 at 4:32 AM Christian König
> > wrote:
> >> On 01.07.25 10:03, Zhang, GuoQing (Sam) wrote:
> >>> thaw() is called before writing the hiberation image to swap disk. See
> >>> the doc here
Move POST code for Gen2+ and Gen1 to separate source files and
hide it in ast_2100_post() ans ast_2000_post(). With P2A
configuration, the POST logic for these chip generations has
been mingled in ast_init_dram_reg(). Hence, handle all generations
in a single change. The split simplifies both cases
Move POST code for Gen7+ to separate source file and hide it in
ast_2600_post(). There's not much going on here except for enabling
the DP transmitter chip.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/Makefile | 1 +
drivers/gpu/drm/ast/ast_2600.c | 46 +++
Certain errors can cause the device to be wedged and may
require a vendor specific recovery method to restore normal
operation.
Add a recovery method 'WEDGED=vendor-specific' for such errors. Vendors
must provide additional recovery documentation if this method
is used.
Cc: André Almeida
Cc: Chr
On 02.07.25 13:58, Arunpravin Paneer Selvam wrote:
> Hi Christian,
>
> On 7/2/2025 1:27 PM, Christian König wrote:
>> On 01.07.25 21:08, Arunpravin Paneer Selvam wrote:
>>> Set the dirty bit when the memory resource is not cleared
>>> during BO release.
>>>
>>> v2(Christian):
>>> - Drop the clea
Move POST code for Gen4+ to separate source file and hide it in
ast_2300_post(). With P2A configuration, it performs a full board
POST and enables the transmitter chip; otherwise it only enables the
transmitter chip.
Also fix coding style in several places. No changes to the overall
logic.
Signed
Duplicate ast_set_def_ext_reg() for individual chip generations
and move call it into per-chip source files. Remove the original
code. AST2100 and AST2500 reuse the function from earlier chips.
AST2600 appears to be incorrect as it uses an older function. Keep
this behavior for now.
Signed-off-by:
[cc += tglx, start of thread:
https://lore.kernel.org/r/f8ff40f35a9a5836d1371f60e85c09c5735e3c5e.1750497201.git.lu...@wunner.de/
]
On Wed, Jul 02, 2025 at 12:47:49PM +0200, Lukas Wunner wrote:
> On Mon, Jun 30, 2025 at 01:10:24PM +0200, Hans de Goede wrote:
> > ping? It would be good to get some c
Most of struct ast_dramstruct stores hardware state. Some index
values have known or special meaning. The known values are
- 0x - Terminal entry in the array
- 0xff00 - Delays the programming for usecs
- 0x0004 - Sets the type of DRAM
Add constants and helper macros for these cases. Also add
Set VGACRB6[5], which disables asynchronous sequencer resets via
VGASR0[1]. This was most likely an oversight when adding support
for Gen7. Aligns Gen7 with the earlier Gen4+.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_2600.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/
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