On Tue, Jun 17, 2025 at 12:48 PM Sumit Garg wrote:
>
> On Tue, Jun 10, 2025 at 03:13:49PM +0200, Jens Wiklander wrote:
> > From: Etienne Carriere
> >
> > Add a userspace API to create a tee_shm object that refers to a dmabuf
> > reference.
> >
> > Userspace registers the dmabuf file descriptor as
Hi Dave & Sima,
Here goes drm-intel-fixes towards v6.16-rc3. Two fixes.
MIPI vtotal programming fix for Broxton and build fix for GCOV+AutoFDO config.
Regards, Joonas
***
drm-intel-fixes-2025-06-18:
- Fix MIPI vtotal programming off by one on Broxton
- Fix PMU code for GCOV and AutoFDO enable
On 16.06.2025 17:40, Tomi Valkeinen wrote:
> On 12/06/2025 09:31, Marek Szyprowski wrote:
>> On 12.06.2025 07:49, Tomi Valkeinen wrote:
>>> On 11/06/2025 13:45, Marek Szyprowski wrote:
On 05.06.2025 19:15, Aradhya Bhatia wrote:
> From: Aradhya Bhatia
>
> Move the bridge pre_enable
Helper drm_crtc_vblank_helper_get_vblank_timestamp_internal() aims to
return the timestamp for end of vblank from the vblank_time pointer.
For vblank interrupt fired at the end of vblank, it's fine to subtract
time delta(as a positive value) according to scanout position from
etime to get the times
When we try to allocate a folio via alloc_hugetlb_folio_reserve(),
we need to ensure that there is an active reservation associated
with the allocation. Otherwise, our allocation request would fail
if there are no active reservations made at that moment against any
other allocations. This is becaus
Unlike the existing tests, this new test will create a memfd (backed
by hugetlb) and pin the folios in it (a small subset) before writing/
populating it with data. This is a valid use-case that invokes the
memfd_alloc_folio() kernel API and is expected to work unless there
aren't enough hugetlb fol
Currently, hugetlb_reserve_pages() returns a bool to indicate whether
the reservation map update for the range [from, to] was successful or
not. This is not sufficient for the case where the caller needs to
determine how many entries were updated for the range.
Therefore, have hugetlb_reserve_page
There are cases when we try to pin a folio but discover that it has
not been faulted-in. So, we try to allocate it in memfd_alloc_folio()
but the allocation request may not succeed if there are no active
reservations in the system at that instant.
Therefore, making a reservation (by calling hugetl
There are cases when we try to pin a folio but discover that it has
not been faulted-in. So, we try to allocate it in memfd_alloc_folio()
but there is a chance that we might encounter a fatal crash/failure
(VM_BUG_ON(!h->resv_huge_pages) in alloc_hugetlb_folio_reserve()) if
there are no active rese
On Tue, Jun 17, 2025 at 10:47:48PM +0300, Fedor Pchelkin wrote:
> Hello,
>
> there is a
>
> [0.579232] pci :00:00.2: Resources present before probing
>
> error message observed after
>
> commit 3be5fa236649da6404f1bca1491bf02d4b0d5cce
> Author: Lukas Wunner
> Date: Fri Apr 2
On Wed Jun 18, 2025 at 1:33 AM JST, Danilo Krummrich wrote:
> On Thu, Jun 12, 2025 at 11:01:43PM +0900, Alexandre Courbot wrote:
>> +/// Perform a DMA write according to `load_offsets` from `dma_handle`
>> into the falcon's
>> +/// `target_mem`.
>> +///
>> +/// `sec` is set if the
Hi all,
After merging the drm-misc tree, today's linux-next build (htmldocs)
produced these warnings:
include/drm/drm_device.h:40: warning: Function parameter or struct member 'pid'
not described in 'drm_wedge_task_info'
include/drm/drm_device.h:40: warning: Function parameter or struct member
在 6/16/2025 7:28 PM, Ling Xu 写道:
> 在 4/8/2025 4:14 PM, Srinivas Kandagatla 写道:
>>
>>
>> On 07/04/2025 10:13, Ling Xu wrote:
>>> 在 3/21/2025 1:11 AM, Srinivas Kandagatla 写道:
On 20/03/2025 09:14, Ling Xu wrote:
> The fastrpc driver has support for 5 types of remoteprocs. There are
Hi all,
After merging the drm-misc tree, today's linux-next build (htmldocs)
produced this warning:
Documentation/gpu/drm-uapi.rst:450: WARNING: Title underline too short.
Task information
--- [docutils]
Introduced by commit
cd37124b4093 ("drm/doc: Add a section about "Task infor
On Mon, Jun 16, 2025 at 01:46:42PM +0530, Aneesh Kumar K.V wrote:
> Xu Yilun writes:
>
> > On Wed, Jun 04, 2025 at 07:07:18PM +0530, Aneesh Kumar K.V wrote:
> >> Xu Yilun writes:
> >>
> >> > On Sun, Jun 01, 2025 at 04:15:32PM +0530, Aneesh Kumar K.V wrote:
> >> >> Xu Yilun writes:
> >> >>
> >
From: Sandeep Sheriker M
The current LVDS controller driver is hardcoded to map LVDS lanes to the
JEIDA format. Consequently, connecting an LVDS display that supports the
VESA format results in a distorted display due to the format mismatch.
Query the panel driver and set the appropriate format
From: Dave Airlie
This uses the newly introduced per-node gpu tracking stats,
to track GPU memory allocated via TTM and reclaimable memory in
the TTM page pools.
These stats will be useful later for system information and
later when mem cgroups are integrated.
Cc: Christian Koenig
Cc: Matthew
From: Dave Airlie
While discussing memcg intergration with gpu memory allocations,
it was pointed out that there was no numa/system counters for
GPU memory allocations.
With more integrated memory GPU server systems turning up, and
more requirements for memory tracking it seems we should start
c
Hi Laurent & Anusha,
On 18/06/25 5:06 am, Laurent Pinchart wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On Tue, Jun 17, 2025 at 10:36:34AM -0500, Anusha Srivatsa wrote:
>> Hey folks,
>>
>> Can someone please explain why the driver look
From: Dave Airlie
This is a fix/part revert for c21b039715ce
drm/nouveau/gsp: add hals for fbsr.suspend/resume()
For some undetermined reasons the above commit has caused a regression,
after a few s/r cycles, we start to get channel timeouts with robust
context 38 error (not defined in openrm).
Use Linux kernel-provided helper functions from :
- str_enabled_disabled()
to replace manual ternary expressions like:
enable ? "enabled" : "disabled"
This improves code readability and ensures consistency
with kernel coding style.
No functional change.
Signed-off-by: Yan Zhen
---
drivers/g
On Tue, Jun 17, 2025 at 10:36:34AM -0500, Anusha Srivatsa wrote:
> Hey folks,
>
> Can someone please explain why the driver looks for a panel here:
> https://elixir.bootlin.com/linux/v6.14.11/source/drivers/gpu/drm/bridge/
> microchip-lvds.c#L182 and doesnt use it or set it up anywhere?
>
> I bum
> On Jun 17, 2025, at 16:50, Alex Williamson wrote:
>
> On Tue, 17 Jun 2025 15:56:26 -0500
> Daniel Dadap wrote:
>
>>> On Tue, Jun 17, 2025 at 03:15:35PM -0500, Mario Limonciello wrote:
>>>
>>>
>>> On 6/17/25 2:20 PM, Daniel Dadap wrote:
On Tue, Jun 17, 2025 at 12:59:10PM -0500, Mari
Hi Dmitry,
> Subject: Re: [RFC PATCH v2 0/2] Virtio-GPU suspend and resume
>
> Hi,
>
> On 5/24/25 01:00, dongwon@intel.com wrote:
> > From: Dongwon Kim
> >
> > This patch series introduces a freeze and restore mechanism for the
> > virtio-gpu driver:
> >
> > First patch adds `virtgpu_freeze
On Sat, Jun 14, 2025 at 08:06:06PM +0200, Michal Wilczynski wrote:
> This patch series introduces support for the Imagination IMG BXM-4-64
> GPU found on the T-HEAD TH1520 SoC. A key aspect of this support is
> managing the GPU's complex power-up and power-down sequence, which
> involves multiple c
On Tue, 17 Jun 2025 15:56:26 -0500
Daniel Dadap wrote:
> On Tue, Jun 17, 2025 at 03:15:35PM -0500, Mario Limonciello wrote:
> >
> >
> > On 6/17/25 2:20 PM, Daniel Dadap wrote:
> > > On Tue, Jun 17, 2025 at 12:59:10PM -0500, Mario Limonciello wrote:
> > > > From: Mario Limonciello
> > > >
On Tue, 22 Apr 2025 23:17:01 +0300, Danila Tikhonov wrote:
> This patch series adds support for the Qualcomm Snapdragon 730/730G/732G
> (SM7150) platform along with the Google Pixel 4a (sunfish) device. Since
> the most critical drivers were submitted and applied in separate patch
> series, this
On 2025-06-17 15:45, David Francis wrote:
The kfd CRIU checkpoint ioctl would return an error if trying
to checkpoint a process with no kfd buffer objects.
This is a normal case and should not be an error.
Signed-off-by: David Francis
This patch is
Reviewed-by: Felix Kuehling
---
driv
On Tue, Jun 17, 2025 at 03:15:35PM -0500, Mario Limonciello wrote:
>
>
> On 6/17/25 2:20 PM, Daniel Dadap wrote:
> > On Tue, Jun 17, 2025 at 12:59:10PM -0500, Mario Limonciello wrote:
> > > From: Mario Limonciello
> > >
> > > On a mobile system with an AMD integrated GPU + NVIDIA discrete GPU t
On Tue, Jun 17, 2025 at 09:37:28PM +0200, Thomas Hellström wrote:
> On Tue, 2025-06-17 at 10:04 -0700, Matthew Brost wrote:
> > On Tue, Jun 17, 2025 at 04:55:26PM +0200, Thomas Hellström wrote:
> > > On Tue, 2025-06-17 at 20:17 +0530, Ghimiray, Himal Prasad wrote:
> > > >
> > > >
> > > > On 17-06
On 2025-06-17 15:45, David Francis wrote:
CRIU restore of drm buffer objects requires the ability to create
or import a buffer object with a specific gem handle.
Add new drm ioctl DRM_IOCTL_GEM_CHANGE_HANDLE, which takes
the gem handle of an object and moves that object to a
specified new gem ha
On 6/17/25 2:22 PM, Alex Williamson wrote:
On Tue, 17 Jun 2025 12:59:10 -0500
Mario Limonciello wrote:
From: Mario Limonciello
On a mobile system with an AMD integrated GPU + NVIDIA discrete GPU the
AMD GPU is not being selected by some desktop environments for any
rendering tasks. This i
On 6/17/25 2:20 PM, Daniel Dadap wrote:
On Tue, Jun 17, 2025 at 12:59:10PM -0500, Mario Limonciello wrote:
From: Mario Limonciello
On a mobile system with an AMD integrated GPU + NVIDIA discrete GPU the
AMD GPU is not being selected by some desktop environments for any
rendering tasks. This
On Thu, Jun 12, 2025 at 11:01:28PM +0900, Alexandre Courbot wrote:
> Hi everyone,
>
> The feedback on v4 has been (hopefully) addressed. I guess the main
> remaining unknown is the direction of the `num` module ; for this
> iteration, following the received feedback I have eschewed the extension
>
Hello,
there is a
[0.579232] pci :00:00.2: Resources present before probing
error message observed after
commit 3be5fa236649da6404f1bca1491bf02d4b0d5cce
Author: Lukas Wunner
Date: Fri Apr 25 11:24:21 2025 +0200
Revert "iommu/amd: Prevent binding other PCI drivers to
Add new ioctl DRM_IOCTL_AMDGPU_CRIU_MAPPING_INFO, which
returns a list of mappings associated with a given bo, along with
their positions and offsets.
Signed-off-by: David Francis
---
drivers/gpu/drm/amd/amdgpu/amdgpu_criu.c | 96
drivers/gpu/drm/amd/amdgpu/amdgpu_criu.h
The kfd CRIU checkpoint ioctl would return an error if trying
to checkpoint a process with no kfd buffer objects.
This is a normal case and should not be an error.
Signed-off-by: David Francis
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Add new ioctl DRM_IOCTL_AMDGPU_CRIU_BO_INFO.
This ioctl returns a list of bos with their handles, sizes,
and flags and domains.
This ioctl is meant to be used during CRIU checkpoint and
provide information needed to reconstruct the bos
in CRIU restore.
Signed-off-by: David Francis
---
drivers/
CRIU restore of drm buffer objects requires the ability to create
or import a buffer object with a specific gem handle.
Add new drm ioctl DRM_IOCTL_GEM_CHANGE_HANDLE, which takes
the gem handle of an object and moves that object to a
specified new gem handle.
This ioctl needs to call drm_prime_re
This patch series adds support for CRIU checkpointing of processes that
share memory with the amdgpu dmabuf interface.
This v7 splits the bo and mapping info patches and uses the valid and
invalid lists instead of the rb tree.
A single macro that iterates over both lists is in the works.
On Tue, 2025-06-17 at 10:04 -0700, Matthew Brost wrote:
> On Tue, Jun 17, 2025 at 04:55:26PM +0200, Thomas Hellström wrote:
> > On Tue, 2025-06-17 at 20:17 +0530, Ghimiray, Himal Prasad wrote:
> > >
> > >
> > > On 17-06-2025 18:41, Thomas Hellström wrote:
> > > > On Tue, 2025-06-17 at 18:25 +0530
On Tue, 17 Jun 2025 at 17:11, Jyothi Kumar Seerapu
wrote:
>
>
>
> On 5/30/2025 10:12 PM, Dmitry Baryshkov wrote:
> > On Fri, May 30, 2025 at 07:36:05PM +0530, Jyothi Kumar Seerapu wrote:
> >>
> >>
> >> On 5/21/2025 6:15 PM, Dmitry Baryshkov wrote:
> >>> On Wed, May 21, 2025 at 03:58:48PM +0530, Jy
On Tue, 2025-06-17 at 10:09 -0700, Matthew Brost wrote:
> On Fri, Jun 13, 2025 at 04:02:19PM +0200, Thomas Hellström wrote:
> > Add runtime PM since we might call populate_mm on a foreign device.
> >
> > v3:
> > - Fix a kerneldoc failure (Matt Brost)
> > - Revert the bo type change from device to
On Tue, 17 Jun 2025 12:59:10 -0500
Mario Limonciello wrote:
> From: Mario Limonciello
>
> On a mobile system with an AMD integrated GPU + NVIDIA discrete GPU the
> AMD GPU is not being selected by some desktop environments for any
> rendering tasks. This is because neither GPU is being treated
On Tue, Jun 17, 2025 at 12:59:10PM -0500, Mario Limonciello wrote:
> From: Mario Limonciello
>
> On a mobile system with an AMD integrated GPU + NVIDIA discrete GPU the
> AMD GPU is not being selected by some desktop environments for any
> rendering tasks. This is because neither GPU is being tre
On 6/17/25 1:56 PM, Rodrigo Siqueira wrote:
> On 06/13, Mario Limonciello wrote:
>> On 6/13/2025 9:58 AM, Melissa Wen wrote:
>>> From: Rodrigo Siqueira
>>>
>>> Since DC is a shared code, this commit introduces a new file to work as
>>> a mid-layer in DC for the edid manipulation.
>>>
>>> v3:
>>> -
On 06/13, Mario Limonciello wrote:
> On 6/13/2025 9:58 AM, Melissa Wen wrote:
> > From: Rodrigo Siqueira
> >
> > Since DC is a shared code, this commit introduces a new file to work as
> > a mid-layer in DC for the edid manipulation.
> >
> > v3:
> > - rebase on top of asdn
> Can you put changelo
reedr...@lists.freedesktop.org
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
---
drivers/gpu/drm/msm/dp/dp_panel.c | 2 ++
1 file changed, 2 insertions(+)
--- linux-next-20250617.orig/drivers/gpu/drm/msm/dp/dp_panel.c
+++ linux-next-20250617/drivers/gpu/drm/msm/dp/dp_pan
On Tue, 17 Jun 2025 12:59:06 -0500
Mario Limonciello wrote:
> From: Mario Limonciello
>
> The inline pci_is_display() helper does the same thing. Use it.
>
> Suggested-by: Bjorn Helgaas
> Signed-off-by: Mario Limonciello
> ---
> drivers/vfio/pci/vfio_pci_igd.c | 3 +--
> 1 file changed, 1
From: Mario Limonciello
The inline pci_is_display() helper does the same thing. Use it.
Suggested-by: Bjorn Helgaas
Signed-off-by: Mario Limonciello
---
sound/hda/hdac_i915.c | 2 +-
sound/pci/hda/hda_intel.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/sound/
From: Mario Limonciello
On a mobile system with an AMD integrated GPU + NVIDIA discrete GPU the
AMD GPU is not being selected by some desktop environments for any
rendering tasks. This is because neither GPU is being treated as
"boot_vga" but that is what some environments use to select a GPU [1]
From: Mario Limonciello
The inline pci_is_display() helper does the same thing. Use it.
Suggested-by: Bjorn Helgaas
Signed-off-by: Mario Limonciello
---
drivers/iommu/intel/iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu
From: Mario Limonciello
The inline pci_is_display() helper does the same thing. Use it.
Suggested-by: Bjorn Helgaas
Signed-off-by: Mario Limonciello
---
drivers/gpu/vga/vga_switcheroo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/vga/vga_switcheroo.c b/dri
From: Mario Limonciello
The inline pci_is_display() helper does the same thing. Use it.
Suggested-by: Bjorn Helgaas
Signed-off-by: Mario Limonciello
---
drivers/vfio/pci/vfio_pci_igd.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/vfio/pci/vfio_pci_igd.c b/dri
From: Mario Limonciello
Several places in the kernel do class shifting to match whether a
PCI device is display class. Introduce a helper for those places to
use.
Signed-off-by: Mario Limonciello
---
include/linux/pci.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/incl
From: Mario Limonciello
On a mobile system with an AMD integrated GPU + NVIDIA discrete GPU the
AMD GPU is not being selected by some desktop environments for any
rendering tasks. This is because the neither GPU is being treated as
"boot_vga" but that is what some environments use to select a GPU
On Fri, Jun 13, 2025 at 04:02:19PM +0200, Thomas Hellström wrote:
> Add runtime PM since we might call populate_mm on a foreign device.
>
> v3:
> - Fix a kerneldoc failure (Matt Brost)
> - Revert the bo type change from device to kernel (Matt Brost)
>
> Signed-off-by: Thomas Hellström
> ---
> d
On Fri, Jun 13, 2025 at 04:02:18PM +0200, Thomas Hellström wrote:
> Add an operation to populate a part of a drm_mm with device
> private memory. Clarify how migration using it is intended
> to work.
>
> v3:
> - Kerneldoc fixes and updates (Matt Brost).
>
> Signed-off-by: Thomas Hellström
> Revi
On Tue, Jun 17, 2025 at 04:55:26PM +0200, Thomas Hellström wrote:
> On Tue, 2025-06-17 at 20:17 +0530, Ghimiray, Himal Prasad wrote:
> >
> >
> > On 17-06-2025 18:41, Thomas Hellström wrote:
> > > On Tue, 2025-06-17 at 18:25 +0530, Ghimiray, Himal Prasad wrote:
> > > >
> > > >
> > > > On 13-06-2
On Thu, Jun 12, 2025 at 11:01:43PM +0900, Alexandre Courbot wrote:
> +/// Perform a DMA write according to `load_offsets` from `dma_handle`
> into the falcon's
> +/// `target_mem`.
> +///
> +/// `sec` is set if the loaded firmware is expected to run in secure
> mode.
> +fn dma
On 6/17/25 7:09 AM, Dave Airlie wrote:
From: Dave Airlie
This seems to remove some random behaviour around suspend/resume
operations, and ordering of memory allocations.
What do you mean with ordering of memory allocations?
Cc: sta...@vger.kernel.org
I think we should add:
Fixes: 176fdc
On Thu, Jun 12, 2025 at 3:24 AM Francesco Dolcini
wrote:
> Hello all,
>
> Commit de04bb0089a9 ("drm/panel/panel-simple: Use the new allocation in
> place of devm_kzalloc()")
> from 6.16-rc1 introduced a regression with this warning during probe
> with panel dpi described in the DT.
>
> A revert s
Hey folks,
Can someone please explain why the driver looks for a panel here:
https://elixir.bootlin.com/linux/v6.14.11/source/drivers/gpu/drm/bridge/microchip-lvds.c#L182
and doesnt use it or set it up anywhere?
I bumped into this while working on converting of_drm_find_panel() callers
and the lv
On Tue, Jun 17, 2025 at 05:33:20AM +, Borah, Chaitanya Kumar wrote:
>
>
> > -Original Message-
> > From: Pekka Paalanen
> > Sent: Monday, June 16, 2025 7:02 PM
> > To: Borah, Chaitanya Kumar
> > Cc: Alex Hung ; dri-devel@lists.freedesktop.org; amd-
> > g...@lists.freedesktop.org; wa
On Tue, Jun 17, 2025 at 04:25:09PM +0200, Simona Vetter wrote:
> On Tue, Jun 17, 2025 at 04:10:40PM +0200, Danilo Krummrich wrote:
> > On Tue, Jun 17, 2025 at 03:51:33PM +0200, Simona Vetter wrote:
> > > On Thu, Jun 12, 2025 at 04:49:54PM +0200, Philipp Stanner wrote:
> > > > + * NOTE that sharing
Register the on-die nvm device with the mtd subsystem.
Refcount nvm object on _get and _put mtd callbacks.
For erase operation address and size should be 4K aligned.
For write operation address and size has to be 4bytes aligned.
CC: Rodrigo Vivi
CC: Lucas De Marchi
Reviewed-by: Raag Jadav
Acked
From: Reuven Abliyev
Erase command is slow on discrete graphics storage
and may overshot PCI completion timeout.
BMG introduces the ability to have non-posted erase.
Add driver support for non-posted erase with polling
for erase completion.
Reviewed-by: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Sign
Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Reviewed-by: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4 +++
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +
GSC NVM controller HW errors on quad access overlapping 1K border.
Align 64bit read and write to avoid readq/writeq over 1K border.
Reviewed-by: Raag Jadav
Acked-by: Miquel Raynal
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd_intel_dg.c | 35 ++
1 fil
Enable access to internal non-volatile memory on DGFX
with GSC/CSC devices via a child device.
The nvm child device is exposed via auxiliary bus.
Reviewed-by: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/
Implement read(), erase() and write() functions.
CC: Lucas De Marchi
CC: Rodrigo Vivi
Reviewed-by: Raag Jadav
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Co-developed-by: Vitaly Lubart
Signed-off-by: Vitaly Lubart
Signed-off-by: Alexander Usyskin
--
In intel-dg, there is no access to the spi controller,
the information is extracted from the descriptor region.
CC: Lucas De Marchi
Reviewed-by: Raag Jadav
Reviewed-by: Rodrigo Vivi
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander U
Add auxiliary driver for intel discrete graphics
non-volatile memory device.
CC: Lucas De Marchi
Reviewed-by: Raag Jadav
Reviewed-by: Rodrigo Vivi
Acked-by: Miquel Raynal
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
MAINTAINERS
Add driver for access to Intel discrete graphics card
internal NVM device.
Expose device on auxiliary bus by i915 and Xe drivers and
provide mtd driver to register this device with MTD framework.
This is a rewrite of "drm/i915/spi: spi access for discrete graphics"
and "spi: add driver for Intel d
On Tue, 2025-06-17 at 20:17 +0530, Ghimiray, Himal Prasad wrote:
>
>
> On 17-06-2025 18:41, Thomas Hellström wrote:
> > On Tue, 2025-06-17 at 18:25 +0530, Ghimiray, Himal Prasad wrote:
> > >
> > >
> > > On 13-06-2025 19:32, Thomas Hellström wrote:
> > > > From: Matthew Brost
> > > >
> > > > T
Em 17/06/2025 10:07, Christian König escreveu:
On 6/17/25 14:49, André Almeida wrote:
To notify userspace about which task (if any) made the device get in a
wedge state, make use of drm_wedge_task_info parameter, filling it with
the task PID and name.
Signed-off-by: André Almeida
Reviewed-by
On 17-06-2025 18:41, Thomas Hellström wrote:
On Tue, 2025-06-17 at 18:25 +0530, Ghimiray, Himal Prasad wrote:
On 13-06-2025 19:32, Thomas Hellström wrote:
From: Matthew Brost
The migration functionality and track-keeping of per-pagemap VRAM
mapped to the CPU mm is not per GPU_vm, but rat
On Tue, 3 Jun 2025 10:49:31 +0100
Ashley Smith wrote:
> This fixes a bug where if we timeout after a suspend and the termination
> fails, due to waiting on a fence that will never be signalled for
> example, we do not resume the group correctly. The fix forces a reset
> for groups that are not t
On 2025-06-17 07:04, Maíra Canal wrote:
> Hi Alex,
>
> On 17/06/25 01:17, Alex Hung wrote:
>> From: Harry Wentland
>>
>> While working on the CTM implementation of VKMS I had to ascertain
>> myself of a few assumptions. One of those is whether drm_fixed.h
>> treats its numbers using signed-magnit
f) -> *mut T {
> pub const fn raw_get(this: *const Self) -> *mut T {
>
> UnsafeCell::raw_get(this.cast::>>()).cast::()
> }
> +
> +/// The opposite operation of [`Opaque::raw_get`].
> +pub const fn from_raw(this: *const T) -> *const Self {
> +this.cast()
> +}
> }
>
> /// Types that are _always_ reference counted.
>
> ---
> base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494
> change-id: 20250617-opaque-from-raw-ac5b8ef6faa2
>
> Best regards,
> --
> Alice Ryhl
Add support for DRM_FORMAT_C8 to vesadrm. The new pixel-format
description PIXEL_FORMAT_C8 describes the layout. Vesadrm's helpers
vesadrm_fill_palette_lut() and vesadrm_load_palette_lut() set the
hardware palette according to the CRTC's output format.
The driver emulates XRGB by converting th
List the conversion from XRGB-to-RGB332 in drm_fb_blit(), so that
drivers based on sysfb-helpers can use it.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_format_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/drm_format_helper.c
b/drivers/gpu/drm/
Add helper drm_crtc_fill_palette_332(), which fills palettes with
RGB332 color data. Each color in RGB332 format serves as an index
into an 8-bit palette that stores the corresponding component-based
colors.
Vesadrm will use the new helper to emulate RGB formats on top of
framebuffers in C8 format
Use the color format stored in struct drm_sysfb_crtc_state for
color-format conversion instead of the scanout-buffer format
announced by firmware. Currently, both values are identical.
This will allow drivers to modify the CRTC's output format to a
certain extend. Specifically, vesadrm will be abl
Add screen_info_pixel_format(), which converts a screen_info's
information about the color format to struct pixel_format. The encoding
within the screen_info structure is complex and therefore prone to
errors. Later patches will convert callers to use the pixel format.
Signed-off-by: Thomas Zimmer
Distiguish between component-based formats and 'the rest' in vesadrm's
color management. Scanout buffers with component-based format allow
for gamma correction. Palette-based formats (i.e., 'the rest') require
palette setup.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/sysfb/vesadrm.c |
Rename vesadrm's gamma helpers in preparation of the upcoming support
for color palettes. Gamma correction and color palettes share the same
hardware features, but the driver's old naming only indicated support
for gamma LUTs.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/sysfb/vesadrm.c
Add helpers that compare two pixel-format descriptions against
each other.
Signed-off-by: Thomas Zimmermann
---
include/video/pixel_format.h | 58
1 file changed, 58 insertions(+)
diff --git a/include/video/pixel_format.h b/include/video/pixel_format.h
index
VESA provides a wide range ot 8-bit palette modes. Add support to
vesadrm. For compatibility with common userspace the driver also
provides XRGB on top of the palettized output.
Patches 1 to 3 prepare screen_info and struct pixel_format for
indexed formats. This cleans up the code for other dr
Convert drm_sysfb_get_format_si() to lookup the screen_info color
format as struct pixel_format with screen_info_pixel_format(). Then
search the list of given formats for the screen_info format with
pixel_format_equal().
Replaces custom code with helpers. The pixel-compare helper
pixel_format_equa
Em 17/06/2025 10:22, André Almeida escreveu:
Em 17/06/2025 10:07, Christian König escreveu:
On 6/17/25 14:49, André Almeida wrote:
To notify userspace about which task (if any) made the device get in a
wedge state, make use of drm_wedge_task_info parameter, filling it with
the task PID and name
On Tue, Jun 17, 2025 at 04:10:40PM +0200, Danilo Krummrich wrote:
> On Tue, Jun 17, 2025 at 03:51:33PM +0200, Simona Vetter wrote:
> > On Thu, Jun 12, 2025 at 04:49:54PM +0200, Philipp Stanner wrote:
> > > + * NOTE that sharing &struct drm_sched_init_args.submit_wq with the
> > > driver
> > > + *
On Tue, 17 Jun 2025 at 16:11, Simona Vetter wrote:
>
> On Fri, Jun 13, 2025 at 04:10:22PM +0200, Simona Vetter wrote:
> > On Fri, Jun 13, 2025 at 04:04:46PM +0200, Simona Vetter wrote:
> > > On Fri, Jun 13, 2025 at 03:12:01PM +0200, Christian König wrote:
> > > > It is possible through flink or IO
On 5/30/2025 9:23 PM, Dmitry Baryshkov wrote:
On Fri, 30 May 2025 at 17:05, Jyothi Kumar Seerapu
wrote:
On 5/9/2025 11:48 AM, Jyothi Kumar Seerapu wrote:
On 5/6/2025 5:02 PM, Dmitry Baryshkov wrote:
On Tue, May 06, 2025 at 04:48:43PM +0530, Jyothi Kumar Seerapu wrote:
GSI hardware ge
Only set PMI fields if the screen_info's Vesa PM segment has been
set. Vesa PMI is the power-management interface. It also provides
means to set the color palette. The interface is optional, so not
all VESA graphics cards support it. Print vesafb's warning [1] if
the hardware palette cannot be set
On 5/30/2025 10:12 PM, Dmitry Baryshkov wrote:
On Fri, May 30, 2025 at 07:36:05PM +0530, Jyothi Kumar Seerapu wrote:
On 5/21/2025 6:15 PM, Dmitry Baryshkov wrote:
On Wed, May 21, 2025 at 03:58:48PM +0530, Jyothi Kumar Seerapu wrote:
On 5/9/2025 9:31 PM, Dmitry Baryshkov wrote:
On 09/05
On Fri, Jun 13, 2025 at 04:10:22PM +0200, Simona Vetter wrote:
> On Fri, Jun 13, 2025 at 04:04:46PM +0200, Simona Vetter wrote:
> > On Fri, Jun 13, 2025 at 03:12:01PM +0200, Christian König wrote:
> > > It is possible through flink or IOCTLs like MODE_GETFB2 to create
> > > multiple handles for the
On Tue, Jun 17, 2025 at 03:51:33PM +0200, Simona Vetter wrote:
> On Thu, Jun 12, 2025 at 04:49:54PM +0200, Philipp Stanner wrote:
> > + * NOTE that sharing &struct drm_sched_init_args.submit_wq with the driver
> > + * theoretically can deadlock. It must be guaranteed that submit_wq never
> > has
>
Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Reviewed-by: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4 +++
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +
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