Hi,
On 5/24/25 01:00, dongwon@intel.com wrote:
> From: Dongwon Kim
>
> This patch series introduces a freeze and restore mechanism for
> the virtio-gpu driver:
>
> First patch adds `virtgpu_freeze` and `virtgpu_restore` functions.
> These functions handle the deletion of virtio queues befor
This patch fixes documentation build warnings:
- WARNING: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:1068
struct member 'mcm' not described in 'mpc_funcs'
- WARNING: ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:1068
struct member 'rmcm' not described in 'mpc_funcs'
Signed-off-by: Abdelrahman
On Thu Jun 12, 2025 at 4:01 PM CEST, Alexandre Courbot wrote:
> Add an equivalent to the `fls` (Find Last Set bit) C function to Rust
> unsigned types.
Have you tried to upstream this?
> It is to be first used by the nova-core driver.
>
> Signed-off-by: Alexandre Courbot
> ---
> rust/kernel/num
On Thu Jun 12, 2025 at 4:01 PM CEST, Alexandre Courbot wrote:
> diff --git a/rust/kernel/num.rs b/rust/kernel/num.rs
> new file mode 100644
> index
> ..ee0f67ad1a89e69f5f8d2077eba5541b472e7d8a
> --- /dev/null
> +++ b/rust/kernel/num.rs
> @@ -0,0 +1,173 @@
>
ware of any recent progress on this particular set from Keith.
I would be happy to collaborate with you or take over the work of
getting it ready for merging.
I also have a StarFive Vision Five 2 board, and my plan was to get the
driver working for the JH7110 first. The only thing different for the
TH1520 SoC is the HDMI driver, which could be added later.
However, the main blocker is the lack of public documentation for the
Verisilicon DC8200 controller. The official StarFive documentation
portal [2] mentions two essential documents: "DC8200 Dual Display
Controller DPU IP Exposed Accessible Registers" and "DC8200 Dual Display
Controller IP Hardware Features."
Pinging the StarFive developers on this thread: would it be possible to
make these documents available? Access to them is critical for us to
successfully move this driver forward.
[1] -
https://lore.kernel.org/all/20250614-apr_14_for_sending-v4-0-8e3945c81...@samsung.com/
[2] - https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/detail_info_display.html
>
> Kind regards,
> Maud
>
Best regards,
--
Michal Wilczynski
On 6/12/25 11:19 PM, Akhil P Oommen wrote:
> On 6/12/2025 5:32 PM, Jens Glathe wrote:
>> On 6/11/25 13:15, Akhil P Oommen wrote:
>>
>>> Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
>>> version). X1-45 is a smaller version of X1-85 with lower core count and
>>> smaller memories. F
Update the img,powervr-rogue.yaml to include the T-HEAD TH1520 SoC's
specific GPU compatible string.
The thead,th1520-gpu compatible, along with its full chain
img,img-bxm-4-64, and img,img-rogue, is added to the
list of recognized GPU types.
The power-domains property requirement for img,img-bxm
Add the "gpu-clkgen" reset property to the AON device tree node. This
allows the AON power domain driver to detect the capability to power
sequence the GPU and spawn the necessary pwrseq-thead-gpu auxiliary
driver for managing the GPU's complex power sequence.
This commit also adds the prerequisit
Extend the TH1520 AON to describe the GPU clkgen reset line, required
for proper GPU clock and reset sequencing.
The T-HEAD TH1520 GPU requires coordinated management of two clocks
(core and sys) and two resets (GPU core reset and GPU clkgen reset).
Only the clkgen reset is exposed at the AON leve
Several RISC-V boards feature Imagination GPUs that are compatible with
the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi
4A board. This commit adjusts the driver's Kconfig dependencies to allow
the PowerVR driver to be compiled on the RISC-V architecture.
By enabling compila
In order to support the complex power sequencing required by the TH1520
GPU, the AON power domain driver must be responsible for initiating the
corresponding sequencer driver. This functionality is specific to
platforms where the GPU power sequencing hardware is controlled by the
AON block.
Extend
Introduce the pwrseq-thead-gpu driver, a power sequencer provider for
the Imagination BXM-4-64 GPU on the T-HEAD TH1520 SoC. This driver is
an auxiliary driver instantiated by the AON power domain driver.
The TH1520 GPU requires a specific sequence to correctly initialize and
power down its resour
Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD
TH1520 SoC used by the Lichee Pi 4A board. This node enables support for
the GPU using the drm/imagination driver.
By adding this node, the kernel can recognize and initialize the GPU,
providing graphics acceleration capabilitie
This patch series introduces support for the Imagination IMG BXM-4-64
GPU found on the T-HEAD TH1520 SoC. A key aspect of this support is
managing the GPU's complex power-up and power-down sequence, which
involves multiple clocks and resets.
The TH1520 GPU requires a specific sequence to be follow
Update the Imagination PVR DRM driver to leverage the pwrseq framework
for managing the power sequence of the GPU on the T-HEAD TH1520 SoC.
To cleanly handle the TH1520's specific power requirements in the
generic driver, this patch implements the "driver match data" pattern. A
has_pwrseq flag in
On Thu, Jun 12, 2025 at 11:01:32PM +0900, Alexandre Courbot wrote:
[...]
> +/// An unsigned integer which is guaranteed to be a power of 2.
> +#[derive(Debug, Clone, Copy)]
> +#[repr(transparent)]
> +pub struct PowerOfTwo(T);
> +
[...]
> +impl Deref for PowerOfTwo {
Why do we need `impl Deref` (an
On Fri, Jun 13, 2025 at 11:16:10PM +0900, Alexandre Courbot wrote:
[...]
> >> +/// Aligns `self` down to `alignment`.
> >> +///
> >> +/// # Examples
> >> +///
> >> +/// ```
> >> +/// use kernel::num::Pow
On Fri, Jun 13, 2025 at 12:33 PM Konrad Dybcio
wrote:
>
> On 6/13/25 4:57 PM, Alexey Klimov wrote:
> > On Fri Jun 13, 2025 at 3:41 PM BST, Rob Clark wrote:
> >> We want to WARN_ON() if info is NULL.
> >>
> >> Suggested-by: Konrad Dybcio
> >> Fixes: 0838fc3e6718 ("drm/msm/adreno: Check for recogni
On Sat, Jun 14, 2025 at 3:39 AM Danilo Krummrich wrote:
>
> On Fri, Jun 13, 2025 at 04:57:03PM -0700, Rob Clark wrote:
> > For UNMAP/REMAP steps we could be needing to lock objects that are not
> > explicitly listed in the VM_BIND ioctl in order to tear-down unmapped
> > VAs. These helpers handle
On Fri, Jun 13, 2025 at 04:57:03PM -0700, Rob Clark wrote:
> For UNMAP/REMAP steps we could be needing to lock objects that are not
> explicitly listed in the VM_BIND ioctl in order to tear-down unmapped
> VAs. These helpers handle locking/preparing the needed objects.
Yes, that's a common use-ca
On Fri, Jun 13, 2025 at 04:57:02PM -0700, Rob Clark wrote:
> Correctly summerize drm_gpuvm_sm_map/unmap, and fix the parameter order
> and names. Just something I noticed in passing.
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/drm_gpuvm.c | 6 +++---
> include/drm/drm_gpuvm.h | 6 +
> -Original Message-
> From: Nilawar, Badal
> Sent: Friday, June 6, 2025 11:27 PM
> To: intel...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Gupta, Anshuman ; Vivi, Rodrigo
> ; Usyskin, Alexander ;
> gre...@linuxfoundation.org; Ceraolo Spurio, Daniele
> ; j...@nvidia.com
Hi Dmitry,
On 2025/6/9 1:44, Dmitry Baryshkov wrote:
On Mon, May 26, 2025 at 08:07:42PM +0800, Damon Ding wrote:
Apply drm_bridge_connector helper for Analogix DP driver.
The following changes have been made:
- Remove &analogix_dp_device.connector and change
&analogix_dp_device.bridge from
> -Original Message-
> From: Nilawar, Badal
> Sent: Friday, June 6, 2025 11:27 PM
> To: intel...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Gupta, Anshuman ; Vivi, Rodrigo
> ; Usyskin, Alexander ;
> gre...@linuxfoundation.org; Ceraolo Spurio, Daniele
> ; j...@nvidia.co
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