On 10/06/2025 16:10, Neil Armstrong wrote:
> On 10/06/2025 16:05, Krzysztof Kozlowski wrote:
>> v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register
>> differences and new implementations of setup_alpha_out(),
>> setup_border_color() and setup_blend_config().
>>
>> Notable changes in v6
Use KMEM_CACHE() instead of kmem_cache_create() to simplify the creation
of SLAB cache.
Signed-off-by: Salah Triki
---
drivers/gpu/drm/xe/xe_hw_fence.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_fence.c b/drivers/gpu/drm/xe/xe_hw_fence.c
ind
By default, HPD was disabled on SN65DSI86 bridge. When the driver was
added (commit "a095f15c00e27"), the HPD_DISABLE bit was set in pre-enable
call which was moved to other function calls subsequently.
Later on, commit "c312b0df3b13" added detect utility for DP mode. But with
HPD_DISABLE bit set,
Hi Andrew,
> Subject: Re: [PATCH v3 1/3] mm/hugetlb: Make hugetlb_reserve_pages()
> return nr of entries updated
>
> On Fri, 6 Jun 2025 06:14:06 + "Kasireddy, Vivek"
> wrote:
>
> > > Also, patch [2/3] addresses a BUG which was introduced into 6.12.
> > > Presumably we want to backport the f
On 6/11/2025 2:51 AM, Palmer Dabbelt wrote:
> From: Palmer Dabbelt
>
> 9KiB frames seem pretty big, but without this I'm getting some warnings
> as of 6.16-rc1
>
> CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.o
> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/s
Hi all,
After merging the drm-misc tree, today's linux-next build (htmldocs)
produced these warnings:
include/drm/drm_bridge.h:943: warning: Function parameter or struct member
'hdmi_cec_init' not described in 'drm_bridge_funcs'
include/drm/drm_bridge.h:943: warning: Function parameter or struct
On 6/10/25 7:08 PM, Bagas Sanjaya wrote:
> GSP message queue docs has been moved following RPC handling split in
> 8a8b1ec5261f20 ("drm/nouveau/gsp: split rpc handling out on its own"),
> before GSP-RM implementation is versioned in c472d828348caf
> ("drm/nouveau/gsp: move subdev/engine impls to
Hi all,
On Wed, 11 Jun 2025 12:08:01 +1000 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the drm-misc tree got a conflict in:
>
> drivers/gpu/drm/vc4/vc4_hdmi.c
>
> between commit:
>
> c0317ad44f45 ("drm/vc4: fix infinite EPROBE_DEFER loop")
>
> from the drm-misc-fixes tree and
GSP message queue docs has been moved following RPC handling split in
8a8b1ec5261f20 ("drm/nouveau/gsp: split rpc handling out on its own"),
before GSP-RM implementation is versioned in c472d828348caf
("drm/nouveau/gsp: move subdev/engine impls to subdev/gsp/rm/r535/").
However, the kernel-doc refe
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/vc4/vc4_hdmi.c
between commit:
c0317ad44f45 ("drm/vc4: fix infinite EPROBE_DEFER loop")
from the drm-misc-fixes tree and commit:
d9f9bae6752f ("drm/bridge: allow limiting I2S formats")
from the drm
Hi,
Is there a QEMU tree using this somewhere?
Also it would be nice to have this tree pushed somewhere, saves time. Thanks,
On 29/5/25 15:34, Xu Yilun wrote:
This series is the generic host side (KVM/VFIO/IOMMUFD) support for the
whole life cycle of private device assignment. It follows the
On 6/6/2025 10:57 AM, Badal Nilawar wrote:
Load late binding firmware
v2:
- s/EAGAIN/EBUSY/
- Flush worker in suspend and driver unload (Daniele)
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/xe/xe_late_bind_fw.c | 121 -
drivers/gpu/drm/xe/xe_late_bind_f
On 6/6/2025 10:57 AM, Badal Nilawar wrote:
Search for late binding firmware binaries and populate the meta data of
firmware structures.
v2:
- drm_err if firmware size is more than max pay load size (Daniele)
- s/request_firmware/firmware_request_nowarn/ as firmware will
not be availab
Fix
aarch64-linux-gnu-ld: drivers/gpu/drm/bridge/ite-it6505.o: in function
`it6505_i2c_probe':
ite-it6505.c:(.text+0x754): undefined reference to `__devm_regmap_init_i2c'
Signed-off-by: Chia-I Wu
---
drivers/gpu/drm/bridge/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
On Mon, Jun 2, 2025 at 7:34 AM Karunika Choo wrote:
>
> Mali-Gx20 and Mali-Gx25 deprecates the use of FLUSH_MEM and FLUSH_PT
> MMU_AS commands in favour of cache maintenance via
> GPU_COMMAND's FLUSH_CACHES and FLUSH_PA_RANGE.
>
> They also introduce the following registers:
> - GPU_COMMAND_ARG0~1
On Mon, Jun 2, 2025 at 7:42 AM Karunika Choo wrote:
>
> As the FLUSH_MEM and FLUSH_PT commands are deprecated in GPUs from
> Mali-Gx20 onwards, this patch adds support for performing cache
> maintenance via the FLUSH_CACHES command in GPU_CONTROL, in place of
> FLUSH_MEM and FLUSH_PT based on PANT
On Mon, Jun 2, 2025 at 8:16 AM Karunika Choo wrote:
>
> This patch replaces the panthor_model structure with a simple switch
> case based on the product_id which is in the format of:
> ((arch_major << 24) | product_major)
>
> This simplifies comparison and allows extending of the function
On Mon, Jun 2, 2025 at 7:33 AM Karunika Choo wrote:
>
> This patch provides an initialization framework for multiple Mali GPUs
> by introducing a GPU support look-up table. Each entry contains, at
> minimum, the architecture major version of the GPU, and may optionally
> provide feature flags and
Hi Jeff,
On Tue, 10 Jun 2025 11:59:12 -0600 Jeff Hugo wrote:
>
> pci_printk() was removed with commit 1c8a0ed2043c ("PCI: Remove unused
> pci_printk()")
> so change to using dev_printk().
>
> Fixes: c11a50b170e7 ("accel/qaic: Add Reliability, Accessibility,
> Serviceability (RAS)")
> Reported-
On Tue, Jun 10, 2025 at 04:05:51PM +0200, Krzysztof Kozlowski wrote:
> Linux coding style asks to use kernel types like u32 instead of uint32_t
> and code already has it in other places, so unify the remaining pieces.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
>
> Changes in v6:
> 1. New patch
On Tue, Jun 10, 2025 at 04:05:49PM +0200, Krzysztof Kozlowski wrote:
> Add support for DSI on Qualcomm SM8750 SoC with notable difference:
>
> DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
> parents before DSI PHY is configured, the PLLs are prepared and their
> initial rat
On Tue, Jun 10, 2025 at 04:05:45PM +0200, Krzysztof Kozlowski wrote:
> Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
> masks and shifts and make the code a bit more readable.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Changes in v6:
> 1. Add new line between declar
On Tue, Jun 10, 2025 at 09:09:21PM +0200, Luca Weiss wrote:
> Add support for the 2160x1080 LCD panel from DJN (98-03057-6598B-I)
> bundled with a HX83112B driver IC, as found on the Fairphone 3
> smartphone.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Luca Weiss
> ---
> drivers/gpu/drm/
The nouveau_get_backlight_name() function generates a unique name for the
backlight interface, appending an id from 1 to 99 for all backlight devices
after the first.
GCC 15 (and likely other compilers) produce the following
-Wformat-truncation warning:
nouveau_backlight.c: In function ‘nouveau_b
On 6/6/2025 10:57 AM, Badal Nilawar wrote:
Introducing xe_late_bind_fw to enable firmware loading for the devices,
such as the fan controller, during the driver probe. Typically,
firmware for such devices are part of IFWI flash image but can be
replaced at probe after OEM tuning.
This patch bi
Each window of a vop2 is usable by a specific set of video ports, so while
binding the vop2, we look through the list of available windows trying to
find one designated as primary-plane and usable by that specific port.
The code later wants to use drm_crtc_init_with_planes with that found
primary
From: Palmer Dabbelt
9KiB frames seem pretty big, but without this I'm getting some warnings
as of 6.16-rc1
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.o
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.c: In function
'smu_v13_0_6_get_gpu_metrics':
Hi Danilo,
[…]
>
>> +
>> +impl OpMap {
>> +/// Returns the base address of the new mapping.
>> +#[inline]
>> +pub fn addr(&self) -> u64 {
>> +self.0.va.addr
>> +}
>> +
>> +/// Returns the range of the new mapping.
>> +#[inline]
>> +pub fn range(&self) -> u64 {
Hi Danilo,
> The lock might be held already by the driver or by TTM when things are called
> from TTM callbacks.
>
> This is why GPUVM never takes locks by itself, but asserts that the correct
> lock
> is held.
>
> I think we really want to get proof by the driver by providing lock guard
> refe
On Mon, 2025-06-09 at 13:36 +0100, Tvrtko Ursulin wrote:
>
> On 03/06/2025 23:50, Juston Li wrote:
> > v3:
> > - Patch introduced to replace per-driver config (Lucas)
> >
> > Signed-off-by: Juston Li
> > ---
> > drivers/gpu/trace/Kconfig | 11 ++-
> > 1 file changed, 10 insertions(+
https://bugzilla.kernel.org/show_bug.cgi?id=220218
Artem S. Tashkinov (a...@gmx.com) changed:
What|Removed |Added
Status|NEW |RESOLVED
Reso
Add the description for the display panel found on this phone.
Unfortunately the LCDB module on PMI632 isn't yet supported upstream so
we need to use a dummy regulator-fixed in the meantime.
And with this done we can also enable the GPU and set the zap shader
firmware path.
Reviewed-by: Konrad Dy
Himax HX83112B is a display driver IC used to drive LCD DSI panels.
Describe it and the Fairphone 3 panel (98-03057-6598B-I) from DJN using
it.
Signed-off-by: Luca Weiss
---
.../bindings/display/panel/himax,hx83112b.yaml | 75 ++
1 file changed, 75 insertions(+)
diff --g
Add the vendor prefix for DJN (http://en.djnlcd.com/).
Acked-by: Krzysztof Kozlowski
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation
Add support for the 2160x1080 LCD panel from DJN (98-03057-6598B-I)
bundled with a HX83112B driver IC, as found on the Fairphone 3
smartphone.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Luca Weiss
---
drivers/gpu/drm/panel/Kconfig| 10 +
drivers/gpu/drm/panel/Makefile
Add a driver for the HX83112B-based panel, and enable it on Fairphone 3
to enable display output, and enable GPU as well.
Signed-off-by: Luca Weiss
---
Changes in v3:
- Pick up tags
- Rebase on v6.16-rc1
- Link to v2:
https://lore.kernel.org/r/20250225-fp3-display-v2-0-0b1f05915...@lucaweiss.eu
On 6/10/25 12:56, Thomas Zimmermann wrote:
Fix the compile-time warnings
drivers/video/fbdev/omap/lcd_dma.c: warning: EXPORT_SYMBOL() is used, but #include
is missing
drivers/video/fbdev/omap/lcdc.c: warning: EXPORT_SYMBOL() is used, but #include
is missing
drivers/video/fbdev/omap/
On 6/10/25 12:56, Thomas Zimmermann wrote:
Fix the compile-time warnings
drivers/video/fbdev/matrox/g450_pll.c: warning: EXPORT_SYMBOL() is used, but
#include is missing
drivers/video/fbdev/matrox/matroxfb_DAC1064.c: warning: EXPORT_SYMBOL() is used,
but #include is missing
drivers/
On 6/10/25 12:56, Thomas Zimmermann wrote:
Fix coding style.
Signed-off-by: Thomas Zimmermann
---
drivers/video/fbdev/matrox/g450_pll.c | 24
drivers/video/fbdev/matrox/matroxfb_DAC1064.c | 46 +++---
drivers/video/fbdev/matrox/matroxfb_g450.c| 60 +-
On 6/10/25 12:56, Thomas Zimmermann wrote:
Fix the compile-time warning
drivers/video/fbdev/cyber2000fb.c: warning: EXPORT_SYMBOL() is used, but #include
is missing
The affected symbols are not used outside of their module.
Signed-off-by: Thomas Zimmermann
---
drivers/video/fbdev/cyber
On 6/10/25 12:56, Thomas Zimmermann wrote:
Fix coding style.
Signed-off-by: Thomas Zimmermann
---
drivers/video/fbdev/macmodes.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Helge Deller
On 6/10/25 12:56, Thomas Zimmermann wrote:
Fix the compile-time warnings
drivers/video/fbdev/c2p_iplan2.c: warning: EXPORT_SYMBOL() is used, but #include
is missing
drivers/video/fbdev/c2p_planar.c: warning: EXPORT_SYMBOL() is used, but #include
is missing
Signed-off-by: Thomas Zimmer
On 6/10/25 1:59 PM, Jeff Hugo wrote:
pci_printk() was removed with commit 1c8a0ed2043c ("PCI: Remove unused
pci_printk()")
so change to using dev_printk().
Fixes: c11a50b170e7 ("accel/qaic: Add Reliability, Accessibility, Serviceability
(RAS)")
Reported-by: Stephen Rothwell
Closes: https:/
On 6/10/25 12:56, Thomas Zimmermann wrote:
Fix the compile-time warnings
drivers/video/fbdev/core/cfbcopyarea.c: warning: EXPORT_SYMBOL() is used, but
#include is missing
drivers/video/fbdev/core/cfbfillrect.c: warning: EXPORT_SYMBOL() is used, but
#include is missing
drivers/video/
On 6/10/25 12:56, Thomas Zimmermann wrote:
Fix the compile-time warning
drivers/video/fbdev/pxafb.c: warning: EXPORT_SYMBOL() is used, but #include
is missing
The affected symbol is not used outside of its module.
Signed-off-by: Thomas Zimmermann
---
drivers/video/fbdev/pxafb.c | 1 -
pci_printk() was removed with commit 1c8a0ed2043c ("PCI: Remove unused
pci_printk()")
so change to using dev_printk().
Fixes: c11a50b170e7 ("accel/qaic: Add Reliability, Accessibility,
Serviceability (RAS)")
Reported-by: Stephen Rothwell
Closes: https://lore.kernel.org/all/20250610124809.1e1ff.
https://bugzilla.kernel.org/show_bug.cgi?id=220218
Bug ID: 220218
Summary: amdgpu: crash in
dc_dmub_srv_apply_idle_power_optimizations
Product: Drivers
Version: 2.5
Hardware: AMD
OS: Linux
Status
On 6/9/25 13:03, Tvrtko Ursulin wrote:
> Dma-fence objects currently suffer from a potential use after free problem
> where fences exported to userspace and other drivers can outlive the
> exporting driver, or the associated data structures.
>
> The discussion on how to address this concluded t
Dma-fence objects currently suffer from a potential use after free problem
where fences exported to userspace and other drivers can outlive the
exporting driver, or the associated data structures.
The discussion on how to address this concluded that adding reference
counting to all the involved ob
Protect the access to driver and timeline name which otherwise could be
freed as dma-fence exported is signalling fences.
This prepares the code for incoming dma-fence API changes which will start
asserting these accesses are done from a RCU locked section.
Now that the safe access is handled in
On Tue, Jun 10, 2025 at 09:28:55AM +0200, Thomas Zimmermann wrote:
> Map DRM FourCC codes to pixel descriptions with an internal struct
> type. Avoid simplefb's struct simplefb_format, which is for parsing
> "simple-framebuffer" DT nodes. Drop the unsupported formats with
> alpha channel from the l
Hi all,
tl;dr;
Xe and probably some other drivers can tear down the internal state referenced
by an exported sync_file fence which then causes a null pointer derefences on
accessing said fence.
IGT that exploits the problem:
https://patchwork.freedesktop.org/patch/642709/?series=146211&rev=2
It
Xe can free some of the data pointed to by the dma-fences it exports. Most
notably the timeline name can get freed if userspace closes the associated
submit queue. At the same time the fence could have been exported to a
third party (for example a sync_fence fd) which will then cause an use-
after-
Protect the access to driver and timeline name which otherwise could be
freed as dma-fence exported is signalling fences.
This prepares the code for incoming dma-fence API changes which will start
asserting these accesses are done from a RCU locked section.
Signed-off-by: Tvrtko Ursulin
---
dri
Hi,
On Tue, Jun 10, 2025 at 5:34 AM Bartosz Golaszewski wrote:
>
> From: Bartosz Golaszewski
>
> struct gpio_chip now has callbacks for setting line values that return
> an integer, allowing to indicate failures. Convert the driver to using
> them.
>
> Signed-off-by: Bartosz Golaszewski
> ---
>
On 14.05.2025 15:44, Marek Szyprowski wrote:
> On 08.05.2025 11:57, Christian König wrote:
>> On 5/7/25 18:09, Marek Szyprowski wrote:
>>> Use common wrappers operating directly on the struct sg_table
>>> objects to
>>> fix incorrect use of scatterlists sync calls. dma_sync_sg_for_*()
>>> function
Add DSI controller for Qualcomm SM8750 SoC which is quite different from
previous (SM8650) generation.
It does not allow the display clock controller clocks like "byte" and
"pixel" to be reparented to DSI PHY PLLs while the DSI PHY PLL is not
configured (not prepared, rate not set). Therefore
ass
Hi,
On Tue, Jun 10, 2025 at 12:43 AM Jayesh Choudhary wrote:
>
> Hello Doug,
>
> On 10/06/25 03:39, Doug Anderson wrote:
> > Hi,
> >
> > On Mon, Jun 2, 2025 at 4:05 AM Jayesh Choudhary wrote:
> >>
> >> Hello Geert, Krzysztof,
> >>
> >> (continuing discussion from both patches on this thread...)
On 6/10/25 05:54, Richard Weinberger wrote:
- Ursprüngliche Mail -
Von: "Alexander Usyskin"
Richard, I've reproduced your setup (modulo that I must load mtdram manually)
and patch provided in this thread helps to fix the issue.
Can you apply and confirm?
Yes, it fixes the issue here!
On Tue, Jun 10, 2025 at 4:14 PM Tamir Duberstein wrote:
>
> Yeah, I think these are good calls - I'll fix it in v11. When would
> you like me to send it?
Since -rc1 is out, please feel free to send it already if you can. It
would be nice to see if we can apply it all soon in the cycle, but we
wil
On Fri, May 30, 2025 at 05:54:29PM +0800, Yongbang Shi wrote:
From: Baihan Li
Add GPU display control enable in dp_mode_set(), which is already
in vdac's mode_set, however, if vdac is not connected, GPU
cannot work.
Fixes: f9698f802e50 ("drm/hisilicon/hibmc: Restructuring the header dp_reg.
On Mon, Jun 09, 2025 at 10:45:35AM -0500, Anusha Srivatsa wrote:
> On Fri, Jun 6, 2025 at 7:03 AM Maxime Ripard wrote:
>
> > On Wed, Jun 04, 2025 at 10:45:11PM -0500, Anusha Srivatsa wrote:
> > > Put the panel reference back when driver is no
> > > longer using it.
> > >
> > > Signed-off-by: Anus
Hi Maxim, Thomas, Maarten,
could you please ack merging this patchset via drm-intel?
Thanks,
Imre
On Thu, Jun 05, 2025 at 11:28:45AM +0300, Imre Deak wrote:
> This is v3 of [1], with the following changes requested by Jani:
>
> - Convert the internal quirk list to an enum list.
> - Track both t
Hi
Am 06.06.25 um 10:43 schrieb Louis Chauvet:
Le 05/06/2025 à 17:24, Thomas Zimmermann a écrit :
The vblank timer simulates a vblank interrupt for hardware without
support. Rate-limits the display update frequency.
DRM drivers for hardware without vblank support apply display updates
ASAP.
On 6/9/2025 9:46 PM, Lukas Wunner wrote:
On Tue, Jun 10, 2025 at 12:48:09PM +1000, Stephen Rothwell wrote:
After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/accel/qaic/qaic_ras.c: In function 'decode_ras_msg':
drivers/accel/qaic/qaic_ras.c
On Tue, Jun 10, 2025 at 12:19:05AM +0100, Prabhakar wrote:
> From: Lad Prabhakar
>
> Document support for the DU IP found on the Renesas RZ/V2N (R9A09G056) SoC.
> The DU IP is functionally identical to that on the RZ/V2H(P) SoC, so no
> driver changes are needed. The existing `renesas,r9a09g057-d
Add a new "ref_tracker" directory in debugfs. Each individual refcount
tracker can register files under there to display info about
currently-held references.
Reviewed-by: Andrew Lunn
Reviewed-by: Krzysztof Karas
Signed-off-by: Jeff Layton
---
lib/ref_tracker.c | 13 +
1 file chang
在 2025-05-31星期六的 20:11 +0800，Icenowy Zheng写道：
> Currently even the SoC's OVL does not declare the support of AFBC,
> AFBC
> is still announced to the userspace within the IN_FORMATS blob, which
> breaks modern Wayland compositors like KWin Wayland and others.
>
> Gate passing modifiers to drm_univ
On 6/7/25 4:15 PM, Akhil P Oommen wrote:
> Add support for Adreno X1-45 GPU present Snapdragon X1P42100
> series of compute chipsets. This GPU is a smaller version of
> X1-85 GPU with lower core count and smaller internal memories.
>
> Signed-off-by: Akhil P Oommen
> ---
Matches what I had runni
As Thomas Weißschuh points out [1], it is now preferable to use %p
instead of hashed pointers with printk(), since raw pointers should no
longer be leaked into the kernel log. Change the ref_tracker
infrastructure to use %p instead of %pK in its formats.
[1]:
https://lore.kernel.org/netdev/202504
After assigning the inode number to the namespace, use it to create a
unique name for each netns refcount tracker with the ns.inum and
net_cookie values in it, and register a symlink to the debugfs file for
it.
init_net is registered before the ref_tracker dir is created, so add a
late_initcall()
Now that we have dentries and the ability to create meaningful symlinks
to them, don't keep a name string in each tracker. Switch the output
format to print "class@address", and drop the name field.
Also, add a kerneldoc header for ref_tracker_dir_init().
Signed-off-by: Jeff Layton
---
drivers/
In a later patch, we'll be adding a 3rd mechanism for outputting
ref_tracker info via seq_file. Instead of a conditional, have the caller
set a pointer to an output function in struct ostream. As part of this,
the log prefix must be explicitly passed in, as it's too late for the
pr_fmt macro.
Revi
Add the ability for a subsystem to add a user-friendly symlink that
points to a ref_tracker_dir's debugfs file. Add a separate
debugfs_symlinks xarray and use that to track symlinks. The reaper
workqueue job will remove symlinks before their corresponding dentries.
Signed-off-by: Jeff Layton
---
Currently, there is no convenient way to see the info that the
ref_tracking infrastructure collects. Attempt to create a file in
debugfs when called from ref_tracker_dir_init().
The file is given the name "class@%px", as having the unmodified address
is helpful for debugging. This should be safe s
Allow pr_ostream to also output directly to a seq_file without an
intermediate buffer. The first caller of +ref_tracker_dir_seq_print()
will come in a later patch, so mark that __maybe_unused for now. That
designation will be removed once it is used.
Reviewed-by: Andrew Lunn
Signed-off-by: Jeff L
A later patch in the series will be adding debugfs files for each
ref_tracker that get created in ref_tracker_dir_init(). The format will
be "class@%px". The current "name" string can vary between
ref_tracker_dir objects of the same type, so it's not suitable for this
purpose.
Add a new "class" st
For those just joining in, this series adds a new top-level
"ref_tracker" debugfs directory, and has each ref_tracker_dir register a
file in there as part of its initialization. It also adds the ability to
register a symlink with a more human-usable name that points to the
file, and does some gener
Linux coding style asks to use kernel types like u32 instead of uint32_t
and code already has it in other places, so unify the remaining pieces.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v6:
1. New patch
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 -
1 file changed, 4 inser
On 6/7/25 4:15 PM, Akhil P Oommen wrote:
> X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
> version of Adreno X1-85 GPU. Describe this new GPU and also add
> the secure gpu firmware path that should used for X1P42100 CRD.
>
> Signed-off-by: Akhil P Oommen
> ---
[...]
> -/* Th
On 05/06/2025 09:53, Christian König wrote:
Smatch pointed out this trivial typo:
drivers/dma-buf/dma-buf.c:1123 dma_buf_map_attachment()
warn: passing positive error code '16' to 'ERR_PTR'
drivers/dma-buf/dma-buf.c
1113 dma_resv_assert_held(attach->dmabuf->resv);
v12.0 DPU on SM8750 comes with new LM crossbar that requires each pipe
rectangle to be programmed separately in blend stage. Implement support
for this along with a new CTL_LAYER_ACTIVE register and setting the
blend stage in layer mixer code.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzyszt
v12.0 DPU on SM8750 comes with new CTL_PIPE_ACTIVE register for
selective activation of pipes, which replaces earlier
dpu_hw_ctl_setup_blendstage() code path for newer devices.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v4:
1. Lowercase hex
2. Add Dmitry's
On Sun, Jun 8, 2025 at 5:06 PM Miguel Ojeda
wrote:
>
> On Fri, Apr 18, 2025 at 5:37 PM Tamir Duberstein wrote:
> >
> > -bindings::BLK_STS_OK as _
> > +bindings::BLK_STS_OK as u8
>
> > -unsafe { bindings::blk_mq_end_request(request_ptr,
> > bindings::BLK_STS_OK as
Hardware Programming Guide for DSI PHY says that PLL_SHUTDOWNB and
DIGTOP_PWRDN_B have to be asserted for any PLL register access.
Whenever dsi_pll_7nm_vco_recalc_rate() or dsi_pll_7nm_vco_set_rate()
were called on unprepared PLL, driver read values of zero leading to all
sort of further troubles,
On 10/06/2025 16:05, Krzysztof Kozlowski wrote:
v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register
differences and new implementations of setup_alpha_out(),
setup_border_color() and setup_blend_config().
Notable changes in v6:
Correct fg_alpha shift on new DPU, pointed out by Abel
On 10/06/2025 16:05, Krzysztof Kozlowski wrote:
Linux coding style asks to use kernel types like u32 instead of uint32_t
and code already has it in other places, so unify the remaining pieces.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v6:
1. New patch
---
drivers/gpu/drm/msm/disp/dpu
Gentle ping, can anybody give me a quick rb for this trivial fix?
Thanks,
Christian.
On 6/5/25 10:53, Christian König wrote:
> Smatch pointed out this trivial typo:
> drivers/dma-buf/dma-buf.c:1123 dma_buf_map_attachment()
> warn: passing positive error code '16' to 'ERR_PTR'
>
> dri
Hi Janusz,
On 2025-06-06 at 15:58:08 GMT, Janusz Krzysztofik wrote:
> The following error has been reported sporadically by CI when a test
> unbinds the i915 driver on a ring submission platform:
>
> <4> [239.330153] [ cut here ]
> <4> [239.330166] i915 :00:02.0: [drm]
v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register
differences and new implementations of setup_alpha_out(),
setup_border_color() and setup_blend_config().
Notable changes in v6:
Correct fg_alpha shift on new DPU, pointed out by Abel Vesas.
Reviewed-by: Dmitry Baryshkov
Signed-off-
Add support for the Qualcomm SM8750 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/msm/msm_mdss.c | 33 +
drivers/gpu/drm/msm/msm_mdss.h | 1 +
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/msm/ms
Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an
incompatible hardware interface change:
ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
offsets were just switched. Currently these registers are not used in
the driver, so the easiest is to document both
Add DPU version v12.0 support for the Qualcomm SM8750 platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Krzysztof Kozlowski
---
Changes in v6:
1. Changes due to rebase on newer HW features patchset rework from
Dmitry.
Changes in v2:
1. Add CDM
---
.../drm/msm/disp/dpu1/catalog/dpu_12_
Add support for DSI on Qualcomm SM8750 SoC with notable difference:
DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
parents before DSI PHY is configured, the PLLs are prepared and their
initial rate is set. Therefore assigned-clock-parents are not working
here and driver is
Driver unconditionally saves current state on first init in
dsi_pll_7nm_init(), but does not save the VCO rate, only some of the
divider registers. The state is then restored during probe/enable via
msm_dsi_phy_enable() -> msm_dsi_phy_pll_restore_state() ->
dsi_7nm_pll_restore_state().
Restoring
Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit
masks and shifts and make the code a bit more readable.
Signed-off-by: Krzysztof Kozlowski
---
Changes in v6:
1. Add new line between declarations and actual code (Dmitry)
Changes in v5:
1. New patch
---
drivers/gpu/drm/msm/d
Hi,
Dependency / Rabased on top of
==
https://lore.kernel.org/r/20250522-dpu-drop-features-v5-0-3b2085a07...@oss.qualcomm.com/
Changes in v6:
=
- Add ack/rb tags
- Dropped dispcc-sm8750 patch, because I sent it separately.
- Several changes due to rebasing
Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation
with two revisions up of the IP block comparing to SM8650.
Reviewed-by: Rob Herring (Arm)
Signed-off-by: Krzysztof Kozlowski
---
Changes in v3:
1. Properly described interconnects
2. Use only one compatible and contains for
According to Hardware Programming Guide for DSI PHY, the retime buffer
resync should be done after PLL clock users (byte_clk and intf_byte_clk)
are enabled. Downstream also does it as part of configuring the PLL.
Driver was only turning off the resync FIFO buffer, but never bringing it
on again.
Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks
fully compatible with earlier SM8650 variant - both are of version
v1.5.1 of the IP block. Datasheet also mentions that both support 4x
MST for DPTX0 and 2x MST for DPTX1.
Acked-by: Rob Herring (Arm)
Reviewed-by: Dmitry Barysh
1 - 100 of 228 matches
Mail list logo
