Thanks Maíra, all patches but 4 are:
Reviewed-by: Iago Toral Quiroga
I hope someone else can can look at the remaining DT patch.
Iago
El mié, 26-02-2025 a las 16:58 -0300, Maíra Canal escribió:
> This series addresses GPU reset issues reported in [1], where running
> a
> long compute job would
Include headers for the symbols directly used in this file instead of
relying on intermediate headers.
Signed-off-by: Raag Jadav
Acked-by: Simona Vetter
---
drivers/gpu/drm/drm_draw.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_draw.c b/drivers/gpu/drm/drm_draw.c
i
This series attempts to cleanup io.h with "include what you use" approach.
This depends on changes available on immutable tag[1].
Although this series is too trivial in the grand scheme of things, it is
still a tiny step towards untangling core headers. I have success results
from LKP for this ser
Drop unused headers and type declaration from io.h.
Signed-off-by: Raag Jadav
Acked-by: Andy Shevchenko
---
include/linux/io.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/linux/io.h b/include/linux/io.h
index 40cb2de73f5e..6a6bc4d46d0a 100644
--- a/include/linux/io.h
+++ b/inc
On Wed, Feb 26, 2025 at 12:04:56PM +0100, Stefan Wahren wrote:
> Hi Dmitry,
>
> Am 24.02.25 um 04:15 schrieb Dmitry Baryshkov:
> > On Sat, Feb 22, 2025 at 11:29:21AM +0100, Stefan Wahren wrote:
> > > From: David Turner
> > >
> > > Add ALSA jack detection to the vc4-hdmi audio driver so userspace
On 26. 02. 25, 19:33, Yury Norov wrote:
Not in cases where macros are inevitable. I mean, do we need parityXX() for
XX in (8, 16, 32, 64) at all? Isn't the parity() above enough for everybody?
The existing codebase has something like:
int ret;
ret = i3c_master_get_free_addr(
On Thu, Feb 27, 2025 at 10:06:24AM +0530, Vignesh Raman wrote:
> If we are not caching the git archive, do not
> set CI_PRE_CLONE_SCRIPT. Setting it makes CI
> try to download the cache first, and if it is
> missing, it tries to clone the repo within a
> time limit, which can cause build failures.
On Wed, Feb 26, 2025 at 11:50:08AM +, Xin Ji wrote:
> > > > > > > > > From: Dmitry Baryshkov
> > > > > > > > > Sent: Thursday, February 13, 2025 9:04 PM
> > > > > > > > > To: Xin Ji
> > > > > > > > > Cc: Andrzej Hajda ; Neil
> > > > > > > > > Armstrong ; Robert Foss
> > > > > > > > > ; Lauren
Hi Jonathan,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-xe/drm-xe-next]
[also build test ERROR on next-20250226]
[cannot apply to linus/master v6.14-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
On Thu, 13 Feb 2025 17:27:55 +0100, Neil Armstrong wrote:
> The mdp1-mem is not supported on the SM8550 & SM8650 SoCs, so properly
> document
> the mdp0-mem and cpu-cfg interconnect entries.
>
> This fixes the following errors:
> display-subsystem@ae0: interconnects: [[200, 3, 7, 32, 1, 7]]
On Mon, 17 Feb 2025 12:17:40 +0100, Marijn Suijten wrote:
> This series covers a step-up towards supporting the DUALPIPE DSC
> topology, also known as 2:2:2 topology (on active-CTL hardware). It
> involves 2 layer mixers, 2 DSC compression encoders, and 2 interfaces
> (on DSI, this is called bon
On Wed, 19 Feb 2025 11:49:16 -0800, Jessica Zhang wrote:
> To debug display mmu faults, this series introduces a display fault
> handler similar to the gpu one.
>
> This series has been tested on sc7280 chromebook by using triggering
> a smmu fault by forcing an incorrect stride on the planes.
>
On Wed, 19 Feb 2025 12:07:12 +0800, Haoxiang Li wrote:
> Add check for the return value of devm_kstrdup() in
> dsi_host_parse_dt() to catch potential exception.
>
>
Applied, thanks!
[1/1] drm/msm/dsi: Add check for devm_kstrdup()
https://gitlab.freedesktop.org/lumag/msm/-/commit/52b3f0e
On Wed, 22 Jan 2025 17:23:44 +0100, Marijn Suijten wrote:
> Some SoCs such as SC7280 (used in the Fairphone 5) have only a single
> DSC "hard slice" encoder. The current hardcoded use of 2:2:1 topology
> (2 LM and 2 DSC for a single interface) make it impossible to use
> Display Stream Compressi
On Tue, 14 Jan 2025 16:55:24 +0800, Fange Zhang wrote:
> On the SM6150 platform there is WB_2 block. Add it to the SM6150 catalog.
>
>
Applied, thanks!
[1/1] drm/msm/dpu: Add writeback support for SM6150
https://gitlab.freedesktop.org/lumag/msm/-/commit/23c0a9d36f78
Best regards,
--
D
On Wed, 29 Jan 2025 12:55:04 +0100, Krzysztof Kozlowski wrote:
> Since SM8250 all downstream sources program clock inverters in
> PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as
> reset value (0x0). The most recent Hardware Programming Guide for 3 nm,
> 4 nm, 5 nm and 7 nm PH
On Tue, 14 Jan 2025 16:59:59 +0100, Krzysztof Kozlowski wrote:
> In few places we store 'phys_enc->hw_ctl' to local 'ctl' variable so use
> it everywhere. No functional change.
>
>
Applied, thanks!
[1/1] drm/msm/dpu: Simplify using local 'ctl' variable
https://gitlab.freedesktop.org/lu
On Fri, 14 Feb 2025 14:17:43 +0100, Krzysztof Kozlowski wrote:
> Changes in v2:
> - Patch #2: Update commit msg
> - Tags
> - Link to v1:
> https://lore.kernel.org/r/20250106-drm-msm-cleanups-v1-0-271ff1c00...@linaro.org
>
> Few minor improvements/cleanups why browsing the code.
>
> [...]
Appl
On Mon, 27 Jan 2025 14:21:04 +0100, Krzysztof Kozlowski wrote:
> DSI phys, from earliest (28 nm) up to newest (3 nm) generation, provide
> two clocks. The respective clock ID is used by drivers and DTS, so it
> should be documented as explicit ABI.
>
>
Applied, thanks!
[1/2] dt-bindings: dis
On Wed, 19 Feb 2025 17:23:31 +0100, Krzysztof Kozlowski wrote:
> Changes in v5:
> - Drop applied patches 1-3
> - Split part touching pll_7nm_register() from last (#4) patch to new patch
>- Thus: new patch #1 in new numbering.
> - Link to v4:
> https://lore.kernel.org/r/20250217-drm-msm-phy-p
On Tue, 14 Jan 2025 20:17:24 +0100, Krzysztof Kozlowski wrote:
> Replace ternary (condition ? "enable" : "disable") syntax with helpers
> from string_choices.h because:
> 1. Simple function call with one argument is easier to read. Ternary
>operator has three arguments and with wrapping migh
On Tue, 18 Feb 2025 01:24:27 +0300, Danila Tikhonov wrote:
> This patch series adds support for the Visionox RM692E5 panel, which is
> used on the Nothing Phone (1) and then adds it to the DTS.
>
> Before integrating the panel into the DTS, we update the DSI code to
> allow bits-per-component (b
On Thu, 23 Jan 2025 14:43:32 +0200, Dmitry Baryshkov wrote:
> As pointed out by Simona, the drm_atomic_helper_check_modeset() and
> drm_atomic_helper_check() require the former function is rerun if the
> driver's callbacks modify crtc_state->mode_changed. MSM is one of the
> drivers which failed
If we are not caching the git archive, do not
set CI_PRE_CLONE_SCRIPT. Setting it makes CI
try to download the cache first, and if it is
missing, it tries to clone the repo within a
time limit, which can cause build failures.
Signed-off-by: Vignesh Raman
---
drivers/gpu/drm/ci/gitlab-ci.yml | 6
Merge request pipelines were only created when changes
were made to drivers/gpu/drm/ci/, causing MRs that
didn't touch this path to break. Fix MR pipeline rules
to trigger jobs for all changes.
Run jobs automatically for marge-bot and scheduled
pipelines, but in all other cases run manually. Also
From: Sohaib Nadeem
[ Upstream commit 0484e05d048b66d01d1f3c1d2306010bb57d8738 ]
[why]:
issues fixed:
- comparison with wider integer type in loop condition which can cause
infinite loops
- pointer dereference before null check
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Hi,
On Wed, Feb 26, 2025 at 05:34:50PM +0100, Uwe Kleine-König wrote:
> On Wed, Feb 26, 2025 at 05:31:08PM +0200, Abel Vesa wrote:
> > The current implementation assumes that the PWM provider will be able to
> > meet the requested period, but that is not always the case. Some PWM
> > providers hav
Jessica Zhang 于2025年2月27日周四 09:38写道：
>
>
>
> On 2/26/2025 4:31 AM, Jun Nie wrote:
> > The stage contains configuration for a mixer pair. Currently the plane
> > supports just one stage and 2 pipes. Quad-pipe support will require
> > handling 2 stages and 4 pipes at the same time. In preparation fo
Hi Jonathan,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-xe/drm-xe-next]
[also build test ERROR on next-20250226]
[cannot apply to linus/master v6.14-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
Since SmartDMA planes provide two rectangles, it is possible to use them
to drive two different DRM planes, first plane getting the rect_0,
another one using rect_1 of the same SSPP. The sharing algorithm is
pretty simple, it requires that each of the planes can be driven by the
single rectangle an
Jessica Zhang 于2025年2月27日周四 02:10写道：
>
>
>
> On 2/26/2025 4:31 AM, Jun Nie wrote:
> > Currently, SSPPs are assigned to a maximum of two pipes. However,
> > quad-pipe usage scenarios require four pipes and involve configuring
> > two stages. In quad-pipe case, the first two pipes share a set of
> >
Instead of using .parent_names, use .parent_data, which binds parent
clocks by using relative names specified in DT in addition to using global
system clock names.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c | 6 +++---
1 file changed, 3 insertions(+), 3 del
LVDS support in MDP4 driver makes use of drm_connector directly. However
LCDC encoder and LVDS connector are wrappers around drm_panel. Switch
them to use drm_panel_bridge/drm_bridge_connector. This allows using
standard interface for the drm_panel and also inserting additional
bridges between enco
Link LVDS clocks to the from MDP4 to the MMCC and back from the MMCC
to the MDP4 display controller.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch
We can check the LCDC clock directly from the LCDC encoder driver, so
remove it from the LVDS connector.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 1 -
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 27
Drop the !COMMON_CLK stub for mpd4_lvds_pll_init(), the DRM_MSM driver
depends on COMMON_CLK.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.
The LVDS/LCDC controller uses pixel clock coming from the multimedia
controller (mmcc) rather than using the PLL directly. Stop using LVDS
PLL directly and register it as a clock provider. Use lcdc_clk as a
pixel clock for the LCDC.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
Add the LCDC / LVDS clock input and the XO used to drive internal LVDS
PLL to MDP4 controller bindings. The controller also provides LVDS PHY
PLL, so add optional #clock-cells to the device.
Acked-by: Rob Herring (Arm)
Signed-off-by: Dmitry Baryshkov
---
Documentation/devicetree/bindings/displa
The LCDC controller uses pixel clock provided by the multimedia clock
controller (mmcc) instead of using LVDS PHY clock directly. Link LVDS
clocks properly, taking MMCC into account.
MDP4 uses custom code to handle LVDS panel. It predates handling
EPROBE_DEFER, it tries to work when the panel devi
On Wed, 26 Feb 2025 at 06:22, Anusha Srivatsa wrote:
>
> Replace platform_get_resource + devm_ioremap
> with just devm_platform_ioremap_resource()
>
> Used Coccinelle to do this change. SmPl patch:
> @rule_2@
> identifier res;
> expression ioremap;
> identifier pdev;
> @@
> -struct resource *res;
On 2/26/2025 4:31 AM, Jun Nie wrote:
The stage contains configuration for a mixer pair. Currently the plane
supports just one stage and 2 pipes. Quad-pipe support will require
handling 2 stages and 4 pipes at the same time. In preparation for that
add a separate define, PIPES_PER_PLANE, to den
On Wed Feb 26, 2025 at 5:02 PM PST, Greg KH wrote:
> On Wed, Feb 26, 2025 at 07:47:30PM -0400, Jason Gunthorpe wrote:
>> The way misc device works you can't unload the module until all the
>> FDs are closed and the misc code directly handles races with opening
>> new FDs while modules are unloading
On Wed, Feb 26, 2025 at 07:47:30PM -0400, Jason Gunthorpe wrote:
> The way misc device works you can't unload the module until all the
> FDs are closed and the misc code directly handles races with opening
> new FDs while modules are unloading. It is quite a different scheme
> than discussed in thi
On Wed, Feb 26, 2025 at 07:47:30PM -0400, Jason Gunthorpe wrote:
[...]
>
> > Other abstractions do consider this though, e.g. the upcoming hrtimer work.
> > [1]
>
> Does it??? hrtimer uses function pointers. Any time you take a
> function pointer you have to reason about how does the .text lifet
On Wed, Feb 26, 2025 at 10:31:10PM +0100, Danilo Krummrich wrote:
> Let's take a step back and look again why we have Devres (and Revocable) for
> e.g. pci::Bar.
>
> The device / driver model requires that device resources are only held by a
> driver, as long as the driver is bound to the device.
On Wed, Feb 26, 2025 at 09:38:22AM -0400, Jason Gunthorpe wrote:
> On Wed, Feb 26, 2025 at 07:55:07AM +, Kasireddy, Vivek wrote:
>
> > > Is there any update or ETA for the v3? Are there any ways we can help?
>
> > I believe Leon's series is very close to getting merged. Once it
> > lands, thi
Add support for userspace to get various properties from a specified VM.
The currently supported properties are:
- The number of engine resets the VM has observed
- The number of exec queue bans the VM has observed, up to the last 50
relevant ones, and how many of those were caused by faults.
T
Add a counter to xe_vm that tracks the number of times an engine reset
has been observed with respect to the VM since creation.
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/xe/xe_guc_submit.c | 2 ++
drivers/gpu/drm/xe/xe_vm_types.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a
Dear Thomas,
Could you check if the patch got lost in review?
I can confirm that mainline is still broken since this 2024/May regression.
Thanks,
Nuno
On Wed, Dec 11, 2024 at 9:07 AM Thomas Zimmermann wrote:
>
> Hi
>
>
> Am 09.12.24 um 14:56 schrieb Nuno Gonçalves:
> > On Mon, Dec 9, 2024 at 1
Add additional information to the xe_vm so it can report the last 50
relevant exec queues that have been banned on it, as well as the
associated pagefault address and address type that caused the ban when
applicable. Since we cannot reasonably associate a pagefault to a
specific exec queue, whenev
Add additional information to vm so it can report up to the last 50
relevant exec queues to have been banned on it, as well as the last
pagefault seen when said exec queues were banned. Since we cannot
reasonably associate a pagefault to a specific exec queue, we
currently report the last seen pag
Add the exec queue id to the exec queue struct. This is useful for
performing a reverse lookup into the xef->exec_queue xarray.
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/xe/xe_exec_queue.c | 1 +
drivers/gpu/drm/xe/xe_exec_queue_types.h | 2 ++
2 files changed, 3 insertions(+)
d
Migrate the pagefault struct from xe_gt_pagefault.c to the
xe_gt_pagefault.h header file, along with the associated enum values.
v2: Normalize names for common header (Matt Brost)
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/xe/xe_gt_pagefault.c | 41 +---
drivers/
Make lookup_vma a static inline header function for xe_vm.
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/xe/xe_gt_pagefault.c | 25 +
drivers/gpu/drm/xe/xe_vm.h | 24
2 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/
On 2/26/2025 4:30 AM, Jun Nie wrote:
There are 2 pipes in a drm plane at most currently, while 4 pipes are
required for quad-pipe case. Generalize the handling to pipe pair and
ease handling to another pipe pair later. Store pipes in array with
removing dedicated r_pipe.
Signed-off-by: Jun Ni
On Mon, 24 Feb 2025 14:27:03 -0500
Yury Norov wrote:
> +#define parity(val) \
> +({ \
> + u64 __v = (val);\
> + int __ret; \
> +
reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/freescale/' for
20250226-initi
On Wed, Feb 26, 2025 at 12:38:51PM -0800, Andrew Morton wrote:
> On Wed, 26 Feb 2025 11:29:53 + Mark Brown wrote:
> > Please don't combine patches for multiple subsystems into a single
> > series if there's no dependencies between them, it just creates
> > confusion about how things get merge
On 26-02-2025 8:46 a.m., Krzysztof Kozlowski wrote:
On Tue, Feb 25, 2025 at 10:14:30PM +0100, Luca Weiss wrote:
Himax HX83112B is a display driver IC used to drive LCD DSI panels.
Describe it and the Fairphone 3 panel (98-03057-6598B-I) from DJN using
it.
Signed-off-by: Luca Weiss
---
.../bi
On Wed, Feb 26, 2025 at 01:21:20PM -0400, Jason Gunthorpe wrote:
> On Wed, Feb 26, 2025 at 02:16:58AM +0100, Danilo Krummrich wrote:
> > Again, the reason a pci::Bar needs to be revocable in Rust is that we can't
> > have
> > the driver potentially keep the pci::Bar alive (or even access it) after
In preparation to expose more info about bridges in debugfs, which will
require more insight into drm_bridge data structures, move the bridges_show
code to drm_bridge.c.
Suggested-by: Jani Nikula
Suggested-by: Dmitry Baryshkov
Signed-off-by: Luca Ceresoli
---
Changed in v8:
- add the file in
This series adds a /sys/kernel/debug/dri/bridges file showing all bridges
between drm_bridge_add() and drm_bridge_remove(), which might not be bound
to any encoder and thus not visible anywhere in debugfs.
It also cleans up the DRM bridge debugfs code by moving code to
drm_bridge.c.
Luca
Signed-
The global bridges_list holding all the bridges between drm_bridge_add()
and drm_bridge_remove() cannot be inspected via debugfs. Add a file showing
it.
To avoid code duplication, move the code printing a bridge info to a common
function.
Signed-off-by: Luca Ceresoli
---
Changed in v8:
- add t
Hello Jani,
On Wed, 26 Feb 2025 14:26:09 +0200
Jani Nikula wrote:
> > Moving the last 2 lines to drm_bridge.c and into a new function we'd
> > have:
> >
> > drm_encoder_register_all() [drm_encoder.c]
> > -> drm_debugfs_encoder_add [*][drm_de
Reviewed-by: Alex Hung
On 2/26/25 13:28, Vitaliy Shevtsov wrote:
There is a type mismatch between what CalculateDynamicMetadataParameters()
takes and what is passed to it. Currently this function accepts several
args as signed long but it's called with unsigned integers and integer. On
some sys
On Friday, 21 February 2025 00:41:41 Central European Standard Time Heiko
Stuebner wrote:
> When the drm-driver probes, it mainly creates the component device, where
> all the sub-drivers (vops, hdmi, etc) hook into.
>
> This will cause the shutdown handler to get called on shutdown, even
> thoug
On Wed, 26 Feb 2025 11:29:53 + Mark Brown wrote:
> On Tue, Feb 25, 2025 at 08:17:14PM +, Easwar Hariharan wrote:
> > This is the second series (part 1*) that converts users of
> > msecs_to_jiffies() that
> > either use the multiply pattern of either of:
> > - msecs_to_jiffies(N*1000) or
Em seg., 17 de fev. de 2025 às 02:37, Vignesh Raman
escreveu:
>
> Move common job configuration for software-driver
> stage jobs to separate job.
>
> Signed-off-by: Vignesh Raman
Acked-by: Helen Koike
> ---
>
> v2:
> - New patch in the series.
>
> v3:
> - No changes.
>
> ---
> drivers/gpu
There is a type mismatch between what CalculateDynamicMetadataParameters()
takes and what is passed to it. Currently this function accepts several
args as signed long but it's called with unsigned integers and integer. On
some systems where long is 32 bits and one of these unsigned int params is
gr
Em seg., 17 de fev. de 2025 às 02:37, Vignesh Raman
escreveu:
>
> We have enabled PROVE_LOCKING (which enables LOCKDEP) in drm-ci.
> This will output warnings when kernel locking errors are encountered
> and will continue executing tests. To detect if lockdep has been
> triggered, check the debug_
Em seg., 17 de fev. de 2025 às 02:37, Vignesh Raman
escreveu:
>
> Enable CONFIG_DEBUG_WW_MUTEX_SLOWPATH for mutex
> slowpath debugging.
>
> Signed-off-by: Vignesh Raman
Acked-by: Helen Koike
> ---
>
> v2:
> - New patch in the series.
>
> v3:
> - No changes.
>
> ---
> drivers/gpu/drm/ci/bu
Hi Dave, Simona,
Fixes for 6.14.
The following changes since commit d082ecbc71e9e0bf49883ee4afd435a77a5101b6:
Linux 6.14-rc4 (2025-02-23 12:32:57 -0800)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.14-2025-02-26
for you to fe
On Wed, 26 Feb 2025 at 20:36, Jessica Zhang wrote:
>
>
>
> On 2/26/2025 3:55 AM, Dmitry Baryshkov wrote:
> > On Thu, Jan 23, 2025 at 02:43:36PM +0200, Dmitry Baryshkov wrote:
> >> The MSM driver uses drm_atomic_helper_check() which mandates that none
> >> of the atomic_check() callbacks toggles cr
As established in commit 89d04995f76c ("MAINTAINERS: Drop Emma Anholt
from all M lines."), Emma is no longer active in the Linux kernel and
dropped the V3D maintainership. Therefore, remove Emma as one of the DT
maintainers and add the current V3D driver maintainer.
Cc: Krzysztof Kozlowski
Cc: Co
In addition to the standard reset controller, V3D 7.x requires configuring
the V3D_SMS registers for proper power on/off and reset. Add the new
registers to `v3d_regs.h` and ensure they are properly configured during
device probing, removal, and reset.
This change fixes GPU reset issues on the Ras
V3D 7.1 exposes a new register block, called V3D_SMS. As BCM2712 has a
V3D 7.1 core, add a new register item to the list. Similar to the GCA
and bridge register, SMS is optional and should only be added for V3D
7.1 variants.
Cc: Krzysztof Kozlowski
Cc: Conor Dooley
Cc: Nicolas Saenz Julienne
Cc
The V3D driver currently determines the GPU tech version (33, 41...)
by reading a register. This approach has worked so far since this
information wasn’t needed before powering on the GPU.
V3D 7.1 introduces new registers that must be written to power on the
GPU, requiring us to know the V3D versi
The V3D driver still relies on `drm_sched_increase_karma()` and
`drm_sched_resubmit_jobs()` for resubmissions when a timeout occurs.
The function `drm_sched_increase_karma()` marks the job as guilty, while
`drm_sched_resubmit_jobs()` sets an error (-ECANCELED) in the DMA fence of
that guilty job.
Similar to commit e4b5ccd392b9 ("drm/v3d: Ensure job pointer is set to
NULL after job completion"), ensure the job pointer is set to `NULL` when
a job's fence has an error. Failing to do so can trigger kernel warnings
in specific scenarios, such as:
1. v3d_csd_job_run() assigns `v3d->csd_job = job
Applied. Thanks!
On Wed, Feb 26, 2025 at 8:11 AM André Almeida wrote:
>
> Prior to the addition of ring reset, the debug option
> `debug_disable_soft_recovery` could be used to force a full device
> reset. Now that we have ring reset, create a debug option to disable
> them in amdgpu, forcing th
Applied. Thanks!
Alex
On Wed, Feb 26, 2025 at 2:04 PM Alex Hung wrote:
>
> Reviewed-by: Alex Hung
>
> On 2/26/25 01:37, Ma Ke wrote:
> > Null pointer dereference issue could occur when pipe_ctx->plane_state
> > is null. The fix adds a check to ensure 'pipe_ctx->plane_state' is not
> > null bef
Thanks for the poke! This patch looks fine to me:
Reviewed-by: Lyude Paul
I'll push it to drm-misc in a moment
On Wed, 2025-02-26 at 10:02 +0100, Thomas Zimmermann wrote:
> Ping. Are there any comments on this patch?
>
> Am 14.01.25 um 10:57 schrieb Thomas Zimmermann:
> > Keep user-forced conn
On 2/26/25 04:10, Vitaliy Shevtsov wrote:
There is a type mismatch between what CalculateDynamicMetadataParameters()
takes and what is passed to it. Currently this function accepts several
args as signed long but it's called with unsigned integers. On some systems
where long is 32 bits and one
Reviewed-by: Alex Hung
On 2/26/25 01:37, Ma Ke wrote:
Null pointer dereference issue could occur when pipe_ctx->plane_state
is null. The fix adds a check to ensure 'pipe_ctx->plane_state' is not
null before accessing. This prevents a null pointer dereference.
Found by code review.
Cc: sta...@
On 2/26/2025 3:55 AM, Dmitry Baryshkov wrote:
On Thu, Jan 23, 2025 at 02:43:36PM +0200, Dmitry Baryshkov wrote:
The MSM driver uses drm_atomic_helper_check() which mandates that none
of the atomic_check() callbacks toggles crtc_state->mode_changed.
Perform corresponding check before calling t
Bifrost MMUs support AArch64 4kB granule specification. However,
panfrost only enables MMU in legacy mode, despite the presence of the
HW_FEATURE_AARCH64_MMU feature flag.
This commit adds support to use page tables according to AArch64 4kB
granule specification. This feature is enabled conditiona
On Wed, Feb 26, 2025 at 08:14:14AM +0100, Jiri Slaby wrote:
> On 25. 02. 25, 14:29, Kuan-Wei Chiu wrote:
> > > +#define parity(val) \
> > > +({ \
> > > + u64 __v = (val);\
> >
Mali Bifrost MMU support AArch64 4kB page tables. This feature is in
panfrost based the HW_FEATURE_AARCH64_MMU feature flag.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_features.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost
The TRANSTAB (Translation table base address) layout is different
depending on the legacy mode configuration.
Currently, the defined values apply to the legacy mode. Let's rename
them so we can add the ones for no-legacy mode.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfr
Hi all,
This is a RFC related to AArch64 page table format support in panfrost.
Currently, only MMU in legacy mode is supported, but Bifrost GPUs use
the standard format LPAE S1 page tables.
There's a previous similar thread on this topic from 2019-May [0], which
got stalled. This RFC is an attem
As done in panthor, define and use these GPU_MMU_FEATURES_* macros,
which makes code easier to read and reuse.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_mmu.c | 6 --
drivers/gpu/drm/panfrost/panfrost_regs.h | 2 ++
2 files changed, 6 insertions(+), 2 deletions
From: Aradhya Bhatia
The OLDI transmitters (TXes) do not have registers of their own, and are
dependent on the source video-ports (VPs) from the DSS to provide
configuration data. This hardware doesn't directly sit on the internal
bus of the SoC, but does so via the DSS. Hence, the OLDI TXes are
From: Aradhya Bhatia
The AM62x and AM62Px SoCs feature 2 OLDI TXes each, which makes it
possible to connect them in dual-link or cloned single-link OLDI display
modes. The current OLDI support in tidss_dispc.c can only support for
a single OLDI TX, connected to a VP and doesn't really support
con
The dss dt schema and the tidss driver have kept the single-link OLDI in
AM65x integrated with the parent video-port (VP) from DSS (as the OLDI
configuration happens from the source VP only).
To help configure the dual-lvds modes that the OLDI has to offer in
devices AM62x and later, a new OLDI bri
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