Am 26.01.25 um 10:32 schrieb Zhaoyu Liu:
TTM always uses pin_count and ttm_resource_is_swapped() together to
determine whether a BO is unevictable.
Now use ttm_resource_unevictable() to replace them.
Signed-off-by: Zhaoyu Liu
Reviewed-by: Christian König
I will pick this up for drm-misc-nex
On 03.02.2025 23:59, Rodrigo Vivi wrote:
> On Tue, Jan 21, 2025 at 09:42:17AM -0500, Rodrigo Vivi wrote:
>> On Sat, Jan 18, 2025 at 06:47:27PM +0100, Michal Wajdeczko wrote:
>>>
>>>
>>> On 17.01.2025 22:57, Vinay Belgaumkar wrote:
Default SLPC power profile is Base(0). Power Saving mode(1)
From: André Almeida
Use DRM's device wedged event to notify userspace that a reset had
happened. For now, only use `none` method meant for telemetry
capture.
In the future we might want to report a recovery method if the reset didn't
succeed.
Acked-by: Shashank Sharma
Signed-off-by: André Alme
Now that we have device wedged event provided by DRM core, make use
of it and support both driver rebind and bus-reset based recovery.
With this in place, userspace will be notified of wedged device on
gt reset failure.
Signed-off-by: Raag Jadav
Reviewed-by: Aravind Iddamsetty
---
drivers/gpu/d
This series introduces device wedged event in DRM subsystem and uses it
in xe, i915 and amdgpu drivers. Detailed description in commit message.
This was earlier attempted as xe specific uevent in v1 and v2 on [1].
Similar work by André Almeida on [2].
Wedged event support for amdgpu by André Almei
This was previously attempted as xe specific reset uevent but dropped
in commit 77a0d4d1cea2 ("drm/xe/uapi: Remove reset uevent for now")
as part of refactoring.
Now that we have device wedged event provided by DRM core, make use
of it and support both driver rebind and bus-reset based recovery.
W
Add documentation for device wedged event in a new "Device wedging"
chapter. This describes basic definitions, prerequisites and consumer
expectations along with an example.
v8: Improve introduction (Christian, Rodrigo)
v9: Add prerequisites section (Christian)
v10: Clarify mmap cleanup and cons
Introduce device wedged event, which notifies userspace of 'wedged'
(hanged/unusable) state of the DRM device through a uevent. This is
useful especially in cases where the device is no longer operating as
expected and has become unrecoverable from driver context. Purpose of
this implementation is
Enable display for AM62L DSS [1] which supports only a single display
pipeline using a single overlay manager, single video port and a single
video lite pipeline which does not support scaling.
The output of video port is routed to SoC boundary via DPI interface and
the DPI signals from the video
This adds support for DSS subsystem present in TI's AM62L SoC
which supports single display pipeline with DPI output which
is also routed to DSI Tx controller within the SoC.
Change Log:
V2:
- Fix incorrect format of compatible string (comma instead of
hyphen) for AM62L SoC
- Use separate regist
The DSS controller on TI's AM62L SoC is an update from that on TI's
AM625/AM65x/AM62A7 SoC. The AM62L DSS [1] only supports a single display
pipeline using a single overlay manager, single video port and a single
video lite pipeline which does not support scaling.
The output of video port is route
Hi
>
>-Original Message-
>From: Dmitry Baryshkov
>Sent: Tuesday, February 4, 2025 1:28 AM
>To: Hermes Wu (吳佳宏)
>Cc: Andrzej Hajda ; Neil Armstrong
>; Robert Foss ; Laurent Pinchart
>; Jonas Karlman ; Jernej
>Skrabec ; Maarten Lankhorst
>; Maxime Ripard ;
>Thomas Zimmermann ; David A
The current code can issue CDMA flushes (DMAPUT bumps) in the middle
of a job, before all opcodes have been written into the pushbuffer.
This can happen when pushbuffer fills up. Presumably this made sense
at some point in the past, but it doesn't anymore, as it cannot lead
to more space appearing
On Mon, Feb 03, 2025 at 04:25:59PM -0800, Abhinav Kumar wrote:
>
>
> On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
> > Setup the HDMI connector on the MSM HDMI outputs. Make use of
> > atomic_check hook and of the provided Infoframe infrastructure.
> >
>
> By atomic_check are you referring to t
On Mon, Feb 03, 2025 at 11:34:00AM -0800, Abhinav Kumar wrote:
>
>
> On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
> > The mode_set callback is deprecated, it doesn't get the
> > drm_bridge_state, just mode-related argumetns. Also Abhinav pointed out
> > that HDMI timings should be programmed aft
On Mon, Feb 03, 2025 at 09:14:26PM +0300, Danila Tikhonov wrote:
> From: Eugene Lepshy
>
> DRM DSC helper has parameters for various bpc values other than 8:
> (8/10/12/14/16).
>
> Remove this guard.
>
> Signed-off-by: Eugene Lepshy
> Signed-off-by: Danila Tikhonov
> ---
> drivers/gpu/drm/
On Mon, Feb 03, 2025 at 04:23:56PM -0300, raf...@beims.me wrote:
> From: Rafael Beims
>
> Add support for HDMI codec with audio coming from the I2S input.
> Support 48kHz and 96kHz sample rate, with 16 bits word size.
>
> Co-developed-by: João Paulo Gonçalves
> Signed-off-by: João Paulo Gonçalv
On Mon, 3 Feb 2025 10:39:58 +0200 "Kirill A. Shutemov"
wrote:
> > diff --git a/mm/filemap.c b/mm/filemap.c
> > index 4fe551037bf7..98493443d120 100644
> > --- a/mm/filemap.c
> > +++ b/mm/filemap.c
> > @@ -1605,8 +1605,9 @@ static void folio_end_reclaim_write(struct folio
> > *folio)
> >
On 2/3/2025 2:57 AM, Abel Vesa wrote:
Link Training Tunable PHY Repeaters (LTTPRs) are defined in DisplayPort
1.4a specification. As the name suggests, these PHY repeaters are
capable of adjusting their output for link training purposes.
According to the DisplayPort standard, LTTPRs have two
On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
Setup the HDMI connector on the MSM HDMI outputs. Make use of
atomic_check hook and of the provided Infoframe infrastructure.
By atomic_check are you referring to the
msm_hdmi_bridge_tmds_char_rate_valid()?
Also please confirm if HDMI audio w
On 2025-02-03 8:29 a.m., Andi Shyti wrote:
Hi,
Please, next time, do not remove the mailing and the other folks
you cc'ed.
I'm adding back the mailing list and Daniele who has commented
before.
Thanks, I also found my previous response click on "reply", not the
"reply all".
...
Clos
Just found my previous response click on "reply", not the "reply all",
so add Cc list.
Regards,
Zhanjun Dong
Forwarded Message
Subject: Re: [PATCH v1] drm/i915/guc: Always disable interrupt ahead of
synchronize_irq
Date: Mon, 27 Jan 2025 17:17:33 -0500
From: Dong, Zhanjun
On Mon, 03 Feb 2025 16:23:55 -0300, raf...@beims.me wrote:
> From: Rafael Beims
>
> Add the I2S audio input port for audio over HDMI support.
>
> Signed-off-by: Rafael Beims
> ---
> .../bindings/display/bridge/lontium,lt8912b.yaml | 8
> 1 file changed, 8 insertions(+)
>
On Mon, 03 Feb 2025 21:14:24 +0300, Danila Tikhonov wrote:
> The Visionox RM692E5 is a 6.55” AMOLED panel used in Nothing Phone (1)
> (sm7325-nothing-spacewar).
>
> Signed-off-by: Danila Tikhonov
> ---
> .../display/panel/visionox,rm692e5.yaml | 77 +++
> 1 file changed,
On Tue, Jan 21, 2025 at 09:42:17AM -0500, Rodrigo Vivi wrote:
> On Sat, Jan 18, 2025 at 06:47:27PM +0100, Michal Wajdeczko wrote:
> >
> >
> > On 17.01.2025 22:57, Vinay Belgaumkar wrote:
> > > Default SLPC power profile is Base(0). Power Saving mode(1)
> > > has conservative up/down thresholds an
On Sun, Feb 02, 2025 at 10:14:31PM +, Colin Ian King wrote:
> There is a spelling mistake in an error message. Fix it.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu
On Mon, Feb 3, 2025 at 4:00 PM John Hubbard wrote:
[..]
>
> >> +()
> >> +)]
> >> +);
> >> +
> >> +impl pci::Driver for NovaCore {
> >> +type IdInfo = ();
> >> +const ID_TABLE: pci::IdTable = &PCI_TABLE;
> >> +
> >> +fn probe(pdev: &mut pci::Device, _info: &Self::IdInfo) ->
On Mon, Feb 03, 2025 at 09:19:59AM +0100, Greg Kroah-Hartman wrote:
> On Sun, Feb 02, 2025 at 12:54:07PM -0800, Linus Torvalds wrote:
> > Greg, Luis, can you explain that odd uevent message / netlink issue?
>
> There was reports from Android devices that the uevent was causing the
> system to wake
On Mon, Feb 3, 2025 at 11:17 AM Biju Das wrote:
>
> Hi Rob,
>
> +Cc relevant subsystems.
>
> > -Original Message-
> > From: Rob Herring
> > Sent: 03 February 2025 16:53
> > Subject: Re: [PATCH v2] of: base: Add of_get_available_child_by_name()
> >
> > On Sat, Feb 1, 2025 at 3:31 AM Biju D
From: Thomas Tai Sent: Thursday, January 30, 2025 12:44
PM
>
> > -Original Message-
> > From: Michael Kelley
> > Sent: Thursday, January 30, 2025 3:20 PM
> > To: Thomas Tai ; mhkelle...@gmail.com;
> > haiya...@microsoft.com; wei@kernel.org; de...@microsoft.com;
> > drawat.fl...@gmai
On 2/3/25 12:24 PM, Joel Fernandes wrote:
Hi Danilo,
On Fri, Jan 31, 2025 at 11:04:24PM +0100, Danilo Krummrich wrote:
...
+const BAR0_SIZE: usize = 8;
+pub(crate) type Bar0 = pci::Bar;
+
+kernel::pci_device_table!(
+PCI_TABLE,
+MODULE_PCI_TABLE,
+::IdInfo,
+[(
+pci::Dev
-t830"
# "arm,mali-t880"
reg:
---
base-commit: df4b2bbff898227db0c14264ac7edd634e79f755
change-id: 20250203-exynos7870-gpu-ccb918e23b2e
Best regards,
--
Kaustabh Chakraborty
Hi Danilo,
On Fri, Jan 31, 2025 at 11:04:24PM +0100, Danilo Krummrich wrote:
> Add the initial nova-core driver stub.
>
> nova-core is intended to serve as a common base for nova-drm (the
> corresponding DRM driver) and the vGPU manager VFIO driver, serving as a
> hard- and firmware abstraction l
Applied. Thanks!
Alex
On Sun, Feb 2, 2025 at 5:08 PM wrote:
>
> From: "Dr. David Alan Gilbert"
>
> Another small pile of deadcode patches.
>
> Signed-off-by: Dr. David Alan Gilbert
>
>
> Dr. David Alan Gilbert (7):
> drm/amd/display: Remove unused mpc1_is_mpcc_idle
> drm/amd/display: Remo
Applied. Thanks!
Alex
On Fri, Jan 31, 2025 at 5:38 PM Nathan Chancellor wrote:
>
> Currently, there are several files in drm/amd/display that aim to have a
> higher -Wframe-larger-than value to avoid instances of that warning with
> a lower value from the user's configuration. However, with the
CC'ed: driv-devel
On 2/2/25 13:39, Kajtár Zsolt wrote:
A series on de-duplicating the common cfb and sys drawing routines will
follow.
Some background:
It happens that I need to use both cfb and sys drawing routines.
For which driver do you need this?
At low resolution where the aperture i
On 2/2/25 21:33, Kajtár Zsolt wrote:
The erase colour calculation for fbcon clearing should use get_color instead
of attr_col_ec, like everything else. The latter is similar but is not correct.
For example it's missing the depth dependent remapping and doesn't care about
blanking.
The problem ca
On 2/1/25 09:18, Soci/Singular wrote:
I was wondering why there's garbage at the bottom of the screen when
tile blitting is used with an odd mode like 1080, 600 or 200. Sure there's
only space for half a tile but the same area is clean when the buffer
is bitmap.
Then later I found that it's supp
On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
The mode_set callback is deprecated, it doesn't get the
drm_bridge_state, just mode-related argumetns. Also Abhinav pointed out
that HDMI timings should be programmed after setting up HDMI PHY and
PLL. Rework the code to program HDMI timings at the
Hello,
syzbot has tested the proposed patch and the reproducer did not trigger any
issue:
Reported-by: syzbot+a504cb5bae4fe117b...@syzkaller.appspotmail.com
Tested-by: syzbot+a504cb5bae4fe117b...@syzkaller.appspotmail.com
Tested on:
commit: d1302efc selftests/udmabuf: add a test to pin
On Sun, Feb 02, 2025 at 06:28:08AM -0800, Guenter Roeck wrote:
> On 2/2/25 05:27, David Laight wrote:
> > On Tue, 21 Jan 2025 15:15:09 -0800
> > Linus Torvalds wrote:
> >
> > > On Tue, 21 Jan 2025 at 14:59, Rodrigo Vivi wrote:
> > > >
> > > > I'm pushing this soon to drm-intel-next, unless Linu
>
> syzbot has found a reproducer for the following issue on:
>
> HEAD commit:69e858e0b8b2 Merge tag 'uml-for-linus-6.14-rc1' of git://g..
> git tree: upstream
> console+strace: https://syzkaller.appspot.com/x/log.txt?x=1431cb2458
> kernel config: https://syzkaller.appspot.com/x/.c
From: Eugene Lepshy
DRM DSC helper has parameters for various bpc values other than 8:
(8/10/12/14/16).
Remove this guard.
Signed-off-by: Eugene Lepshy
Signed-off-by: Danila Tikhonov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --
From: Eugene Lepshy
Enable the Adreno GPU and configure the Visionox RM692E5 panel.
Signed-off-by: Eugene Lepshy
Co-developed-by: Danila Tikhonov
Signed-off-by: Danila Tikhonov
---
Note:
Depends on
https://lore.kernel.org/linux-arm-msm/20250122-dpu-111-topology-v2-1-505e95964...@somainline.o
The Visionox RM692E5 is a 6.55” AMOLED panel used in Nothing Phone (1)
(sm7325-nothing-spacewar).
Signed-off-by: Danila Tikhonov
---
.../display/panel/visionox,rm692e5.yaml | 77 +++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/dis
From: Eugene Lepshy
Add the driver for Visionox RM692E5 panel support found in Nothing
Phone (1).
Signed-off-by: Eugene Lepshy
Co-developed-by: Danila Tikhonov
Signed-off-by: Danila Tikhonov
---
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile
This patch series adds support for the Visionox RM692E5 panel, which is
used on the Nothing Phone (1) and then adds it to the DTS.
But before adding to DTS we need to allow all bpc values in DSC code,
because Visionox RM692E5 has a bpc value of 10. Also we need to make sure
that the DSC patch fo
On Mon, 03 Feb 2025 21:24:31 +0530, Devarsh Thakkar wrote:
> Fix incorrect format of compatible string (comma instead of hyphen) for
> TI's AM62A7 SoC.
>
> s/ti,am62a7,dss/ti,am62a7-dss
>
> Fixes: 7959ceb767e4 ("dt-bindings: display: ti: Add support for am62a7 dss")
> Reviewed-by: Krzysztof Koz
On 1/31/25 16:39, Matt Coster wrote:
> On 28/01/2025 19:48, Michal Wilczynski wrote:
>> Add reset controller driver for the T-HEAD TH1520 SoC that manages
>> hardware reset lines for various subsystems. The driver currently
>> implements support for GPU reset control, with infrastructure in plac
Use DC_LOG_DEBUG instead of pr_info to match other uses in dc.c.
Fixes: eb8eec752038 ("drm/amd/display: Add debug messages for
dc_validate_boot_timing()")
Reviewed-by: Mario Limonciello
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+
Hi,
On Sat, Feb 1, 2025 at 10:55 AM Tejas Vipin wrote:
>
> Changes the sharp-ls060t1sx01 panel to use multi style functions for
Not worth spinning for this, but s/Changes/Change/
> improved error handling.
>
> Signed-off-by: Tejas Vipin
> ---
> .../gpu/drm/panel/panel-sharp-ls060t1sx01.c |
On Mon, Feb 03, 2025 at 06:29:21PM +0100, Krzysztof Kozlowski wrote:
> Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to
> avoid hard-coding bit masks and shifts and make the code a bit more
> readable. While touching the lines in dsi_7nm_pll_save_state()
> resulting cached->pix
On 1/31/25 16:39, Matt Coster wrote:
> On 28/01/2025 19:48, Michal Wilczynski wrote:
>> Add bindings for the PowerVR BXM-4-64 GPU integrated in the T-HEAD
>> TH1520 SoC. This GPU requires two clocks.
>
> None of the IMG Rogue GPUs use two clocks; they're all either one or
> three. The TRM for
On Mon, Feb 03, 2025 at 11:01:28AM +0100, Maxime Ripard wrote:
> Hi Dmitry,
>
> On Thu, Jan 16, 2025 at 03:08:00AM +0200, Dmitry Baryshkov wrote:
> > On Wed, Jan 15, 2025 at 10:05:36PM +0100, Maxime Ripard wrote:
> > > The TI sn65dsi86 driver follows the drm_encoder->crtc pointer that is
> > > dep
On Mon, Feb 03, 2025 at 06:29:18PM +0100, Krzysztof Kozlowski wrote:
> PHY_CMN_CLK_CFG0 register is updated by the PHY driver and by two
> divider clocks from Common Clock Framework:
> devm_clk_hw_register_divider_parent_hw(). Concurrent access by the
> clocks side is protected with spinlock, howe
On Mon, Feb 03, 2025 at 06:29:19PM +0100, Krzysztof Kozlowski wrote:
> PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux
> clock from Common Clock Framework:
> devm_clk_hw_register_mux_parent_hws(). There could be a path leading to
> concurrent and conflicting updates between PHY
On Mon, Feb 03, 2025 at 06:29:20PM +0100, Krzysztof Kozlowski wrote:
> PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI
> clock divider, source of bitclk and two for enabling the DSI PHY PLL
> clocks.
>
> dsi_7nm_set_usecase() sets only the source of bitclk, so should leave
On Mon, Feb 03, 2025 at 05:16:05PM +0100, Herve Codina wrote:
> The current code uses a the reset_pipe() local function to reset the
> CRTC outputs.
>
> drm_atomic_helper_reset_crtc() has been introduced recently and it
> performs exact same operations.
>
> In order to avoid code duplication, use
On Mon, Feb 03, 2025 at 05:16:04PM +0100, Herve Codina wrote:
> drm_atomic_helper_reset_crtc() allows to reset the CRTC active outputs.
>
> This resets all active components available between the CRTC and
> connectors.
>
> Signed-off-by: Herve Codina
> ---
> drivers/gpu/drm/drm_atomic_helper.c
Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to
avoid hard-coding bit masks and shifts and make the code a bit more
readable. While touching the lines in dsi_7nm_pll_save_state()
resulting cached->pix_clk_div assignment would be too big, so just
combine pix_clk_div and bit_clk
PHY_CMN_CLK_CFG0 register is updated by the PHY driver and by two
divider clocks from Common Clock Framework:
devm_clk_hw_register_divider_parent_hw(). Concurrent access by the
clocks side is protected with spinlock, however driver's side in
restoring state is not. Restoring state is called from
PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI
clock divider, source of bitclk and two for enabling the DSI PHY PLL
clocks.
dsi_7nm_set_usecase() sets only the source of bitclk, so should leave
all other bits untouched. Use newly introduced
dsi_pll_cmn_clk_cfg1_update() t
PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux
clock from Common Clock Framework:
devm_clk_hw_register_mux_parent_hws(). There could be a path leading to
concurrent and conflicting updates between PHY driver and clock
framework, e.g. changing the mux and enabling PLL clocks.
Changes in v2:
- Add Fixes tag
- New patch #4
- Link to v1:
https://lore.kernel.org/r/20250131-drm-msm-phy-pll-cfg-reg-v1-0-3b99efeb2...@linaro.org
Calling these improvements, not fixes, because I don't think we ever hit
actual concurrency issue. Although if we ever hit it, it would be very
tric
On Mon, Feb 03, 2025 at 02:04:30PM +0800, Hermes Wu via B4 Relay wrote:
> From: Hermes Wu
>
> For supporting audio form I2S to DP audio data sub stream.
> Add hdmi_audio callbacks to drm_bridge_funcs for the
> HDMI codec framework. The DRM_BRIDGE_OP_HDMI flag in bridge.ops
> must be set, and hdmi
HDMI audio is available on the Rock 5B HDMI TX port.
Enable it.
Signed-off-by: Detlev Casanova
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
b/arch/arm64/boot/dts/rockchip/rk3588-ro
Use the simple-audio-card driver with the hdmi0 QP node as CODEC and
the i2s5 device as CPU.
The simple-audio-card,mclk-fs value is set to 128 as it is done in
the downstream driver.
The #sound-dai-cells value is set to 0 in the hdmi0 node so that it can be
used as an audio codec node.
Signed-of
To support HDMI audio on the rk3588 based devices, the generic HDMI
Codec framework is used in the dw-hdmi-qp DRM bridge driver.
The implementation is mainly based on the downstream driver, ported to the
generic HDMI Codec framework [1] recently merged in the master branch.
The parameters computat
From: Sugar Zhang
Register the dw-hdmi-qp bridge driver as an HDMI audio codec.
The register values computation functions (for n) are based on the
downstream driver, as well as the register writing functions.
The driver uses the generic HDMI Codec framework in order to implement
the HDMI audio
Hi Rob,
+Cc relevant subsystems.
> -Original Message-
> From: Rob Herring
> Sent: 03 February 2025 16:53
> Subject: Re: [PATCH v2] of: base: Add of_get_available_child_by_name()
>
> On Sat, Feb 1, 2025 at 3:31 AM Biju Das wrote:
> >
> > There are lot of drivers using of_get_child_by_na
On Mon, 3 Feb 2025 22:46:15 +0900
Asahi Lina wrote:
> Hi,
>
> On 2/3/25 6:21 PM, Boris Brezillon wrote:
> > +Akash with whom we've been discussing adding a 'REPEAT' mode to
> > drm_gpuvm/panthor.
> >
> > On Sun, 2 Feb 2025 19:53:47 +0100
> > Danilo Krummrich wrote:
> >
> >> Hi Lina,
> >>
>
Hi Maxime, Nicolas
On 30/01/2025 17:47, Nicolas Dufresne wrote:
> Le jeudi 30 janvier 2025 à 17:38 +0100, Maxime Ripard a écrit :
>> Hi Nicolas,
>>
>> On Thu, Jan 30, 2025 at 10:59:56AM -0500, Nicolas Dufresne wrote:
>>> Le jeudi 30 janvier 2025 à 14:46 +0100, Maxime Ripard a écrit :
Hi,
On 1/31/25 16:39, Matt Coster wrote:
> On 28/01/2025 19:48, Michal Wilczynski wrote:
>> The T-Head TH1520 SoC integrates a variety of clocks for its subsystems,
>> including the Application Processor (AP) and the Video Output (VO) [1].
>> Up until now, the T-Head clock driver only supported AP c
On 1/31/25 16:39, Matt Coster wrote:
> On 28/01/2025 19:47, Michal Wilczynski wrote:
>> The LicheePi 4A board, featuring the T-HEAD TH1520 SoC, includes an
>> Imagination
>> Technologies BXM-4-64 GPU. Initial support for this GPU was provided through
>> a
>> downstream driver [1]. Recently, ef
On Mon, Feb 03, 2025 at 04:49:34PM +0100, Simona Vetter wrote:
> On Fri, Jan 31, 2025 at 06:28:57PM +, Lorenzo Stoakes wrote:
> > in the fb_defio video driver, page dirty state is used to determine when
> > frame buffer pages have been changed, allowing for batched, deferred I/O to
> > be perfo
Hi Dmitry,
On Mon, 3 Feb 2025 17:56:46 +0200
Dmitry Baryshkov wrote:
> On Mon, Feb 03, 2025 at 03:58:22PM +0100, Herve Codina wrote:
> > The current code uses a the reset_pipe() local function to reset the
> > CRTC outputs.
> >
> > drm_atomic_helper_reset_crtc() has been introduced recently and
Hi Dmitry,
On Mon, 3 Feb 2025 17:56:33 +0200
Dmitry Baryshkov wrote:
> On Mon, Feb 03, 2025 at 03:58:21PM +0100, Herve Codina wrote:
> > drm_atomic_helper_reset_crtc() allows to reset the CRTC active outputs.
> >
> > This resets all active components available between the CRTC and
> > connector
Hi Rob
On 30/01/2025 23:20, Rob Herring wrote:
>
> Why would panthor need CMA, it has an MMU.
>
> In any case, I agree with Maxime that this is redundant.
>
This is correct, the GPU has an MMU. The reason I introduced this custom
CMA DTB entry is to allow creation of a standalone DMA heap whic
Both the TI SN65DSI83 and SN65DSI84 bridges have an IRQ pin to signal
errors using interrupt.
This interrupt is not documented in the binding.
Add the missing interrupts property.
Signed-off-by: Herve Codina
Reviewed-by: Laurent Pinchart
Acked-by: Conor Dooley
---
.../devicetree/bindings/dis
In some cases observed during ESD tests, the TI SN65DSI83 cannot recover
from errors by itself. A full restart of the bridge is needed in those
cases to have the bridge output LVDS signals again.
Also, during tests, cases were observed where reading the status of the
bridge was not even possible.
The current code uses a the reset_pipe() local function to reset the
CRTC outputs.
drm_atomic_helper_reset_crtc() has been introduced recently and it
performs exact same operations.
In order to avoid code duplication, use the new helper instead of the
local function.
Signed-off-by: Herve Codina
drm_atomic_helper_reset_crtc() allows to reset the CRTC active outputs.
This resets all active components available between the CRTC and
connectors.
Signed-off-by: Herve Codina
---
drivers/gpu/drm/drm_atomic_helper.c | 41 +
include/drm/drm_atomic_helper.h | 2 +
Hi,
Usually the TI SN65DSI83 recovers from error by itself but during ESD
tests, we have some cases where the TI SN65DSI83 didn't recover.
In order to handle those cases, this series adds support for a recovery
mechanism.
Compare to the previous iteration, this v5 series fixes the v4 series
beca
On Sun, Feb 02, 2025 at 01:02:47PM +0900, Inki Dae wrote:
> 2025년 2월 1일 (토) 오전 1:56, Bjorn Helgaas 님이 작성:
> >
> > I don't know this code at all, so this is likely just noise, but the
> > wait_event_timeout() usage in decon_wait_for_vblank() looks funny to
> > me.
> >
> > decon_wait_for_vblank() wai
On Mon, Feb 03, 2025 at 03:58:22PM +0100, Herve Codina wrote:
> The current code uses a the reset_pipe() local function to reset the
> CRTC outputs.
>
> drm_atomic_helper_reset_crtc() has been introduced recently and it
> performs exact same operations.
>
> In order to avoid code duplication, use
Hi all,
Oops, this series doesn't apply on top of v6.14-rc1. My bad, sorry about
that.
Please ignore this series. I will send soon a new iteration fixed.
Apologies,
Hervé
On Mon, 3 Feb 2025 15:58:19 +0100
Herve Codina wrote:
> Hi,
>
> Usually the TI SN65DSI83 recovers from error by itself b
On Mon, Feb 03, 2025 at 03:58:21PM +0100, Herve Codina wrote:
> drm_atomic_helper_reset_crtc() allows to reset the CRTC active outputs.
>
> This resets all active components available between the CRTC and
> connectors.
>
> Signed-off-by: Herve Codina
> ---
> drivers/gpu/drm/drm_atomic_helper.c
Fix incorrect format of compatible string (comma instead of hyphen) for
TI's AM62A7 SoC.
s/ti,am62a7,dss/ti,am62a7-dss
Fixes: 7959ceb767e4 ("dt-bindings: display: ti: Add support for am62a7 dss")
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Devarsh Thakkar
---
V2: Add Reviewed-by and update
On Fri, Jan 31, 2025 at 06:28:57PM +, Lorenzo Stoakes wrote:
> in the fb_defio video driver, page dirty state is used to determine when
> frame buffer pages have been changed, allowing for batched, deferred I/O to
> be performed for efficiency.
>
> This implementation had only one means of doi
On 03/02/2025 15:03, Devarsh Thakkar wrote:
> Fix compatible string for AM62A7 DSS.
Fix incorrect format of compatible string (comma instead of hyphen) for
> s/ti,am62a7,dss/ti,am62a7-dss
>
> Fixes: 7959ceb767e4 ("dt-bindings: display: ti: Add support for am62a7 dss")
> Signed-off-by: Devars
struct pvr_gem_object *pvr_obj, u64 pvr_obj_offset,
u64 device_addr, u64 size);
+int pvr_vm_unmap_obj(struct pvr_vm_context *vm_ctx,
+struct pvr_gem_object *pvr_obj,
+u64 device_addr, u64 size);
int pvr_vm_unmap(struct pvr_vm_context *vm_ctx, u64 device_
release work structure. */
+ struct work_struct release_work;
};
/**
---
base-commit: 3ab334814dc7dff39075e055e12847d51878916e
change-id: 20250203-fence-release-deadlock-a0753c07bfdd
Best regards,
--
Brendan King
From: Brendan King
Ensure job done fences are only initialised once.
This fixes a memory manager not clean warning from drm_mm_takedown
on module unload.
Signed-off-by: Brendan King
---
drivers/gpu/drm/imagination/pvr_queue.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --
Hi Krzysztof
On 30/01/2025 13:25, Krzysztof Kozlowski wrote:
> On 30/01/2025 14:08, Florent Tomasin wrote:
>> Allow mali-valhall-csf driver to retrieve a protected
>> heap at probe time by passing the name of the heap
>> as attribute to the device tree GPU node.
>
> Please wrap commit message acc
Add some basic tests for exercising entity priority handling.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
.../scheduler/tests/drm_sched_tests_basic.c | 95 ++-
1 file changed, 94 insertions(+), 1 deletion(
Add a basic test for exercising modifying the entities scheduler list at
runtime.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
.../scheduler/tests/drm_sched_tests_basic.c | 66 ++-
1 file changed, 65 insert
Add a basic test for exercising modifying the entities scheduler list at
runtime.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
.../scheduler/tests/drm_sched_tests_basic.c | 66 ++-
1 file changed, 65 insert
Implement a mock scheduler backend and add some basic test to exercise the
core scheduler code paths.
Mock backend (kind of like a very simple mock GPU) can either process jobs
by tests manually advancing the "timeline" job at a time, or alternatively
jobs can be configured with a time duration in
There has repeatedly been quite a bit of apprehension when any change to the DRM
scheduler is proposed, with two main reasons being code base is considered
fragile, not well understood and not very well documented, and secondly the lack
of systematic testing outside the vendor specific tests suites
Add a very simple TDR test which submits a single job and verifies that
the TDR handling will run if the backend failed to complete the job in
time.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
.../drm/scheduler/tests/drm_mo
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