Hi Krzysztof,
Thanks very much for your review.
On 2024/12/27 15:38, Krzysztof Kozlowski wrote:
On Tue, Dec 24, 2024 at 05:49:03PM +0800, Kever Yang wrote:
This patch set adds rk3562 SoC and its evb support.
Split out patches belong to different subsystem.
Test with GMAC, USB, PCIe, EMMC
On 09/01/2025 23:39, Dmitry Baryshkov wrote:
> On Thu, Jan 09, 2025 at 02:08:37PM +0100, Krzysztof Kozlowski wrote:
>> Add support for the Qualcomm SM8750 platform.
>>
>> Signed-off-by: Krzysztof Kozlowski
>> ---
>> drivers/gpu/drm/msm/msm_mdss.c | 33 +
>> drivers
Sure, the test does the following:
1. Create a Vulkan buffer using VK_STRUCTURE_TYPE_EXPORT_MEMORY_ALLOCATE_INFO
and VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
2. Get Vulkan buffer FD using vkGetMemoryFdKHR()
3. Import the Vulcan buffer to intel_vpu using DRM_IOCTL_PRIME_FD_TO_HANDLE
4. Call m
Patch 1 reverts a previous fix for loss of HDMI sync when playing YUV420
@ 59.94 media. The patch does resolve a calculation issue. It also makes
all fractional rates invalid which is a bigger problem.
Patch 2 provides a proper fix after I figured out the actual root cause
of the original problem.
Playing YUV420 @ 59.94 media causes HDMI output to lose sync
with a fatal error reported:
[ 89.610280] Fatal Error, invalid HDMI vclk freq 593406
In meson_encoder_hdmi_set_vclk the initial vclk_freq value is
593407 but YUV420 modes halve the value to 296703.5 and this
is stored as int which los
This reverts commit bfbc68e4d8695497f858a45a142665e22a512ea3.
The patch does permit the offending YUV420 @ 59.94 phy_freq and
vclk_freq mode to match in calculations. It also results in all
fractional rates being unavailable for use. This was unintended
and requires the patch to be reverted.
Cc:
On 09/01/2025 11:37, Alexandre Mergnat wrote:
> Enable the DRM HDMI connector support.
> Enable the MIPI-DSI display Startek KD070FHFID015 panel.
Why? It was in previous commit, now its missing.
Best regards,
Krzysztof
[...]
> > Could this be due to amdgpu setting sched->ready when the rings are
> > finished initializing from long ago rather than when the scheduler has
> > been armed?
>
> Yes and that is absolutely intentional.
>
> Either the driver is not done with it's resume yet, or it has already
> started it
Hi,
On 1/9/2025 12:22 PM, Krzysztof Karas wrote:
> Hi Jacek,
>
> On 2025-01-08 at 11:53:46 +0100, Jacek Lawrynowicz wrote:
>> drm_gem_mmap_obj() expects VM_DONTEXPAND flag to be set after mmap
>> callback is executed. Set this flag at the end of i915_gem_dmabuf_mmap()
>> to prevent WARN on mmap i
> -Original Message-
> From: Zeng, Oak
> Sent: Friday, January 10, 2025 4:30 AM
> To: Belgaumkar, Vinay ; Upadhyay, Tejas
> ; intel...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Nilawar, Badal
> ; Mrozek, Michal ;
> Morek, Szymon ; Souza, Jose
> ; De Marchi, Lucas
> Su
> -Original Message-
> From: Belgaumkar, Vinay
> Sent: Friday, January 10, 2025 12:07 AM
> To: Souza, Jose ; intel...@lists.freedesktop.org;
> Upadhyay, Tejas
> Cc: dri-devel@lists.freedesktop.org; Nilawar, Badal
> ; De Marchi, Lucas ;
> Mrozek, Michal ; Morek, Szymon
>
> Subject: Re:
Hi Damon,
kernel test robot noticed the following build warnings:
[auto build test WARNING on rockchip/for-next]
[also build test WARNING on robh/for-next drm/drm-next
drm-exynos/exynos-drm-next linus/master v6.13-rc6 next-20250109]
[cannot apply to drm-intel/for-linux-next drm-intel/for-linux
Hi Dmitry,
> Subject: Re: [PATCH] drm/virtio: Lock the VGA resources during initialization
>
> On 12/11/24 09:43, Vivek Kasireddy wrote:
> > +static int __init virtio_gpu_driver_init(void)
> > +{
> > + struct pci_dev *pdev;
> > + int ret;
> > +
> > + pdev = pci_get_device(PCI_VENDOR_ID_REDH
> -Original Message-
> From: Murthy, Arun R
> Sent: Friday, January 10, 2025 1:16 AM
> To: dri-devel@lists.freedesktop.org; intel-...@lists.freedesktop.org; intel-
> x...@lists.freedesktop.org
> Cc: dmitry.barysh...@linaro.org; Kandpal, Suraj ;
> Shankar, Uma ; "Imported from f20241218-d
From: Ao Xu
The S4-series splits the HIU into `sys_ctrl`, `pwr_ctrl`, and `clk_ctrl`.
Introduce VPU clock settings specific to the Amlogic S4 SoC,
which differ from the configurations used for G12.
Signed-off-by: Ao Xu
---
drivers/gpu/drm/meson/meson_vclk.c | 1018 +
From: Ao Xu
Adjust the parameters passed to specific API calls in the
Meson HDMI encoder to align with hardware requirements.
Configure VCLK to use double pixels for
480p and 576p resolutions in the Amlogic S4.
Signed-off-by: Ao Xu
---
drivers/gpu/drm/meson/meson_encoder_hdmi.c | 19 ++
This patch series adds DRM support for the Amlogic S4-series SoCs.
Compared to the Amlogic G12-series, the S4-series introduces the following
changes:
1 The S4-series splits the HIU into three separate components: `sys_ctrl`,
`pwr_ctrl`, and `clk_ctrl`.
As a result, VENC and VCLK drivers are u
From: Ao Xu
Update VIU and VPP initialization for S4 compatibility.
VPP_MISC register definition was different with G12 SoCs,
so disabled watermark control for S4.
Signed-off-by: Ao Xu
---
drivers/gpu/drm/meson/meson_registers.h | 1 +
drivers/gpu/drm/meson/meson_viu.c | 9 ++---
d
From: Ao Xu
Introduce support for HDMI TX video mode (vmode) timing in the
Meson VENC driver for the Amlogic S4 SoC. These updates enable
reliable HDMI output with correct timing for S4 devices.
Signed-off-by: Ao Xu
---
drivers/gpu/drm/meson/meson_venc.c | 334 +
From: Ao Xu
Add support for Composite Video Baseband Signal (CVBS)
in the Meson encoder driver for the Amlogic S4 SoC.
Signed-off-by: Ao Xu
---
drivers/gpu/drm/meson/meson_encoder_cvbs.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c
From: Ao Xu
Update plane register configurations in the Meson DRM driver
to support the Amlogic S4 SoC. These adjustments ensure proper
handling of display planes with S4-specific hardware requirements.
Signed-off-by: Ao Xu
---
drivers/gpu/drm/meson/meson_crtc.c | 90 +
From: Ao Xu
Add Device Tree support for the DRM subsystem on the Amlogic S4 SoC.
Enable nodes for canvas, vpu, and HDMI controllers.
Enable nodes for CVBS and HDMI bridge connector components.
Signed-off-by: Ao Xu
---
.../boot/dts/amlogic/meson-s4-s805x2-aq222.dts | 39 +++
arch/arm64
From: Ao Xu
Add S4 dw_hdmi register access method.
Adjust clock, power domain, and PHY configurations
to support HDMI on the S4.
Signed-off-by: Ao Xu
---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 244 --
drivers/gpu/drm/meson/meson_dw_hdmi.h | 126
From: Ao Xu
Add devicetree document for S4 HDMI controller
Signed-off-by: Ao Xu
---
Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
b/Documentation/de
From: Ao Xu
Add devicetree document for S4 VPU
Signed-off-by: Ao Xu
---
.../bindings/display/amlogic,meson-vpu.yaml| 48 --
1 file changed, 44 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
b/Documentati
From: Ao Xu
Add S4 compatible for DRM driver. This update driver logic to support
S4-specific configurations. This also add vpu clock operation in
bind, suspend, resume, shutdown stage.
Signed-off-by: Ao Xu
---
drivers/gpu/drm/meson/meson_drv.c | 127 +-
dri
On Thu, Jan 09, 2025 at 10:40:51AM -0400, Jason Gunthorpe wrote:
> On Thu, Jan 09, 2025 at 12:57:58AM +0800, Xu Yilun wrote:
> > On Wed, Jan 08, 2025 at 09:30:26AM -0400, Jason Gunthorpe wrote:
> > > On Tue, Jan 07, 2025 at 10:27:15PM +0800, Xu Yilun wrote:
> > > > Add a flag for ioctl(VFIO_DEVICE_
[Public]
Hi Lyude,
Could you help to merge if patches are ready to go? Thanks!
Regards,
Wayne
> -Original Message-
> From: Wayne Lin
> Sent: Friday, January 10, 2025 10:36 AM
> To: dri-devel@lists.freedesktop.org
> Cc: ly...@redhat.com; Wentland, Harry ;
> imre.d...@intel.com; ville.sy
[Why]
The RAD of sideband message printed today is incorrect.
For RAD stored within MST branch
- If MST branch LCT is 1, it's RAD array is untouched and remained as 0.
- If MST branch LCT is larger than 1, use nibble to store the up facing
port number in cascaded sequence as illustrated below:
Add a helper drm_dp_mst_get_ufp_num_at_lct_from_rad() to extract the up
facing port number at specific link count from the RAD. Use the added
helper in drm_dp_mst_rad_to_str() & drm_dp_get_mst_branch_device() to
unify the implementation.
V2:
- Adjust the code format (Lyude)
Cc: Imre Deak
Cc: Vil
This is v3 of [1], with the following changes:
- Modify description "drm_dp_mst_topology_mgr::mst_primary" to
"&drm_dp_mst_topology_mgr.mst_primary" so kdoc formats it properly (Lyude)
- Ajust code format (Lyude)
Cc: Imre Deak
Cc: Ville Syrjälä
Cc: Harry Wentland
Cc: Lyude Paul
[1] https:
Hi Dave,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on drm-misc/drm-misc-next drm-tip/drm-tip v6.13-rc6
next-20250109]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
e you r-b it,
Okay. Please don't add extra tags in future.
The patch itself is:
Reviewed-by: Dmitry Baryshkov
>
> > Signed-off-by: Hermes Wu
> > ---
> > Changes in v3:
> > - The V value compare loop from i = 0 to i = 4 and shall exit with i == 5
> &g
[Public]
Thanks, Lyude!
Will adjust and send another version later.
Regards,
Wayne
> -Original Message-
> From: Lyude Paul
> Sent: Friday, January 10, 2025 6:45 AM
> To: Lin, Wayne ; dri-devel@lists.freedesktop.org
> Cc: imre.d...@intel.com; ville.syrj...@linux.intel.com; Wentland, Harr
On Thu, Jan 09, 2025 at 05:50:16PM -0800, Jessica Zhang wrote:
>
>
> On 1/9/2025 5:42 PM, Dmitry Baryshkov wrote:
> > On Fri, 10 Jan 2025 at 02:30, Jessica Zhang
> > wrote:
> > >
> > >
> > >
> > > On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
> > > > On Thu, Jan 09, 2025 at 02:34:44PM -0800,
On Thu, Jan 09, 2025 at 05:40:23PM -0800, Abhinav Kumar wrote:
>
>
> On 1/5/2025 7:07 PM, Dmitry Baryshkov wrote:
> > The fix_core_ab_vote is an average bandwidth value, used for bandwidth
> > overrides in several cases. However there is an internal inconsistency:
> > fix_core_ib_vote is defined
dvice to a path.
So I add it before you r-b it,
> Signed-off-by: Hermes Wu
> ---
> Changes in v3:
> - The V value compare loop from i = 0 to i = 4 and shall exit with i == 5
> if all V element matches
> - Link to v2:
> https://lore.kernel.org/r/20250109-fix-hdcp-v
On Fri, 10 Jan 2025 at 02:30, Jessica Zhang wrote:
>
>
>
> On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
> > On Thu, Jan 09, 2025 at 02:34:44PM -0800, Jessica Zhang wrote:
> >>
> >>
> >> On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
> >>> On Fri, Jan 03, 2025 at 10:03:35AM -0800, Jessica Zhang wrot
On 1/9/2025 5:42 PM, Dmitry Baryshkov wrote:
On Fri, 10 Jan 2025 at 02:30, Jessica Zhang wrote:
On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
On Thu, Jan 09, 2025 at 02:34:44PM -0800, Jessica Zhang wrote:
On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
On Fri, Jan 03, 2025 at 10:03:35AM
Hi Thomas,
At 2025-01-09 22:56:56, "Thomas Zimmermann" wrote:
>Add drm_modes_size_dumb(), a helper to calculate the dumb-buffer
>scanline pitch and allocation size. Implementations of struct
>drm_driver.dumb_create can call the new helper for their size
>computations. There's currently quite a b
On 1/5/2025 7:07 PM, Dmitry Baryshkov wrote:
The fix_core_ab_vote is an average bandwidth value, used for bandwidth
overrides in several cases. However there is an internal inconsistency:
fix_core_ib_vote is defined in KBps, while fix_core_ab_vote is defined
in Bps.
Fix that by changing the t
On 1/5/2025 7:07 PM, Dmitry Baryshkov wrote:
The IB values in core_perf calculations (max_per_pipe_ib,
fix_core_ib_vote) are expressed in KBps and are passed to icc_set_bw
without additional division. Change type of those values to u32.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/m
On 1/5/2025 7:07 PM, Dmitry Baryshkov wrote:
The code in dpu_core_perf_crtc_check() mostly duplicates code in
dpu_core_perf_aggregate(). Remove the duplication by reusing the latter
function.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 94 +++
On 1/9/2025 4:00 PM, Dmitry Baryshkov wrote:
On Thu, Jan 09, 2025 at 02:34:44PM -0800, Jessica Zhang wrote:
On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
On Fri, Jan 03, 2025 at 10:03:35AM -0800, Jessica Zhang wrote:
On 12/19/2024 9:03 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 a
On Thu, Jan 09, 2025 at 02:53:40PM -0800, Jessica Zhang wrote:
>
>
> On 1/9/2025 2:13 PM, Dmitry Baryshkov wrote:
> > On Thu, 9 Jan 2025 at 23:26, Jessica Zhang
> > wrote:
> > >
> > >
> > >
> > > On 12/28/2024 8:47 PM, Dmitry Baryshkov wrote:
> > > > On Thu, Dec 26, 2024 at 02:49:28PM -0800,
On Thu, Jan 09, 2025 at 02:34:44PM -0800, Jessica Zhang wrote:
>
>
> On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
> > On Fri, Jan 03, 2025 at 10:03:35AM -0800, Jessica Zhang wrote:
> > >
> > >
> > > On 12/19/2024 9:03 PM, Dmitry Baryshkov wrote:
> > > > On Mon, Dec 16, 2024 at 04:43:26PM -0800
On Thu, Jan 09, 2025 at 02:53:16PM +0100, Thomas Zimmermann wrote:
> Hi
>
>
> Am 22.12.24 um 06:00 schrieb Dmitry Baryshkov:
> > As pointed out by Simona, the drm_atomic_helper_check_modeset() and
> > drm_atomic_helper_check() require the former function is rerun if the
> > driver's callbacks mod
On Tue, 17 Dec 2024 14:17:07 -0600, Derek Foreman wrote:
> The code that changes hdmi->ref_clk was accidentally copied from
> downstream code that sets a different clock. We don't actually
> want to set any clock here at all.
>
> Setting this clock incorrectly leads to incorrect timings for
> DD
On Thu, Jan 09, 2025 at 02:08:35PM +0100, Krzysztof Kozlowski wrote:
> Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with two
> differences worth noting:
>
> 1. ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their
>offsets were just switched. Currently these r
From: Rob Clark
If userspace is trying to achieve a timeout of zero, let 'em have it.
Only round up if the timeout is greater than zero.
Fixes: 4969bccd5f4e ("drm/msm: Avoid rounding down to zero jiffies")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.h | 10 --
1 file chang
On Thu, Jan 09, 2025 at 02:08:38PM +0100, Krzysztof Kozlowski wrote:
> Not finished. Looking around, maybe someone already did some works
> around new CTL_PIPE_ACTIVE and CTL_LAYER_ACTIVE registers?
This is not enough, the whole blend setup is to be moved to LM
block.
>
> Signed-off-by: Krzyszto
> -Original Message-
> From: Belgaumkar, Vinay
> Sent: January 9, 2025 5:03 PM
> To: Zeng, Oak ; Upadhyay, Tejas
> ; intel...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Nilawar, Badal
> ; Mrozek, Michal
> ; Morek, Szymon
> ; Souza, Jose ;
> De Marchi, Lucas
> Subject:
Am Donnerstag, 9. Januar 2025, 15:57:13 CET schrieb Thomas Zimmermann:
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
> buffer size. Align the pitch to a multiple of 64.
>
> Signed-off-by: Thomas Zimmermann
> Cc: Sandy Huang
> Cc: "Heiko Stübner"
> Cc: Andy Yan
I've loo
On 1/9/2025 2:13 PM, Dmitry Baryshkov wrote:
On Thu, 9 Jan 2025 at 23:26, Jessica Zhang wrote:
On 12/28/2024 8:47 PM, Dmitry Baryshkov wrote:
On Thu, Dec 26, 2024 at 02:49:28PM -0800, Jessica Zhang wrote:
On 12/20/2024 5:07 PM, Dmitry Baryshkov wrote:
On Fri, Dec 20, 2024 at 04:12:29
Patch looks good to me, just one small change:
On Mon, 2024-12-23 at 12:07 +0800, Wayne Lin wrote:
> - for (i = 0; i < lct - 1; i++) {
> - int shift = (i % 2) ? 0 : 4;
> - int port_num = (rad[i / 2] >> shift) & 0xf;
> + for (i = 1; i < lct; i++) {
> + in
Hey there! Patch looks good to me, just one small change:
On Mon, 2024-12-23 at 12:07 +0800, Wayne Lin wrote:
> + /**
> + * @rad: Relative Address of the MST branch.
> + * For drm_dp_mst_topology_mgr::mst_primary, it's rad[8] are all 0,
> + * unset and unused. For MST branches c
On Thu, Jan 09, 2025 at 02:08:37PM +0100, Krzysztof Kozlowski wrote:
> Add support for the Qualcomm SM8750 platform.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 33 +
> drivers/gpu/drm/msm/msm_mdss.h | 1 +
> 2 files changed, 3
On 1/3/2025 10:16 AM, Dmitry Baryshkov wrote:
On Fri, Jan 03, 2025 at 10:03:35AM -0800, Jessica Zhang wrote:
On 12/19/2024 9:03 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 2024 at 04:43:26PM -0800, Jessica Zhang wrote:
Add the cwb_enabled flag to msm_display topology and adjust the toplog
We have a few reports of sc7180-trogdor-pompom devices that have a
panel in them that IDs as STA 0x0004 and has the following raw EDID:
00 ff ff ff ff ff ff 00 4e 81 04 00 00 00 00 00
10 20 01 04 a5 1a 0e 78 0a dc dd 96 5b 5b 91 28
1f 52 54 00 00 00 01 01 01 01 01 01 01 01 01 01
01 01 0
On Thu, Jan 09, 2025 at 02:08:36PM +0100, Krzysztof Kozlowski wrote:
> Add DPU version v12.0 support for the Qualcomm SM8750 platform.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h| 522
> +
> drivers/gpu/drm/msm/disp/dpu1
On Thu, 9 Jan 2025 at 23:26, Jessica Zhang wrote:
>
>
>
> On 12/28/2024 8:47 PM, Dmitry Baryshkov wrote:
> > On Thu, Dec 26, 2024 at 02:49:28PM -0800, Jessica Zhang wrote:
> >>
> >>
> >> On 12/20/2024 5:07 PM, Dmitry Baryshkov wrote:
> >>> On Fri, Dec 20, 2024 at 04:12:29PM -0800, Jessica Zhang wr
ev->host_visible_lock);
if (ret)
---
base-commit: 643e2e259c2b25a2af0ae4c23c6e16586d9fd19c
change-id: 20250109-virtgpu-mixed-page-size-282b8f4a02fc
On 1/9/2025 9:37 AM, Zeng, Oak wrote:
-Original Message-
From: dri-devel On
Behalf Of Tejas Upadhyay
Sent: January 9, 2025 7:07 AM
To: intel...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org; Nilawar, Badal
; Belgaumkar, Vinay
; Mrozek, Michal
; Morek, Szymon
; Souza, Jose
vm_size, vma->vm_page_prot);
return ret;
}
---
base-commit: 643e2e259c2b25a2af0ae4c23c6e16586d9fd19c
change-id: 20250109-virtgpu-gem-partial-map-335ec40656d1
On 12/28/2024 8:47 PM, Dmitry Baryshkov wrote:
On Thu, Dec 26, 2024 at 02:49:28PM -0800, Jessica Zhang wrote:
On 12/20/2024 5:07 PM, Dmitry Baryshkov wrote:
On Fri, Dec 20, 2024 at 04:12:29PM -0800, Jessica Zhang wrote:
On 12/19/2024 9:52 PM, Dmitry Baryshkov wrote:
On Mon, Dec 16, 202
On Mon, Jan 06, 2025 at 04:30:20PM +0900, Zhenyu Wang wrote:
> On Sun, Dec 22, 2024 at 12:25:09AM +, Dr. David Alan Gilbert wrote:
> > Note: zhen...@linux.intel.com's address bounces:
> >
>
> yeah, I've left Intel so can't use that box any more, looks Rodrigo hasn't
> queue up my address chan
On Thu, Jan 9, 2025 at 3:29 PM Borislav Petkov wrote:
>
> Hi folks,
>
> this is rc6 + tip/master, machine is Carrizo laptop.
Possibly fixed by this patch?
https://lore.kernel.org/lkml/CAJZ5v0i=ap+w4QZ8f2DsaHY6D=XUEuSNjyQ-2_=dgolfzjd...@mail.gmail.com/T/
Alex
>
> full dmesg attached.
>
> Thx.
>
EDITME: Imported from f20241218-dpst-v7-0-81bfe7d08...@intel.com
Please review before sending.
Display histogram is a hardware functionality where a statistics for 'n'
number of frames is generated to form a histogram data. This is notified
to the user via histogram event. Compositor will
Hi folks,
this is rc6 + tip/master, machine is Carrizo laptop.
full dmesg attached.
Thx.
...
[ 13.271015] [drm] DM_PPLIB:level : 8
[ 13.271658] [drm] Display Core v3.2.310 initialized on DCE 11.0
[ 13.351651] kmemleak: Found object by alias at 0x888107b65918
[ 13.35236
Enable pipe dithering while enabling histogram to overcome some
atrifacts seen on the screen.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_histogram.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c
b/drivers
In Display 20+, new registers are added for setting index, reading
histogram and writing the IET.
v2: Removed duplicate code (Jani)
v3: Moved histogram core changes to earlier patches (Jani/Suraj)
v4: Rebased after addressing comments on patch 1
v5: Added the retry logic from patch3 and rebased th
The delay counter for histogram does not reset and as a result the
histogram bin never gets updated. Workaround would be to use save and
restore histogram register.
v2: Follow the seq in interrupt handler
Restore DPST bit 0
read/write dpst ctl rg
Restore DPST bit 1 and Guar
Upon drm getting the IET LUT value from the user through the IET_LUT
property, i915 driver will write the LUT table to the hardware
registers.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_crtc.c| 3 +++
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
2 files chang
Handle histogram caps and histogram config property in i915 driver. Fill
the histogram hardware capability and act upon the histogram config
property to enable/disable histogram in i915.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_crtc.c| 7 +++
drivers/gpu/drm/i
User created LUT can be fed back to the hardware so that the hardware
can apply this LUT data to see the enhancement in the image.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_histogram.c | 70 ++
drivers/gpu/drm/i915/display/intel_histogram.h | 4
Upon enabling histogram an interrupt is trigerred after the generation
of the statistics. This patch registers the histogram interrupt and
handles the interrupt.
v2: Added intel_crtc backpointer to intel_histogram struct (Jani)
Removed histogram_wq and instead use dev_priv->unodered_eq (Jani)
Histogram added as part of i915/display driver. Adding the same for xe
as well.
Signed-off-by: Arun R Murthy
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/xe/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index
5c97ad6ed7
Statistics is generated from the image frame that is coming to display
and an event is sent to user after reading this histogram data.
v2: forward declaration in header file along with error handling (Jani)
v3: Replaced i915 with intel_display (Suraj)
v4: Removed dithering enable/disable (Vandita)
Display Histogram is an array of bins and can be generated in many ways
referred to as modes.
Ex: HSV max(RGB), Wighted RGB etc.
Understanding the histogram data format(Ex: HSV max(RGB))
Histogram is just the pixel count.
For a maximum resolution of 10k (10240 x 4320 = 44236800)
25 bits should be
Add drm-crtc property for IET 1DLUT and for the properties added add
corresponding get/set_property.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/drm_atomic_state_helper.c | 9 ++
drivers/gpu/drm/drm_atomic_uapi.c | 13
drivers/gpu/drm/drm_crtc.c| 54 +++
Add the register/bit definitions for global histogram.
v2: Intended the register contents, removed unused regs (Jani)
Bspec: 4270
Signed-off-by: Arun R Murthy
Reviewed-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_histogram_regs.h| 48 ++
1 file changed, 48 inser
Add drm-crtc property for histogram and for the properties added add
the corresponding get/set_property.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/drm_atomic_state_helper.c | 14 ++
drivers/gpu/drm/drm_atomic_uapi.c | 15 +++
drivers/gpu/drm/drm_crtc.c| 73
ImageEnhancemenT(IET) hardware interpolates the LUT value to generate
the enhanced output image. LUT takes an input value, outputs a new
value based on the data within the LUT. 1D LUT can remap individual
input values to new output values based on the LUT sample. LUT can be
interpolated by the hard
On Wed, Jan 08, 2025 at 06:55:16PM +, Tvrtko Ursulin wrote:
>
> On 08/01/2025 16:57, Danilo Krummrich wrote:
> > On Wed, Jan 08, 2025 at 03:13:39PM +, Tvrtko Ursulin wrote:
> > >
> > > On 08/01/2025 08:31, Danilo Krummrich wrote:
> > > > On Mon, Dec 30, 2024 at 04:52:45PM +, Tvrtko Ur
On 1/9/2025 13:48, Lizhi Hou wrote:
Due to miss returning error when setting clock, the smatch static
checker reports warning:
drivers/accel/amdxdna/aie2_smu.c:68 npu1_set_dpm()
error: uninitialized symbol 'freq'.
Fixes: f4d7b8a6bc8c ("accel/amdxdna: Enhance power management settings")
Rep
On Wed, Jan 08, 2025 at 05:57:25PM +0100, Danilo Krummrich wrote:
> On Wed, Jan 08, 2025 at 03:13:39PM +, Tvrtko Ursulin wrote:
Hi, all.
Just catching up on this post holidays. A few thoughts below.
> >
> > On 08/01/2025 08:31, Danilo Krummrich wrote:
> > > On Mon, Dec 30, 2024 at 04:52:45P
Due to miss returning error when setting clock, the smatch static
checker reports warning:
drivers/accel/amdxdna/aie2_smu.c:68 npu1_set_dpm()
error: uninitialized symbol 'freq'.
Fixes: f4d7b8a6bc8c ("accel/amdxdna: Enhance power management settings")
Reported-by: Dan Carpenter
Closes:
https:
On 1/8/2025 17:41, Lizhi Hou wrote:
Due to miss returning error when setting clock, the smatch static
checker reports warning:
drivers/accel/amdxdna/aie2_smu.c:68 npu1_set_dpm()
error: uninitialized symbol 'freq'.
Fixes: f4d7b8a6bc8c ("accel/amdxdna: Enhance power management settings")
Rep
Hi Dave, Simona
Two fixes this week.
Thanks,
Thomas
drm-xe-fixes-2025-01-09:
Driver Changes:
- Avoid a NULL ptr deref when wedging (Lucas)
- Fix power gate sequence on DG1 (Rodrigo)
The following changes since commit f0ed39830e6064d62f9c5393505677a26569bb56:
xe/oa: Fix query mode of operation
On 1/9/2025 6:36 AM, Souza, Jose wrote:
On Thu, 2025-01-09 at 17:37 +0530, Tejas Upadhyay wrote:
Allow user to provide a low latency hint per exec queue. When set,
KMD sends a hint to GuC which results in special handling for this
exec queue. SLPC will ramp the GT frequency aggressively every
On Wed, Jan 8, 2025 at 10:14 PM Ian Forbes wrote:
>
> Unused since commit a78a8da51b36
> ("drm/ttm: replace busy placement with flags v6")
>
> Signed-off-by: Ian Forbes
> ---
> drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 1 -
> drivers/gpu/drm/vmwgfx/vmwgfx_bo.h | 1 -
> 2 files changed, 2 deletions(-)
On 12/18/2024 11:49 PM, Jun Nie wrote:
There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd
interface to 3rd PP instead of the 2nd PP.
Signed-off-by: Jun Nie
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 +
On Thu, Jan 9, 2025 at 5:16 AM Joel Granados wrote:
>
[...]
> drivers/base/firmware_loader/fallback_table.c | 2 +-
> drivers/cdrom/cdrom.c | 2 +-
> drivers/char/hpet.c | 2 +-
> drivers/char/ipmi/ipmi_poweroff.c | 2 +-
> drivers/cha
> -Original Message-
> From: dri-devel On
> Behalf Of Tejas Upadhyay
> Sent: January 9, 2025 7:07 AM
> To: intel...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Nilawar, Badal
> ; Belgaumkar, Vinay
> ; Mrozek, Michal
> ; Morek, Szymon
> ; Souza, Jose ;
> De Marchi, Lucas
On 09.01.2025 13:05, Tvrtko Ursulin wrote:
> On 08/01/2025 21:02, Adrián Larumbe wrote:
> > This is motivated by the desire of some dirvers (eg. Panthor) to print the
> > size of internal memory regions with a prefix that reflects the driver
> > name, as suggested in the previous documentation comm
On Thu, Jan 09, 2025 at 11:52:56PM +0800, Nick Chan wrote:
>
> Daniel Thompson 於 2025/1/8 下晝6:52 寫道:
> > On Wed, Dec 11, 2024 at 07:34:38PM +0800, Nick Chan wrote:
> >> Add driver for backlight controllers attached via Apple DWI 2-wire
> >> interface, which is found on some Apple iPhones, iPads and
On 09/01/2025 16:26, Thomas Zimmermann wrote:
Hi
Am 09.01.25 um 17:05 schrieb Matthew Auld:
On 09/01/2025 14:57, Thomas Zimmermann wrote:
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. Align the pitch to a multiple of 8. Align the
buffer size according to har
On Thu, Jan 09, 2025 at 10:55:53AM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> This is the 3rd iteration of this after talking to Ben and
> Danilo, I think this makes sense now.
>
> The fence sync logic doesn't handle a fence sync across devices
> as it tries to write to a channel offset f
On 09/01/2025 15:47, Christian König wrote:
And pushed to drm-misc-next.
Sorry I'm still catching up from the holidays,
Thank you! I afforded myself an extra ping with all this talk about
unreliable/corrupt email.
Regards,
Tvrtko
Am 09.01.25 um 11:53 schrieb Tvrtko Ursulin:
Christian
On 09/01/2025 15:08, Michel Dänzer wrote:
On 2025-01-03 13:31, Christian König wrote:
Am 03.01.25 um 13:02 schrieb Tvrtko Ursulin:
One big question is whether round-robin can really be removed. Does
anyone use
it, rely on it, or what are even use cases where it is much better
than FIFO.
So
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