On Tue, Dec 10, 2024 at 07:57:05AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam
>
> The imx8mm-phg board has an AUO G084SN05 V9 8.4" 800x600 LVDS panel.
>
> Improve the devicetree description by passing the LVDS compatible
> string to fix the following dt-schema warning:
>
> imx8mm-phg.dtb
On 12/24/2024, Marek Vasut wrote:
> Commit a25b988ff83f ("drm/bridge: Extend bridge API to disable connector
> creation")
> added DRM_BRIDGE_ATTACH_NO_CONNECTOR bridge flag and all bridges handle
> this flag in some way since then.
> Newly added bridge drivers must no longer contain the connector
On 12/24/2024, Marek Vasut wrote:
> Commit a25b988ff83f ("drm/bridge: Extend bridge API to disable connector
> creation")
> added DRM_BRIDGE_ATTACH_NO_CONNECTOR bridge flag and all bridges handle
> this flag in some way since then.
> Newly added bridge drivers must no longer contain the connector
On 12/26/2024, Marek Vasut wrote:
> On 12/24/24 5:21 AM, Dmitry Baryshkov wrote:
> > On Tue, Dec 24, 2024 at 02:46:14AM +0100, Marek Vasut wrote:
> >> The dw-hdmi output_port is set to 1 in order to look for a connector
> >> next bridge in order to get DRM_BRIDGE_ATTACH_NO_CONNECTOR
> working.
> >>
On 12/24/2024, Marek Vasut wrote:
> The dw-hdmi output_port is set to 1 in order to look for a connector
> next bridge in order to get DRM_BRIDGE_ATTACH_NO_CONNECTOR working.
> The output_port set to 1 makes the DW HDMI driver core look up the
> next bridge in DT, where the next bridge is often the
On 2024/12/18 19:44, Dmitry Baryshkov wrote:
On Wed, Dec 18, 2024 at 11:18:01AM +0800, fange zhang wrote:
On 2024/12/13 18:19, Dmitry Baryshkov wrote:
On Fri, 13 Dec 2024 at 11:21, fange zhang wrote:
On 2024/12/10 19:02, Dmitry Baryshkov wrote:
On Tue, Dec 10, 2024 at 02:54:00PM +080
On 2024/12/26 13:18, Bjorn Andersson wrote:
On Tue, Dec 10, 2024 at 02:53:51PM +0800, Fange Zhang wrote:
This series aims to enable display on the QCS615 platform
1.Add MDSS & DPU support for QCS615
2.Add DSI support for QCS615
QCS615 platform supports DisplayPort, and this feature will be
assigned-clock* properties can be used by default now, so allow them.
Signed-off-by: Liu Ying
---
v8:
* No change.
v7:
* No change.
v6:
* No change.
v5:
* No change.
v4:
* No change.
v3:
* No change.
v2:
* New patch as needed by MIPI/LVDS subsystems device tree.
.../devicetree/bindings/ph
Document SCU controlled display pixel link child nodes.
Signed-off-by: Liu Ying
---
v8:
* No change.
v7:
* No change.
v6:
* No change.
v5:
* No change.
v4:
* No change.
v3:
* No change.
v2:
* New patch as needed by display controller subsystem device tree.
.../devicetree/bindings/firmware
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v8:
* Drop instance numbers
i.MX8qxp Display Controller pixel engine consists of all processing
units that operate in the AXI bus clock domain. Add drivers for
ConstFrame, ExtDst, FetchLayer, FetchWarp and LayerBlend units, as
well as a pixel engine driver, so that two displays with primary
planes can be supported. The pixe
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer. Add kernel
mode setting support for the display controller part with two CRTCs and
two p
i.MX8qxp Display Controller contains a blit engine for raster graphics.
It may read up to 3 source images from memory and computes one destination
image from it, which is written back to memory.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v8:
* Drop instance numbers from compatibl
Freescale i.MX8qxp Display Controller is implemented as construction set of
building blocks with unified concept and standardized interfaces. Document
all existing processing units.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v8:
* Drop instance numbers from compatible strings. T
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v8:
* No change.
v7:
* No change.
v6:
* No change.
v5:
* No change.
v4:
* No change.
v3:
* Collect Rob's R-b tag.
MX8-DLVDS-LCD1 display module integrates a KOE TX26D202VM0BWA LCD panel
and a touch IC. Add an overlay to support the LCD panel on i.MX8qxp
MEK. mipi_lvds_0_ldb channel0 and mipi_lvds_1_ldb channel1 send odd
and even pixels to the panel respectively.
Signed-off-by: Liu Ying
---
v8:
* No change.
Enable display controller for i.MX8qxp MEK.
Signed-off-by: Liu Ying
---
v8:
* No change.
v7:
* No change.
v6:
* No change.
v5:
* No change.
v4:
* No change.
v3:
* No change.
v2:
* New patch. (Francesco)
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4
1 file changed, 4 insertions(+
The MIPI-LVDS combo subsystems are peripherals of pixel link MSI
bus in i.MX8qxp display controller subsystem. Add the MIPI-LVDS
combo subsystems.
Signed-off-by: Liu Ying
---
v8:
* No change.
v7:
* No change.
v6:
* No change.
v5:
* No change.
v4:
* No change.
v3:
* No change.
v2:
* New pat
Add display controller subsystem in i.MX8qxp SoC.
Signed-off-by: Liu Ying
---
v8:
* Drop instance numbers from display controller internal devices' compatible
strings. (Dmitry)
v7:
* Add instance numbers to display controller internal devices' compatible
strings.
* Drop aliases.
v6:
* No ch
Add myself as the maintainer of i.MX8qxp Display Controller.
Signed-off-by: Liu Ying
---
v8:
* No change.
v7:
* No change.
v6:
* No change.
v5:
* No change.
v4:
* No change.
v3:
* No change.
v2:
* Improve file list. (Frank)
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff -
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit. Add driver for it.
Reviewed-by: Maxime Ripard
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Liu Ying
---
v8:
* Collect Dmitry's R-b tag.
v7:
* Fix regmap_config definition by re
i.MX8qxp Display Controller display engine consists of all processing
units that operate in a display clock domain. Add minimal feature
support with FrameGen and TCon so that the engine can output display
timings. The FrameGen driver, TCon driver and display engine driver
are components to be agg
i.MX8qxp Display Controller contains a command sequencer is designed to
autonomously process command lists.
Signed-off-by: Liu Ying
---
v8:
* No change.
v7:
* No change.
v6:
* No change.
v5:
* No change.
v4:
* Replace "fsl,iram" property with standard "sram" property. (Rob)
v3:
* New patch.
i.MX8qxp Display Controller contains a AXI performance counter which allows
measurement of average bandwidth and latency during operation.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v8:
* No change.
v7:
* No change.
v6:
* No change.
v5:
* No change.
v4:
* Collect Rob's R-b ta
i.MX8qxp Display Controller display engine consists of all processing units
that operate in a display clock domain.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v8:
* Drop instance numbers from compatible strings. This means switching back to
the patch in v4. So, add Rob's previo
i.MX8qxp Display Controller pixel engine consists of all processing units
that operate in the AXI bus clock domain. Command sequencer and interrupt
controller of the Display Controller work with AXI bus clock, but they are
not in pixel engine.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Ar
Hi,
This patch series aims to add Freescale i.MX8qxp Display Controller support.
The controller is comprised of three main components that include a blit
engine for 2D graphics accelerations, display controller for display output
processing, as well as a command sequencer.
Previous patch series
On 12/27/2024, Dmitry Baryshkov wrote:
> On Wed, 25 Dec 2024 at 09:18, Liu Ying wrote:
>>
>> On 12/23/2024, Dmitry Baryshkov wrote:
>>> On Mon, Dec 23, 2024 at 02:41:40PM +0800, Liu Ying wrote:
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engi
Am 28.12.24 um 07:32 schrieb Shuai Xue:
It's observed that most GPU jobs utilize less than one server, typically
with each GPU being used by an independent job. If a job consumed poisoned
data, a SIGBUS signal will be sent to terminate it. Meanwhile, the
gpu_recovery parameter is set to -1 by def
>
> Hello Alexander,
>
> >> If so, I have to add patch for mtd subsystem to always have device for
> master
> >> initialized regardless of kernel flag.
> >> Only to initialize struct device, not to create full mtd node.
> >>
> >> Miquel - are you agree to this?
>
> Conceptually yes, but please m
Hi Andy,
Am Sonntag, 29. Dezember 2024, 07:48:36 CET schrieb Andy Yan:
>
> Hi Heiko,
>
> At 2024-12-29 02:36:36, "Heiko Stübner" wrote:
> >Hi Andy,
> >
> >Am Samstag, 28. Dezember 2024, 13:21:43 CET schrieb Andy Yan:
> >> From: Andy Yan
> >>
> >>
> >> As the VOP[0] and HDMI[1] driver have al
On 2024-12-18 16:35:21, Darrick J. Wong wrote:
> On Tue, Dec 17, 2024 at 11:58:12PM +0100, Mirsad Todorovac wrote:
> > The source static analysis tool gave the following advice:
> >
> > ./fs/xfs/libxfs/xfs_dir2.c:382:15-22: WARNING opportunity for kmemdup
> >
> > → 382 args->value = kmal
Add MAINTAINERS entries for the driver.
Signed-off-by: Nick Chan
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 910305c11e8a..54a6c8ca7017 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2196,6 +2196,7 @@ F:
Documentation/devicetree/b
Add driver for backlight controllers attached via Apple DWI 2-wire
interface, which is found on some Apple iPhones, iPads and iPod touches
with a LCD display.
Although there is an existing apple_bl driver, it is for backlight
controllers on Intel Macs attached via PCI, which is completely differen
Apple SoCs come with a 2-wire interface named DWI. On some iPhones, iPads
and iPod touches the backlight controller is connected via this interface.
This series adds a backlight driver for backlight controllers connected
this way.
Changes since v3:
- $ref to common.yaml in bindings
- (and then add
Add backlight controllers attached via Apple DWI 2-wire interface.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Nick Chan
---
.../bindings/leds/backlight/apple,dwi-bl.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/leds/b
Hi Krzysztof,
At 2024-12-29 18:13:39, "Krzysztof Kozlowski" wrote:
>On Sat, Dec 28, 2024 at 08:21:48PM +0800, Andy Yan wrote:
>> From: Andy Yan
>>
>> Add vop found on rk3576, the main difference between rk3576 and the
>> previous vop is that each VP has its own interrupt line.
>>
>> Signed-o
On Sat, Dec 28, 2024 at 08:21:48PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> Add vop found on rk3576, the main difference between rk3576 and the
> previous vop is that each VP has its own interrupt line.
>
> Signed-off-by: Andy Yan
>
> ---
>
> Changes in v2:
> - describe constraint SOC by S
Hey all,
For one of our new boards I have to get the ADV7513 chip working with TIDSS,
the driver for this expects a bridge chip to have atomic ops and provide bus
formats.
Doing this for our own needs was quite straightforward but I'd very much like
to upstream this as I think it could be helpf
On Wed, 11 Dec 2024 at 04:37, Cristian Ciocaltea
wrote:
>
> Add support for the second HDMI TX port found on RK3588 SoC.
>
> Signed-off-by: Cristian Ciocaltea
> ---
Tested-by: Jagan Teki # edgeble-6tops-modules
On Wed, 11 Dec 2024 at 04:37, Cristian Ciocaltea
wrote:
>
> In preparation to enable the second HDMI output port found on RK3588
> SoC, add the related PHY node. This requires a GRF, hence add the
> dependent node as well.
>
> Signed-off-by: Cristian Ciocaltea
> ---
Tested-by: Jagan Teki # edg
It's observed that most GPU jobs utilize less than one server, typically
with each GPU being used by an independent job. If a job consumed poisoned
data, a SIGBUS signal will be sent to terminate it. Meanwhile, the
gpu_recovery parameter is set to -1 by default, the amdgpu driver resets
all GPUs on
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