On Fri, Dec 13, 2024 at 10:29 PM Vasily Khoruzhick wrote:
>
> On Thu, May 4, 2023 at 10:34 PM Roman Beranek wrote:
> >
> > TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X),
> > however MIPI DSI output only seems to work when PLL_MIPI is selected and
> > thus the choice must
From: Andy Yan
The company name has update to Rockchip Electronics Co., Ltd.
since 2021.
And change Co.Ltd to Co., Ltd. to fix mail server warning:
DBL_SPAM(6.50)[co.ltd:url];
Signed-off-by: Andy Yan
Reviewed-by: Sebastian Reichel
---
Changes in v2:
- Fix an omitted file cdn-dp-core.h
driv
On Thu, May 4, 2023 at 10:34 PM Roman Beranek wrote:
>
> TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X),
> however MIPI DSI output only seems to work when PLL_MIPI is selected and
> thus the choice must be hardcoded in.
>
> Currently, this driver can't propagate rate chang
On Fri, Dec 13, 2024 at 02:16:51PM -0800, Matthew Brost wrote:
> On Fri, Nov 29, 2024 at 10:31:32AM +1100, Alistair Popple wrote:
> >
> > Matthew Brost writes:
> >
> > > Avoid multiple CPU page faults to the same device page racing by trying
> > > to lock the page in do_swap_page before taking a
The pull request you sent on Sat, 14 Dec 2024 07:23:44 +1000:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-fixes-2024-12-14
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/e72da82d5a6deec67a680434e1f19ba3996fbb11
Thank you!
--
Deet-doot-dot, I am a bot.
h
On Fri, Nov 29, 2024 at 11:00:24AM +1100, Alistair Popple wrote:
>
> Matthew Brost writes:
>
> [...]
>
> > + * 3) Invalidation driver vfunc.
> > + *
> > + * void driver_invalidation(struct drm_gpusvm *gpusvm,
> > + * struct drm_gpusvm_notifier *notifier,
> > + *
On Tue, 2024-12-03 at 06:34 -0500, Genes Lists wrote:
> On Tue, 2024-12-03 at 11:16 +0200, Ville Syrjälä wrote:
> > > ...
>
> > Probably https://gitlab.freedesktop.org/drm/i915/kernel/-
> > /issues/13057
> >
> Very helpful.
>
> I tested your patch set on Linus' tree commit
> cdd30ebb1b9f36159d66
On 12/13/24 13:33, Jeffrey Hugo wrote:
Add basic support for the new AIC200 product. The PCIe Device ID is
0xa110. With this, we can turn on the lights for AIC200 by leveraging
much of the existing driver.
Co-developed-by: Youssef Samir
Signed-off-by: Youssef Samir
Signed-off-by: Jeffrey Hug
On 12/13/24 13:33, Jeffrey Hugo wrote:
From: Youssef Samir
During the initialization of the qaic device, pci_select_bars() is
used to fetch a bitmask of the BARs exposed by the device. On devices
that have Virtual Functions capabilities, the bitmask includes SR-IOV
BARs.
Use a mask to filter
On 12/13/24 13:33, Jeffrey Hugo wrote:
As the number of cards supported by the driver grows, their
configurations will differ. The driver needs to become more dynamic
to support these configurations. Currently, each card may differ in
the exposed BARs, the regions they map to, and the family.
On 12/13/24 13:33, Jeffrey Hugo wrote:
From: Youssef Samir
AIC200 device will support MSI-X while AIC100 devices will keep using
MSI. pci_alloc_irq_vectors() will try to allocate MSI-X vectors if it
is supported by the target device, otherwise, it will fallback to MSI.
Add support for MSI-X
On 13.12.2024 5:55 PM, Akhil P Oommen wrote:
> On 12/13/2024 10:10 PM, neil.armstr...@linaro.org wrote:
>> On 13/12/2024 17:31, Konrad Dybcio wrote:
>>> On 13.12.2024 5:28 PM, neil.armstr...@linaro.org wrote:
On 13/12/2024 16:37, Konrad Dybcio wrote:
> On 13.12.2024 2:12 PM, Akhil P Oommen
On 12/13/24 13:33, Jeffrey Hugo wrote:
From: Youssef Samir
Devices use 1 MSI vector for the MHI controller and as many vectors as
the DMA bridge channels on the device. During the probing of the
device, the driver allocates 32 MSI vectors, which is usually more
than what is needed for AIC100
The latest released firmware supports reading firmware interface version
from registers directly. The driver's probe routine reads the major and
minor version numbers. If the firmware interface is not compatible with
the driver, the driver's probe routine returns failure.
Co-developed-by: Min Ma
Add SET_STATE ioctl to configure device power mode for aie2 device.
Three modes are supported initially.
POWER_MODE_DEFAULT: Enable clock gating and set DPM (Dynamic Power
Management) level to value which has been set by resource solver or
maximum DPM level the device supports.
POWER_MODE_HIGH: E
Switch mailbox message id and hardware context id management over from
the idr api to the xarray api.
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/TODO | 1 -
drivers/accel/amdxdna/aie2_ctx.c| 5 ++-
drivers/accel/amdxdna/aie2_message.c| 5 ++-
drivers/accel/amd
For input structures, it is better to check if the pad is zero.
Thus, the pad bytes might be usable in the future.
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/aie2_ctx.c | 3 +++
drivers/accel/amdxdna/aie2_message.c | 3 +++
drivers/accel/amdxdna/amdxdna_ctx.c | 6 ++
drivers/
Add NPU6 registers and other private configurations.
Co-developed-by: Xiaoming Ren
Signed-off-by: Xiaoming Ren
Reviewed-by: Mario Limonciello
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/Makefile | 3 +-
drivers/accel/amdxdna/amdxdna_pci_drv.c | 1 +
drivers/accel/amdxdna/a
Add recent improvements and bug fixes for amdxdna driver (depends on [1])
1. Support recent hardware and firmware.
2. Replace idr APIs with xarray.
3. Fix the bugs been found.
[1]: https://lore.kernel.org/all/20241118172942.2014541-1-lizhi@amd.com/
Changes since v2:
- Remove merged patches fr
> On Tue, Dec 10, 2024 at 09:45:50AM -0800, Johnny Liu wrote:
> > An activity monitor (actmon) is used to measure the device runtime
> > utilization to help drive software power management policies.
> >
> > Extend the reg space to include actmon aperture for actmon configuration
> > through host1x.
> On Tue, Dec 10, 2024 at 09:45:49AM -0800, Johnny Liu wrote:
> > Activity monitoring (actmon for short) is a means to dynamically
> > measure the utilization of units in the system to help drive software
> > power management policies.
> >
>
> Is this a resend or v2? Please always mark your patches
On Fri, Nov 29, 2024 at 10:31:32AM +1100, Alistair Popple wrote:
>
> Matthew Brost writes:
>
> > Avoid multiple CPU page faults to the same device page racing by trying
> > to lock the page in do_swap_page before taking an extra reference to the
> > page. This prevents scenarios where multiple C
Only SSPP, WB and VBIF still have feature bits remaining, all other
hardware blocks don't have feature bits anymore. Remove the 'features'
from the DPU_HW_BLK_INFO so that it doesn't get included into hw info
structures by default and only include it when necessary.
Signed-off-by: Dmitry Baryshkov
Continue cleanup of the feature flags and replace the last remaining LM
feature with a bitfield flag, simplifying corresponding data structures
and access.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++--
drivers/gpu/drm/msm/disp/dpu
Continue cleanup of the feature flags and replace the last remaining LM
feature with a bitfield flag, simplifying corresponding data structures
and access.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8
drivers/gpu/drm/msm/disp/dpu1/ca
Continue cleanup of the feature flags and replace the last remaining CTL
feature with a bitfield flag, simplifying corresponding data structures
and access.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/cat
Drop unused LM features from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 -
Drop unused MDP TOP features from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cata
The DPU_PINGPONG_TE2 is unused by the current code (and can further be
replaced by the checking for the te2 sblk presense). Other feature bits
are completely unused. Drop them from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h |
Continue migration to the MDSS-revision based checks and replace
DPU_SSPP_QOS_8LVL feature bit with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm
Continue migration to the MDSS-revision based checks and drop the
DPU_DIM_LAYER feature bit. It is currently unused, but can be replaed
with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 --
drivers/gpu/drm/msm/disp
Continue migration to the MDSS-revision based checks and replace
DPU_WB_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 +-
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_AUDIO_SELECT feature bit with the core_major_ver == 8 ||
core_major_ver == 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dp
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
Continue migration to the MDSS-revision based checks and replace
DPU_DATA_HCTL_EN feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
drivers/gpu/drm/ms
Continue migration to the MDSS-revision based checks and replace
DPU_MIXER_COMBINED_ALPHA feature bit with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gp
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_DSPP_SUB_BLOCK_FLUSH feature bit with the core_major_ver >= 7
check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h |
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_PERIPH_0_REMOVED feature bit with the core_major_ver >= 8 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h |
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_VSYNC_SEL feature bit with the core_major_ver < 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 -
dr
Continue migration to the MDSS-revision based checks and replace
DPU_PINGPONG_DITHER feature bit with the core_major_ver >= 3 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998
Continue migration to the MDSS-revision based checks and replace
DPU_PINGPONG_DSC feature bit with the core_major_ver < 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 -
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_STATUS_SUPPORTED feature bit with the core_major_ver >= 5
check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gp
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_VM_CFG feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8
The INTF_SC7280_MASK is equal to the INTF_SC7180_MASK. Stop defining a
separate symbol and use the INTF_SC7180_MASK instead.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h| 8
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8 -
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_HAS_LAYER_EXT4 feature bit with the core_major_ver >= 9 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h |
Stop declaring DPU_DSPP_PCC as a part of the DSPP features, use the
presence of the PCC sblk to check whether PCC is present in the hardware
or not.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_
Inline the _setup_mixer_ops() function, it makes it easier to handle
different conditions involving LM configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 24 +---
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/driver
Inline the _setup_dspp_ops() function, it makes it easier to handle
different conditions involving DSPP configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/ms
Inline the _setup_ctl_ops() function, it makes it easier to handle
different conditions involving CTL configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 96 ++
1 file changed, 46 insertions(+), 50 deletions(-)
diff --git a
Inline the _setup_dsc_ops() function, it makes it easier to handle
different conditions involving DSC configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/d
As a preparation to further MDSS-revision cleanups stop passing MDSS
revision to the setup_timing_gen() callback. Instead store a pointer to
it inside struct dpu_hw_intf and use it diretly. It's not that the MDSS
revision can chance between dpu_hw_intf_init() and
dpu_encoder_phys_vid_setup_timing_e
The SM8450 and later chips have DPU_MDP_PERIPH_0_REMOVED feature bit
set, which means that those platforms have dropped some of the
registers, including the WD TIMER-related ones. Stop providing the
callback to program WD timer on those platforms.
Fixes: 100d7ef6995d ("drm/msm/dpu: add support for
Several DPU 5.x platforms are supposed to be using DPU_WB_INPUT_CTRL,
to bind WB and PINGPONG blocks, but they do not. Change those platforms
to use WB_SM8250_MASK, which includes that bit.
Fixes: 1f5bcc4316b3 ("drm/msm/dpu: enable writeback on SC8108X")
Fixes: ab2b03d73a66 ("drm/msm/dpu: enable w
| 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 ++-
50 files changed, 295 insertions(+), 836 deletions(-)
---
base-commit: 789384eb1437aed94155dc0eac8a8a6ba1baf578
change-id: 20241213-dpu-drop-features-7603dc3ee1
From: Youssef Samir
During the initialization of the qaic device, pci_select_bars() is
used to fetch a bitmask of the BARs exposed by the device. On devices
that have Virtual Functions capabilities, the bitmask includes SR-IOV
BARs.
Use a mask to filter out SR-IOV BARs if they exist.
Signed-off
From: Matthew Leung
Refactor the firmware loading code to have distinct helper functions for
BHI and BHIe operations. This lays the foundation for separating the
firmware loading protocol from the firmware being loaded and the EE it
is loaded in.
Signed-off-by: Matthew Leung
Reviewed-by: Yousse
Add basic support for the new AIC200 product. The PCIe Device ID is
0xa110. With this, we can turn on the lights for AIC200 by leveraging
much of the existing driver.
Co-developed-by: Youssef Samir
Signed-off-by: Youssef Samir
Signed-off-by: Jeffrey Hugo
---
drivers/accel/qaic/mhi_controller.c
As the number of cards supported by the driver grows, their
configurations will differ. The driver needs to become more dynamic
to support these configurations. Currently, each card may differ in
the exposed BARs, the regions they map to, and the family.
Create config structs for each card, and le
From: Youssef Samir
AIC200 device will support MSI-X while AIC100 devices will keep using
MSI. pci_alloc_irq_vectors() will try to allocate MSI-X vectors if it
is supported by the target device, otherwise, it will fallback to MSI.
Add support for MSI-X vectors allocation for AIC200 devices.
Sig
From: Youssef Samir
Devices use 1 MSI vector for the MHI controller and as many vectors as
the DMA bridge channels on the device. During the probing of the
device, the driver allocates 32 MSI vectors, which is usually more
than what is needed for AIC100 devices, which is wasting resources.
Alloc
Initial support to the driver to boot up AIC200. AIC200 uses BHIe
without BHI, which is something that the MHI bus has not supported until
now. While the MHI changes are listed first to facilitate cross-tree
merging, they are not needed until the last change in the series.
Also, AIC200 is a differ
From: Matthew Leung
Currently, mhi host only performs firmware transfer via BHI in PBL and
BHIe from SBL. To support BHIe transfer directly from PBL, a policy
needs to be added.
With this policy, BHIe will be used to transfer firmware in PBL if the
mhi controller has bhie regs, sets seg_len, and
Hi Linus,
This is the weekly fixes pull for drm. Just has i915, xe and amdgpu
changes in it, the misc tree didn't get a PR to me this week (cc'ed),
so next week might have a larger set of changes, otherwise nothing too
major in here.
Regards,
Dave.
drm-fixes-2024-12-14:
drm fixes for 6.13-rc3
On Fri, 13 Dec 2024 at 21:15, Abhinav Kumar wrote:
>
>
>
> On 12/12/2024 5:05 PM, Dmitry Baryshkov wrote:
> > On Thu, Dec 12, 2024 at 11:11:54AM -0800, Jessica Zhang wrote:
> >> Filter out modes that have a clock rate greater than the max core clock
> >> rate when adjusted for the perf clock facto
Hi Vignesh
On 12/11/2024 9:10 PM, Vignesh Raman wrote:
Hi Abhinav / Helen,
On 12/12/24 01:48, Abhinav Kumar wrote:
Hi Helen / Vignesh
On 12/4/2024 12:33 PM, Helen Mae Koike Fornazier wrote:
On Wed, 04 Dec 2024 16:21:26 -0300 Abhinav Kumar wrote ---
> Hi Helen
>
> On 12/4/202
On Thu, Dec 12, 2024 at 11:12:39AM +0100, Simona Vetter wrote:
> On Thu, Dec 12, 2024 at 09:49:24AM +0100, Thomas Hellström wrote:
> > On Mon, 2024-12-09 at 16:31 +0100, Simona Vetter wrote:
> > > On Mon, Dec 09, 2024 at 03:03:04PM +0100, Christian König wrote:
> > > > Am 09.12.24 um 14:33 schrieb
On 12/12/2024 5:05 PM, Dmitry Baryshkov wrote:
On Thu, Dec 12, 2024 at 11:11:54AM -0800, Jessica Zhang wrote:
Filter out modes that have a clock rate greater than the max core clock
rate when adjusted for the perf clock factor
This is especially important for chipsets such as QCS615 that hav
Many selftests call igt_flush_test() on cleanup. With default preemption
timeout of compute engines raised to 7.5 seconds, hardcoded flush timeout
of 3 seconds is too short. That results in GPU forcibly wedged and kernel
taineted, then IGT abort triggered. CI BAT runs loose a part of their
expec
From: Youssef Samir
aic100_image_table is currently defined as a "const char *" array,
this can potentially lead to the accidental modification of the
pointers inside. Also, checkpatch.pl gives a warning about it.
Change the type to a "const char * const" array to make the pointers
immutable, pr
From: "Eric R. Smith"
MediaTek (MTK) uses some unique tiled memory formats
for video decoding. Add these to the uapi drm_fourcc.h
so that we can use them in Mesa, GStreamer, and other
tools/libraries.
Signed-off-by: Eric R. Smith
---
include/uapi/drm/drm_fourcc.h | 31 +
On Thursday, 12 December 2024 02:52:34 EST Andy Yan wrote:
> Hi Detlev,
>
> At 2024-12-11 23:45:01, "Detlev Casanova"
wrote:
> >On Wednesday, 11 December 2024 01:34:34 EST Andy Yan wrote:
> >> Hi Detlev,
> >>
> >> At 2024-12-11 02:40:14, "Detlev Casanova"
> >
> >wrote:
> >> >Hi Andy,
> >> >
>
On 12/13/2024 10:57 AM, Lizhi Hou wrote:
On 12/13/24 09:49, Jeffrey Hugo wrote:
On 12/13/2024 10:41 AM, Lizhi Hou wrote:
On 12/13/24 09:07, Jeffrey Hugo wrote:
On 12/13/2024 2:02 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
The old SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS macros cau
On 12/13/24 09:49, Jeffrey Hugo wrote:
On 12/13/2024 10:41 AM, Lizhi Hou wrote:
On 12/13/24 09:07, Jeffrey Hugo wrote:
On 12/13/2024 2:02 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
The old SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS macros cause
a build
warning when CONFIG_PM is di
On Fri, Dec 13, 2024 at 8:47 AM Akhil P Oommen wrote:
>
> On 12/12/2024 10:42 PM, Rob Clark wrote:
> > On Thu, Dec 12, 2024 at 9:08 AM Rob Clark wrote:
> >>
> >> On Thu, Dec 12, 2024 at 7:59 AM Akhil P Oommen
> >> wrote:
> >>>
> >>> On 12/5/2024 10:24 PM, Rob Clark wrote:
> From: Rob Clark
On 12/13/2024 10:41 AM, Lizhi Hou wrote:
On 12/13/24 09:07, Jeffrey Hugo wrote:
On 12/13/2024 2:02 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
The old SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS macros cause a
build
warning when CONFIG_PM is disabled:
drivers/accel/amdxdna/amdxdna_pci
On 12/13/24 09:07, Jeffrey Hugo wrote:
On 12/13/2024 2:02 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
The old SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS macros cause a
build
warning when CONFIG_PM is disabled:
drivers/accel/amdxdna/amdxdna_pci_drv.c:343:12: error:
'amdxdna_pmops_res
On 12/13/24 08:55, Jeffrey Hugo wrote:
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
+/**
+ * struct amdxdna_drm_get_power_mode - Get the configured power mode
+ * @power_mode: The mode type from enum amdxdna_power_mode_type
+ * @pad: MBZ.
I don't see a check for zero in the implementation
We discu
Hi,
On Wed, Dec 4, 2024 at 2:58 AM Uwe Kleine-König
wrote:
>
> These drivers don't use the driver_data member of struct i2c_device_id,
> so don't explicitly initialize this member.
>
> This prepares putting driver_data in an anonymous union which requires
> either no initialization or named desig
On 12/13/2024 10:02 AM, Lizhi Hou wrote:
On 12/13/24 08:58, Jeffrey Hugo wrote:
On 12/6/2024 3:00 PM, Lizhi Hou wrote:
The latest released firmware supports reading firmware interface version
from registers directly. The driver's probe routine reads the major and
minor version numbers. If the
On 12/13/2024 9:38 AM, Lizhi Hou wrote:
From: Mike Lothian
For amdxdna_mailbox.c, linux/interrupt.h is indirectly included by
trace/events/amdxdna.h. So if TRACING is disabled, driver compiling will
fail.
Fixes: b87f920b9344 ("accel/amdxdna: Support hardware mailbox")
Reported-by: Mike Lothian
On Fri, Dec 13, 2024 at 02:27:09PM +0100, Borislav Petkov wrote:
> On Fri, Dec 13, 2024 at 10:35:03AM +0200, Kalle Valo wrote:
> > I agree, it makes the code harder to read for someone who is not
> > familiar with all the %p magic we have (like me).
> +1
And me too. In case one thinks of unprinta
On 12/13/2024 2:02 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
This driver fails to build in random configurations:
drivers/accel/amdxdna/amdxdna_mailbox.c:357:8: error: unknown type name
'irqreturn_t'
357 | static irqreturn_t mailbox_irq_handler(int irq, void *p)
|^~~~
On 12/13/24 5:50 PM, Akhil P Oommen wrote:
On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
On 12/12/24 4:58 PM, Akhil P Oommen wrote:
On 12/5/2024 10:24 PM, Rob Clark wrote:
From: Rob Clark
Performance counter usage falls into two categories:
1. Local usage, where the counter configuratio
On 12/13/2024 2:02 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
The old SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS macros cause a build
warning when CONFIG_PM is disabled:
drivers/accel/amdxdna/amdxdna_pci_drv.c:343:12: error: 'amdxdna_pmops_resume'
defined but not used [-Werror=unused-fu
On 12/13/2024 9:38 AM, Lizhi Hou wrote:
From: Mike Lothian
For amdxdna_mailbox.c, linux/interrupt.h is indirectly included by
trace/events/amdxdna.h. So if TRACING is disabled, driver compiling will
fail.
Fixes: b87f920b9344 ("accel/amdxdna: Support hardware mailbox")
Reported-by: Mike Lothian
On 12/13/24 08:58, Jeffrey Hugo wrote:
On 12/6/2024 3:00 PM, Lizhi Hou wrote:
The latest released firmware supports reading firmware interface version
from registers directly. The driver's probe routine reads the major and
minor version numbers. If the firmware interface does not compatible
w
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
Add recent improvements and bug fixes for amdxdna driver (depends on [1])
1. Support recent hardware and firmware.
2. Replace idr APIs with xarray.
3. Fix the bugs been found.
[1]: https://lore.kernel.org/all/20241118172942.2014541-1-lizhi@amd.com/
Cha
On 12/6/2024 3:00 PM, Lizhi Hou wrote:
The latest released firmware supports reading firmware interface version
from registers directly. The driver's probe routine reads the major and
minor version numbers. If the firmware interface does not compatible with
the driver, the driver's probe routine
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
+/**
+ * struct amdxdna_drm_get_power_mode - Get the configured power mode
+ * @power_mode: The mode type from enum amdxdna_power_mode_type
+ * @pad: MBZ.
I don't see a check for zero in the implementation
+ */
+struct amdxdna_drm_get_power_mode {
+
On 12/13/2024 10:10 PM, neil.armstr...@linaro.org wrote:
> On 13/12/2024 17:31, Konrad Dybcio wrote:
>> On 13.12.2024 5:28 PM, neil.armstr...@linaro.org wrote:
>>> On 13/12/2024 16:37, Konrad Dybcio wrote:
On 13.12.2024 2:12 PM, Akhil P Oommen wrote:
> On 12/13/2024 3:07 AM, Neil Armstrong
On 12/13/24 08:42, Jeffrey Hugo wrote:
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
Switch mailbox message id and hardware context id management over from
the idr api to the xarray api.
Signed-off-by: Lizhi Hou
Implementation looks sane, however you appear to be missing several
instances of #in
On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
> On 12/12/24 4:58 PM, Akhil P Oommen wrote:
>> On 12/5/2024 10:24 PM, Rob Clark wrote:
>>> From: Rob Clark
>>>
>>> Performance counter usage falls into two categories:
>>>
>>> 1. Local usage, where the counter configuration, start, and end read
>>
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
Enhance GET_INFO ioctl to support retrieving firmware version.
Signed-off-by: Lizhi Hou
Reviewed-by: Jeffrey Hugo
Warning below through.
enum amdxdna_drm_get_param {
DRM_AMDXDNA_QUERY_AIE_STATUS,
DRM_AMDXDNA_QUERY_AIE_METADATA,
@@ -
On 12/12/2024 10:42 PM, Rob Clark wrote:
> On Thu, Dec 12, 2024 at 9:08 AM Rob Clark wrote:
>>
>> On Thu, Dec 12, 2024 at 7:59 AM Akhil P Oommen
>> wrote:
>>>
>>> On 12/5/2024 10:24 PM, Rob Clark wrote:
From: Rob Clark
Performance counter usage falls into two categories:
>>>
On 12/13/24 08:37, Jeffrey Hugo wrote:
On 12/6/2024 2:59 PM, Lizhi Hou wrote:
Add NPU6 registers and other private configurations.
Co-developed-by: Xiaoming Ren
Signed-off-by: Xiaoming Ren
Signed-off-by: Lizhi Hou
---
drivers/accel/amdxdna/Makefile | 3 +-
drivers/accel/amdxdna/npu
Hi Tomi,
Thank you for the patch.
On Fri, Dec 13, 2024 at 04:02:59PM +0200, Tomi Valkeinen wrote:
> From: Tomi Valkeinen
>
> The binding is missing maxItems for all renesas,cmms and renesas,vsps
> properties. As the amount of cmms or vsps is always a fixed amount, set
> the maxItems to match th
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