ping for review
Am 05.11.24 um 14:20 schrieb Thomas Zimmermann:
Remove the connector-status initialization from several of vmwgfx's
functions. It is not required by the driver or DRM helpers.
DRM initializes the connector to unknown status in __drm_connector_init()
and reads the physical statu
On 21-11-24, 18:31, Jyothi Kumar Seerapu wrote:
> GSI hardware generates an interrupt for each transfer completion.
> For multiple messages within a single transfer, this results in
> N interrupts for N messages, leading to significant software
> interrupt latency.
>
> To mitigate this latency, ut
The information passed as request tgid and pid is actually the
client id of the process. This client id is used as an
identifier by DSP to identify the DSP PD corresponding to the
process. Currently process tgid is getting passed as the
identifier which is getting replaced by a custom client id.
Re
Memory intensive applications(which requires more tha 4GB) that wants
to offload tasks to DSP might have to split the tasks to multiple
user PD to make the resources available.
For every call to DSP, fastrpc driver passes the process tgid which
works as an identifier for the DSP to enqueue the tas
This patch series carries changes to use a masked session index
as an identifier instead of process tgid to support mutiple PDs
from same process.
Patch [v4]:
https://lore.kernel.org/all/20241121084713.2599904-1-quic_ekang...@quicinc.com/
Changes in v5:
- Remove mask and just modify session ind
On 11/27/2024, Nikolaus Voss wrote:
> LDB clock has to be a fixed multiple of the pixel clock.
> As LDB and pixel clock are derived from different clock sources
> (at least on imx8mp), this constraint cannot be satisfied for
> any pixel clock, which leads to flickering and incomplete
> lines on the
Hi,
On 2024/11/30 22:51, Markus Elfring wrote:
Because the of_dma_configure() will returns '-EPROBE_DEFER' if the probe
return?
…
Stop pretending that it will always suceess, quit if it fail.
succeed?
drm_panel_init() was made to initialize the fields in |struct drm_panel|.
There is no need to separately initialize them again.
Drop the separate assignments that are redundant.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/panel/panel-visionox-rm69299.c | 3 ---
1 file changed, 3 deletions(-
Move out dmabuf detachment and unmapping into separate function. This
removes duplicated code and there is no need to check the GEM's kref now,
since both bo->attached and bo->sgt are unset under held reservation lock.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/virtio/virtgpu_prime.c | 3
Hi,
On 2024/12/2 6:59, Sebastian Reichel wrote:
Hi,
On Sat, Nov 30, 2024 at 09:25:12PM +0100, Heiko Stübner wrote:
Am Freitag, 29. November 2024, 03:43:57 CET schrieb Damon Ding:
On 2024/11/27 19:04, Heiko Stübner wrote:
Am Mittwoch, 27. November 2024, 12:00:10 CET schrieb Damon Ding:
On 20
MX8-DLVDS-LCD1 display module integrates a KOE TX26D202VM0BWA LCD panel
and a touch IC. Add an overlay to support the LCD panel on i.MX8qxp
MEK. mipi_lvds_0_ldb channel0 and mipi_lvds_1_ldb channel1 send odd
and even pixels to the panel respectively.
Signed-off-by: Liu Ying
---
v5:
* No change.
Enable display controller for i.MX8qxp MEK.
Signed-off-by: Liu Ying
---
v5:
* No change.
v4:
* No change.
v3:
* No change.
v2:
* New patch. (Francesco)
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-
The MIPI-LVDS combo subsystems are peripherals of pixel link MSI
bus in i.MX8qxp display controller subsystem. Add the MIPI-LVDS
combo subsystems.
Signed-off-by: Liu Ying
---
v5:
* No change.
v4:
* No change.
v3:
* No change.
v2:
* New patch. (Francesco)
.../boot/dts/freescale/imx8qxp-ss-dc
Add display controller subsystem in i.MX8qxp SoC.
Signed-off-by: Liu Ying
---
v5:
* No change.
v4:
* No change.
v3:
* No change.
v2:
* New patch. (Krzysztof)
.../arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 408 ++
.../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 236 ++
assigned-clock* properties can be used by default now, so allow them.
Signed-off-by: Liu Ying
---
v5:
* No change.
v4:
* No change.
v3:
* No change.
v2:
* New patch as needed by MIPI/LVDS subsystems device tree.
.../devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml | 5 -
1 file c
Document SCU controlled display pixel link child nodes.
Signed-off-by: Liu Ying
---
v5:
* No change.
v4:
* No change.
v3:
* No change.
v2:
* New patch as needed by display controller subsystem device tree.
.../devicetree/bindings/firmware/fsl,scu.yaml | 20 +++
1 file changed
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer. Add kernel
mode setting support for the display controller part with two CRTCs and
two p
Add myself as the maintainer of i.MX8qxp Display Controller.
Signed-off-by: Liu Ying
---
v5:
* No change.
v4:
* No change.
v3:
* No change.
v2:
* Improve file list. (Frank)
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1240e75ecf4b..f
i.MX8qxp Display Controller pixel engine consists of all processing
units that operate in the AXI bus clock domain. Add drivers for
ConstFrame, ExtDst, FetchLayer, FetchWarp and LayerBlend units, as
well as a pixel engine driver, so that two displays with primary
planes can be supported. The pixe
i.MX8qxp Display Controller contains a command sequencer is designed to
autonomously process command lists.
Signed-off-by: Liu Ying
---
v5:
* No change.
v4:
* Replace "fsl,iram" property with standard "sram" property. (Rob)
v3:
* New patch. (Rob)
.../imx/fsl,imx8qxp-dc-command-sequencer.yaml
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit. Add driver for it.
Signed-off-by: Liu Ying
---
v5:
* Replace .remove_new with .remove in dc-ic.c. (Uwe)
v4:
* Use regmap to define register map for all registers. (Dmitry)
* Use
i.MX8qxp Display Controller display engine consists of all processing
units that operate in a display clock domain. Add minimal feature
support with FrameGen and TCon so that the engine can output display
timings. The FrameGen driver, TCon driver and display engine driver
are components to be agg
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer.
Signed-off-by: Liu Ying
---
v5:
* Document aliases. Drop Rob's previous R-b tag. (Maxi
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v5:
* No change.
v4:
* No change.
v3:
* Collect Rob's R-b tag.
v2:
* Drop unneeded "|". (Krzysztof)
.../fsl,imx8qxp
i.MX8qxp Display Controller contains a AXI performance counter which allows
measurement of average bandwidth and latency during operation.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v5:
* No change.
v4:
* Collect Rob's R-b tag.
v3:
* New patch. (Rob)
...sl,imx8qxp-dc-axi-perf
i.MX8qxp Display Controller display engine consists of all processing units
that operate in a display clock domain.
Signed-off-by: Liu Ying
---
v5:
* Document aliases. Drop Rob's previous R-b tag. (Maxime)
v4:
* Collect Rob's R-b tag.
v3:
* No change.
v2:
* Drop fsl,dc-*-id DT properties. (Kr
i.MX8qxp Display Controller pixel engine consists of all processing units
that operate in the AXI bus clock domain. Command sequencer and interrupt
controller of the Display Controller work with AXI bus clock, but they are
not in pixel engine.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Ar
i.MX8qxp Display Controller contains a blit engine for raster graphics.
It may read up to 3 source images from memory and computes one destination
image from it, which is written back to memory.
Signed-off-by: Liu Ying
Reviewed-by: Rob Herring (Arm)
---
v5:
* No change.
v4:
* Collect Rob's R-b
Freescale i.MX8qxp Display Controller is implemented as construction set of
building blocks with unified concept and standardized interfaces. Document
all existing processing units.
Signed-off-by: Liu Ying
---
v5:
* Document aliases for processing units which have multiple instances in
the Dis
Hi,
This patch series aims to add Freescale i.MX8qxp Display Controller support.
The controller is comprised of three main components that include a blit
engine for 2D graphics accelerations, display controller for display output
processing, as well as a command sequencer.
Previous patch series
On 12/01/2024, Uwe Kleine-König wrote:
> Hello,
Hello,
>
> On Mon, Nov 25, 2024 at 05:33:06PM +0800, Liu Ying wrote:
>> +struct platform_driver dc_de_driver = {
>> +.probe = dc_de_probe,
>> +.remove_new = dc_de_remove,
>
> Please use .remove here. Also in a few other patches of this ser
Hi Krzysztof,
On 2024/11/27 18:23, Krzysztof Kozlowski wrote:
On 27/11/2024 08:51, Damon Ding wrote:
Add the compatible "rockchip,rk3588-edp".
This we see from the diff. Say something about hardware and why it is
not compatible with existing variants.
In response to your kind suggestion, I
Hi,
On Sat, Nov 30, 2024 at 09:25:12PM +0100, Heiko Stübner wrote:
> Am Freitag, 29. November 2024, 03:43:57 CET schrieb Damon Ding:
> > On 2024/11/27 19:04, Heiko Stübner wrote:
> > > Am Mittwoch, 27. November 2024, 12:00:10 CET schrieb Damon Ding:
> > >> On 2024/11/27 17:29, Heiko Stübner wrote:
On Sat, Nov 30, 2024 at 12:30 PM Akhil P Oommen
wrote:
>
> On 11/30/2024 7:01 PM, Konrad Dybcio wrote:
> > On 25.11.2024 5:33 PM, Akhil P Oommen wrote:
> >> There are a few chipsets which don't have system cache a.k.a LLC.
> >> Currently, the assumption in the driver is that the system cache
> >>
Hi Dmitry,
On Sat, 30 Nov 2024, Dmitry Baryshkov wrote:
On Tue, Nov 26, 2024 at 04:45:54PM +0100, Nikolaus Voss wrote:
LDB clock has to be a fixed multiple of the pixel clock.
As LDB and pixel clock are derived from different clock sources
(at least on imx8mp), this constraint cannot be satisfi
Hi Srikar & Louis,
On 01/12/24 02:36, Louis Chauvet wrote:
+Cc: dri-devel@lists.freedesktop.org
On 30/11/24 - 13:49, Ananta Srikar Puranam wrote:
Dear Louis Chauvet,
Hi Srikar!
I was able to successfully compile Linux with VKMS enabled and have set up
igt-gpu-tests in a QEMU machine. I can
From: Yonatan Maman
Handle P2P DMA mapping errors when the transaction requires traversing
an inaccessible host bridge that is not in the allowlist:
- In `populate_mtt`, if a P2P mapping fails, the `HMM_PFN_ALLOW_P2P` flag
is cleared only for the PFNs that returned a mapping error.
- In `page
From: Yonatan Maman
ATS (Address Translation Services) mainly utilized to optimize PCI
Peer-to-Peer transfers and prevent bus failures. This change employed
ATS usage for ODP memory, to optimize DMA P2P for ODP memory. (e.g DMA
P2P for private device pages - ODP memory).
Signed-off-by: Yonatan M
From: Yonatan Maman
Enabling Peer-to-Peer DMA (P2P DMA) access in GPU-centric applications
is crucial for minimizing data transfer overhead (e.g., for RDMA use-
case).
This change aims to enable that capability for Nouveau over HMM device
private pages. P2P DMA for private device pages allows th
From: Yonatan Maman
Add Peer-to-Peer (P2P) DMA request for hmm_range_fault calling,
utilizing capabilities introduced in mm/hmm. By setting
range.default_flags to HMM_PFN_REQ_FAULT | HMM_PFN_REQ_TRY_P2P, HMM
attempts to initiate P2P DMA connections for device private pages
(instead of page fault
From: Yonatan Maman
Based on: Provide a new two step DMA mapping API patchset
https://lore.kernel.org/kvm/20241114170247.ga5...@lst.de/T/#t
This patch series aims to enable Peer-to-Peer (P2P) DMA access in
GPU-centric applications that utilize RDMA and private device pages. This
enhancement redu
From: Yonatan Maman
hmm_range_fault() by default triggered a page fault on device private
when HMM_PFN_REQ_FAULT flag was set. pages, migrating them to RAM. In some
cases, such as with RDMA devices, the migration overhead between the
device (e.g., GPU) and the CPU, and vice-versa, significantly d
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