On 2024/11/27 15:15, Krzysztof Kozlowski wrote:
On 27/11/2024 08:05, Yongxing Mou wrote:
Document the MDSS hardware found on the Qualcomm QCS8300 platform.
Signed-off-by: Yongxing Mou
Will fail testing, so only limited review.
Thanks for reviewing,will fix it in next patchset.
+exampl
On Tue, Nov 26, 2024 at 10:11:48PM +0800, Sandor Yu wrote:
> Add bindings for Cadence MHDP8501 DisplayPort/HDMI bridge.
>
> Signed-off-by: Sandor Yu
> ---
> v18->v19:
> - move data-lanes property to endpoint of port@1
>
> v17->v18:
> - remove lane-mapping and replace it with data-lanes
> - remov
On 11/26/2024, Miquel Raynal wrote:
> Hi Liu,
Hi,
>
The
pixel clock can be got from LDB's remote input LCDIF DT node by
calling of_clk_get_by_name() in fsl_ldb_probe() like the below patch
does. Similar to setting pixel clock rate, I think a chance is that
pixel clock en
On 27/11/2024 04:32, Hironori KIKUCHI wrote:
> Hello Krzysztof,
>
> Thank you for your reply.
>
>>> The old schemas "leadtek,ltk035c5444t", "fascontek,fs035vg158", and
>>> "anbernic,rg35xx-plus-panel" exist independently.
>> So you duplicate them. I wrote: Don't duplicate.
>
> Ok, thanks. I won'
On 27/11/2024 08:05, Yongxing Mou wrote:
> Document the MDSS hardware found on the Qualcomm QCS8300 platform.
>
> Signed-off-by: Yongxing Mou
Will fail testing, so only limited review.
> +examples:
> + - |
> +#include
> +#include
> +#include
> +#include
> +#include
>
Add definitions for the display hardware used on the
Qualcomm QCS8300 platform.
Signed-off-by: Yongxing Mou
---
.../drm/msm/disp/dpu1/catalog/dpu_8_4_qcs8300.h| 485 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog
Document the MDSS hardware found on the Qualcomm QCS8300 platform.
Signed-off-by: Yongxing Mou
---
.../bindings/display/msm/qcom,qcs8300-mdss.yaml| 239 +
1 file changed, 239 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
On 27/11/2024 08:05, Yongxing Mou wrote:
> This series introduces support to enable the Mobile Display Subsystem (MDSS)
> and Display Processing Unit (DPU) for the Qualcomm QCS8300 target. It
> includes the addition of the hardware catalog, compatible string,
> relevant device tree changes, and the
Document the DPU for Qualcomm QCS8300 platform.
Signed-off-by: Yongxing Mou
---
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
b/Documentation/devicetree/bi
Add devicetree changes to enable MDSS display-subsystem and its
display-controller(DPU) for Qualcomm QCS8300 platform.
Signed-off-by: Yongxing Mou
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 87 +++
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dt
Add Mobile Display Subsystem (MDSS) support for the QCS8300 platform.
Signed-off-by: Yongxing Mou
---
drivers/gpu/drm/msm/msm_mdss.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
b7bd899ead44bf86998e7295bcc
This series introduces support to enable the Mobile Display Subsystem (MDSS)
and Display Processing Unit (DPU) for the Qualcomm QCS8300 target. It
includes the addition of the hardware catalog, compatible string,
relevant device tree changes, and their YAML bindings.
Signed-off-by: Yongxing Mou
-
Hi Dmitry,
> Subject: Re: [PATCH v5 0/5] drm/virtio: Import scanout buffers from other
> devices
>
> Hello, Vivek
>
> All patches applied to misc-next with a small modification, thanks!
Thank you so much for taking the time to test, review and merge this series!!
>
> Note: While verifying move
Hi Dmitry,
> >> Wondering if it could be a problem with my guest kernel config. I
> >> attached my config to the email, please try to boot guest with my config
> >> if you'll have time.
> > Sure, let me try to test with your config. Could you also please share your
> > Qemu launch parameters?
>
>
On Wed, Nov 27, 2024 at 11:02 AM Xin Ji wrote:
>
> Update HDCP content_protection to DRM_MODE_CONTENT_PROTECTION_UNDESIRED
> in bridge .atomic_disable().
>
> Signed-off-by: Xin Ji
Tested-by: Pin-yen Lin
> ---
> drivers/gpu/drm/bridge/analogix/anx7625.c | 25 ++-
> 1 file ch
Hello Krzysztof,
Thank you for your reply.
> > The old schemas "leadtek,ltk035c5444t", "fascontek,fs035vg158", and
> > "anbernic,rg35xx-plus-panel" exist independently.
> So you duplicate them. I wrote: Don't duplicate.
Ok, thanks. I won't duplicate.
They are already duplicated in the tree with
Update HDCP content_protection to DRM_MODE_CONTENT_PROTECTION_UNDESIRED
in bridge .atomic_disable().
Signed-off-by: Xin Ji
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 25 ++-
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/an
Hi Laurent
Thank you for the reply
> > Hi Maarten, Maxime, Thomas
> > Cc Laurent
> >
> > The patch has been created as 1 patch for "drivers/gpu/drm", but this time
> > I have finely disassembled the patch into 3 patches.
>
> Thomas has merged v6 in drm-misc in commit
> 17558f97fe62fbe1475788
Hi Lyude,
> On 30 Sep 2024, at 20:09, Lyude Paul wrote:
>
> We start off by introducing wrappers for the first important type of mode
> object: a DRM display connector. This introduces Connector DriverConnector> and ConnectorState. Both
> DriverConnector and DriverConnectorState must be implemen
On Tue, Nov 26, 2024 at 05:34:21PM +0100, Sasha Finkelstein via B4 Relay wrote:
> +module_platform_driver(adp_mipi_platform_driver);
This is part of the same driver as adp_drv.c, so I don't think there's
supposed to be another module_platform_driver() call here?
/nix/store/hni09p7jhc8szjr2h5j5m0l
Hi Lyude,
> On 30 Sep 2024, at 20:09, Lyude Paul wrote:
>
> The KMS API has a very consistent idea of a "mode config object", which
> includes any object with a drm_mode_object struct embedded in it. These
> objects have their own object IDs which DRM exposes to userspace, and we
> introduce the
This series adds a bridge and glue driver for the DSI2 controller found
in the rk3588 soc from Rockchip, that is based on a Synopsis IP block.
As the manual states:
The Display Serial Interface 2 (DSI-2) is part of a group of communication
protocols defined by the MIPI Alliance. The MIPI DSI-2 Hos
From: Heiko Stuebner
Add a Synopsys Designware MIPI DSI host DRM bridge driver for their
DSI2 host controller, based on the Rockchip version from the driver
rockchip/dw-mipi-dsi2.c in their vendor-kernel with phy & bridge APIs.
While the driver is heavily modelled after the previous IP, the regi
From: Heiko Stuebner
This adds the glue code for the MIPI DSI2 bridge on Rockchip SoCs and
enables its use on the RK3588.
Right now the DSI2 controller is always paired with a DC-phy based on a
Samsung IP, so the interface values are set statically for now.
This stays true for the upcoming RK357
From: Heiko Stuebner
The Display Serial Interface 2 (DSI-2) is part of a group of communication
protocols defined by the MIPI Alliance. The RK3588 implements this
specification in its two MIPI DSI-2 Host Controllers that are based on a
new Synopsis IP.
Signed-off-by: Heiko Stuebner
---
.../roc
Hi Lyude,
> On 30 Sep 2024, at 20:09, Lyude Paul wrote:
>
> For drivers which use the shmem based GEM helpers, they'll want to use the
> relevant drm_fbdev_shmem_setup() functions instead of the
> drm_fbdev_dma_setup() functions. To allow for this, introduce another
> FbdevImpl that such drivers
On Tue, Nov 26, 2024 at 10:11:49PM +0800, Sandor Yu wrote:
> Add a new DRM DisplayPort and HDMI bridge driver for Candence MHDP8501
> used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
> standards according embedded Firmware running in the uCPU.
>
> For iMX8MQ SOC, the DisplayPort/HDM
On 2024/11/27 2:20, Krzysztof Kozlowski wrote:
> On 26/11/2024 18:00, Sasha Finkelstein wrote:
>> On Tue, 26 Nov 2024 at 17:46, Krzysztof Kozlowski wrote:
+properties:
+ compatible:
+items:
+ - enum:
+ - apple,j293-summit
+ - apple,j493-
+Cc: Miquèl, who is actively working on imx8mp video clock rates.
On Tue, 26 Nov 2024 16:45:54 +0100
Nikolaus Voss wrote:
> LDB clock has to be a fixed multiple of the pixel clock.
> As LDB and pixel clock are derived from different clock sources
> (at least on imx8mp), this constraint cannot be
Hi Lyude,
> On 30 Sep 2024, at 20:09, Lyude Paul wrote:
>
> This commit adds some traits for registering DRM devices with KMS support,
> implemented through the kernel::drm::kms::Kms trait. Devices which don't
> have KMS support can simply use PhantomData.
>
> Signed-off-by: Lyude Paul
>
> --
On Tue, 26 Nov 2024 at 18:00, Maxime Ripard wrote:
>
> On Tue, Nov 26, 2024 at 12:07:10AM +0200, Dmitry Baryshkov wrote:
> > On Mon, 25 Nov 2024 at 15:17, Maxime Ripard wrote:
> > >
> > > On Fri, Nov 22, 2024 at 03:32:57PM +0200, Dmitry Baryshkov wrote:
> > > > On Tue, Nov 12, 2024 at 03:05:37AM
On Tue, Nov 26, 2024 at 09:19:47AM +0100, Christian König wrote:
> Am 25.11.24 um 18:27 schrieb Matthew Brost:
> > On Mon, Nov 25, 2024 at 05:19:54PM +0100, Christian König wrote:
> > > Am 25.11.24 um 16:29 schrieb Matthew Brost:
> > > > On Fri, Nov 15, 2024 at 10:27:59AM -0800, Matthew Brost wrote
xe_bo_vmap only works on contiguous BOs, disallow xe_bo_vmap on BO
unless we are certain the BO is contiguous.
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/xe/xe_bo.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drive
Non-contiguous VRAM cannot easily be mapped in TTM nor can non-visible
VRAM easily be accessed. Add xe_ttm_access_memory which hooks into
ttm_bo_access to access such memory.
v4:
- Assert memory access rather than taking RPM ref (Thomas / Auld)
- Fix warning on xe_res_cursor.h for non-zero offse
The delayed snapshot capture worker can access the GPU or VRAM both of
which require a PM reference. Take a reference in this worker.
Cc: Rodrigo Vivi
Cc: Maarten Lankhorst
Fixes: 4f04d07c0a94 ("drm/xe: Faster devcoredump")
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Auld
---
drivers/gp
We only allow continguous BOs to be vmapped, set XE_BO_FLAG_PINNED on
BOs in migrate selftest as this forces continguous BOs and selftest uses
vmaps.
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/xe/tests/xe_migrate.c | 13 +
1 file changed, 9 insertions
Add xe_bo_vm_access which is wrapper around ttm_bo_vm_access which takes
rpm refs for device access.
Suggested-by: Thomas Hellström
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/xe/xe_bo.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
dif
Non-contiguous mapping of BO in VRAM doesn't work, use ttm_bo_access
instead.
v2:
- Fix error handling
Fixes: 0eb2a18a8fad ("drm/xe: Implement VM snapshot support for BO's and
userptr")
Suggested-by: Matthew Auld
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/xe/
Don't open code vmap of a BO, use ttm_bo_access helper which is safe for
non-contiguous BOs and non-visible BOs.
Suggested-by: Matthew Auld
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/xe/display/intel_bo.c | 25 +
1 file changed, 1 inserti
Fully reviewed and resending for final CI.
Dropping non-visible patch for now as it a bit larger, not strickly
required to unblock EU debug, and be sent independently in a follow up.
Matt
Matthew Brost (8):
drm/xe: Add xe_bo_vm_access
drm/ttm: Add ttm_bo_access
drm/xe: Add xe_ttm_access_me
Non-contiguous VRAM cannot easily be mapped in TTM nor can non-visible
VRAM easily be accessed. Add ttm_bo_access, which is similar to
ttm_bo_vm_access, to access such memory.
v4:
- Fix checkpatch warnings (CI)
v5:
- Fix checkpatch warnings (CI)
v6:
- Fix kernel doc (Auld)
v7:
- Move ttm_bo_ac
Hi Lyude, sorry for the late review!
> On 30 Sep 2024, at 20:09, Lyude Paul wrote:
>
> This adds some very basic rust bindings for fourcc. We only have a single
> format code added for the moment, but this is enough to get a driver
> registered.
>
> TODO:
> * Write up something to automatically
On 26/11/2024 18:00, Sasha Finkelstein wrote:
> On Tue, 26 Nov 2024 at 17:46, Krzysztof Kozlowski wrote:
>>> +allOf:
>>> + - $ref: dsi-controller.yaml#
> ...
>>> +patternProperties:
>>> + "^panel@[0-3]$": true
>>
>> These look unusual. Is this a DSI controller? If so, then reference
>> dsi-contr
See my comments inline below:
Regards,
Zhanjun
On 2024-11-17 1:44 p.m., Alan Previn wrote:
The order of the devcoredump event flow is:
drm-scheduler -> guc-submission-execq-timed-out-job ->
guc-submission-kill-job -> xe-devcoredump (once the work
is confirmed to have been killed).
As we are aw
On 26/11/2024 17:46, Krzysztof Kozlowski wrote:
>
>> +
>> + reg:
>> +maxItems: 1
>> +
>> + max-brightness: true
>> +
>> + port: true
>
> No, these cannot be true without definition. Again, please open existing
> bindings and use them as example. You probably miss here some reference,
> but
On 26/11/2024 17:34, Sasha Finkelstein wrote:
> On Mon, 25 Nov 2024 at 16:07, Krzysztof Kozlowski wrote:
>>
>> BTW, max-brightness is a property of backlight, not panel, I think.
> This is an oled panel, so no separate backlight device, the mipi commands
> just change the pixel brightness. There i
On 26/11/2024 17:34, Sasha Finkelstein via B4 Relay wrote:
> /*
> * Force the bus number assignments so that we can declare some of the
> * on-board devices and properties that are populated by the bootloader
> diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi
> b/arch/arm64/boot/dts/apple/t8
On 26/11/2024 17:34, Sasha Finkelstein via B4 Relay wrote:
> From: Sasha Finkelstein
>
> Add bindings for a secondary display controller present on certain
> Apple laptops.
>
A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindi
Hi.
This patch series adds support for a secondary display controller
present on Apple M1/M2 chips and used to drive the display of the
"touchbar" touch panel present on those.
Signed-off-by: Sasha Finkelstein
---
Changes in v2:
- Addressing the review feedback.
- Split out the mipi part of the
On 11/26/24 4:56 PM, Maxime Ripard wrote:
On Tue, Nov 26, 2024 at 12:48:20AM +0100, Marek Vasut wrote:
On 11/22/24 2:32 PM, Dmitry Baryshkov wrote:
On Tue, Nov 12, 2024 at 03:05:37AM +0100, Marek Vasut wrote:
The Pixel PLL is not very capable and may come up with wildly inaccurate
clock. Since
From: Sasha Finkelstein
This is the display panel used for the touchbar on laptops that have it.
Co-developed-by: Nick Chan
Signed-off-by: Nick Chan
Signed-off-by: Sasha Finkelstein
---
drivers/gpu/drm/panel/Kconfig| 9 +++
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/
From: Sasha Finkelstein
Adds device tree entries for the touchbar screen
Co-developed-by: Janne Grunau
Signed-off-by: Janne Grunau
Signed-off-by: Sasha Finkelstein
---
arch/arm64/boot/dts/apple/t8103-j293.dts | 31
arch/arm64/boot/dts/apple/t8103.dtsi | 61 ++
From: Sasha Finkelstein
Add the MAINTAINERS entries for the driver
Signed-off-by: Sasha Finkelstein
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
e7f0170977013889ca7c39b17727ba36d32e92dc..9a2fb7cd80e09f24932b91cd33d0cd2b3514b31c
1006
From: Sasha Finkelstein
Add bindings for a secondary display controller present on certain
Apple laptops.
Signed-off-by: Sasha Finkelstein
---
.../display/apple,h7-display-pipe-mipi.yaml| 89 ++
.../bindings/display/apple,h7-display-pipe.yaml| 77 +++
From: Sasha Finkelstein
This display controller is present on M-series chips and is used
to drive the touchbar display.
Co-developed-by: Janne Grunau
Signed-off-by: Janne Grunau
Signed-off-by: Sasha Finkelstein
---
drivers/gpu/drm/Kconfig| 2 +
drivers/gpu/drm/Makefile | 1
On 15/11/2024 10:35, Philipp Stanner wrote:
The various objects defined and used by the GPU scheduler are currently
not fully documented. Furthermore, there is no documentation yet
informing drivers about how they should handle timeouts.
Add documentation describing the scheduler's objects and
Atm when the connector is added to the drm_mode_config::connector_list,
the connector may not be fully initialized yet. This is not a problem
for user space, which will see the connector only after it's registered
later, it could be a problem for in-kernel users looking up connectors
via the above
After a connector is added to the drm_mode_config::connector_list, it's
visible to any in-kernel users looking up connectors via the above list.
Make sure that the connector is properly initialized before such
look-ups.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915
Follow the canonical way in intel_dp_mst.c, referencing a connector only
via a struct intel_connector pointer and naming this pointer 'connector'
instead of 'intel_connector', the only exception being the casting of
a drm_connector function parameter pointer to intel_connector, calling
the drm_conn
After an error during adding an MST connector the MST port and the
intel_connector object could be leaked, fix this up.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
dif
This patchset is v2 of [1], without the first patch which is already
merged, adding Rodrigo's R-bs and addressing Jani's review comments in
patch 1 of this patchset and the newly added patch 4.
Cc: Rodrigo Vivi
Cc: Jani Nikula
[1] https://lore.kernel.org/all/20241115164159.1081675-1-imre.d...@i
On Tue, Nov 26, 2024 at 12:07:10AM +0200, Dmitry Baryshkov wrote:
> On Mon, 25 Nov 2024 at 15:17, Maxime Ripard wrote:
> >
> > On Fri, Nov 22, 2024 at 03:32:57PM +0200, Dmitry Baryshkov wrote:
> > > On Tue, Nov 12, 2024 at 03:05:37AM +0100, Marek Vasut wrote:
> > > > The Pixel PLL is not very capa
On 26/11/2024 16:24, Akhil P Oommen wrote:
>> No, this makes everything total mess. Why xo now is allowed to be first
>> clock?
>>
>> Drop and explain in commit msg why other devices now get smmu clock.
>
> I thought it was okay to make this list a bit flexible. Btw, the other
> existing clock-nam
On Tue, Nov 26, 2024 at 12:48:20AM +0100, Marek Vasut wrote:
> On 11/22/24 2:32 PM, Dmitry Baryshkov wrote:
> > On Tue, Nov 12, 2024 at 03:05:37AM +0100, Marek Vasut wrote:
> > > The Pixel PLL is not very capable and may come up with wildly inaccurate
> > > clock. Since DPI panels are often toleran
On Tue, Nov 26, 2024 at 02:24:12PM +0200, Jani Nikula wrote:
> On Tue, 26 Nov 2024, Maxime Ripard wrote:
> > On Tue, Nov 26, 2024 at 12:16:34PM +0200, Jani Nikula wrote:
> >> On Mon, 25 Nov 2024, Maxime Ripard wrote:
> >> > I wonder about the naming though (and prototype). I doesn't really
> >> >
On 11/26/2024 7:42 PM, Krzysztof Kozlowski wrote:
> On 26/11/2024 15:06, Akhil P Oommen wrote:
>> A612 GPU requires an additional smmu_vote clock. Update the bindings to
>> reflect this.
>>
>> Signed-off-by: Akhil P Oommen
>> ---
>> .../devicetree/bindings/display/msm/gpu.yaml | 28
>>
Hi,
Am Mittwoch, 6. November 2024, 14:54:39 CET schrieb neil.armstr...@linaro.org:
> > +#define UPDATE(v, h, l)(((v) << (l)) & GENMASK((h),
> > (l)))
>
> I'm not super fan of this macro, overall I thinkg you should switch to
> regmap and make use of regmap_update_bits and dro
On Tue, Nov 26, 2024 at 10:11:51PM +0800, Sandor Yu wrote:
> Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ.
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> DisplayPort or HDMI PHY mode is configured in the driver.
>
> Signe
On 11/26/2024 7:36 PM, Akhil P Oommen wrote:
> A612 GPU requires an additional smmu_vote clock. Update the bindings to
> reflect this.
>
> Signed-off-by: Akhil P Oommen
> ---
> .../devicetree/bindings/display/msm/gpu.yaml | 28
> --
> 1 file changed, 16 insertions(+),
On Tue, Nov 26, 2024 at 07:36:48PM +0530, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Add gpu and gmu nodes for qcs615 chipset.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 86
>
> 1 file chan
On Tue, Nov 26, 2024 at 07:36:49PM +0530, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Enable GPU for qcs615-ride platform and provide path for zap
> shader.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> ---
> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8
> 1 file cha
Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ.
Cadence HDP-TX PHY could be put in either DP mode or
HDMI mode base on the configuration chosen.
DisplayPort or HDMI PHY mode is configured in the driver.
Signed-off-by: Sandor Yu
Signed-off-by: Alexander Stein
---
v18->v19:
- Simp
This series adds support for Adreno 612 to QCS615 chipset's devicetree.
DRM driver's support was posted earlier and can be found here:
https://patchwork.freedesktop.org/patch/626066/
Patch#1 is for Rob Clark and the other 2 for Bjorn
Signed-off-by: Akhil P Oommen
---
Akhil P Oommen (1):
+0xb8/0xd0
[8.711206] Modules linked in:
[8.714285] CPU: 1 UID: 0 PID: 49 Comm: kworker/1:1 Tainted: GW
6.12.0-next-20241126 #1
[8.723790] Tainted: [W]=WARN
[8.726781] Hardware name: Google Shuboz/Shuboz, BIOS
Google_Shuboz.13434.780.2022_10_13_1418 09/12/2022
From: Alexander Stein
This adds DCSS + MHDP + MHDP PHY nodes. PHY mode (DP/HDMI) is selected
by the connector type connected to mhdp port@1 endpoint.
Signed-off-by: Alexander Stein
---
v17->v19:
*No change
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 68 +++
1 file changed
From: Alexander Stein
Add HDMI connector and connect it to MHDP output. Enable peripherals
for HDMI output.
Signed-off-by: Alexander Stein
---
v18->v19:
- Move property data-lanes to endpoint of port@1
v17->v18:
- replace lane-mapping with data-lanes
.../dts/freescale/imx8mq-tqma8mq-mba8mx.d
Add bindings for Freescale iMX8MQ DP and HDMI PHY.
Signed-off-by: Sandor Yu
Reviewed-by: Rob Herring
---
v9->v18:
*No change.
.../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml | 51 +++
1 file changed, 51 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/fsl
Add a new DRM DisplayPort and HDMI bridge driver for Candence MHDP8501
used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
standards according embedded Firmware running in the uCPU.
For iMX8MQ SOC, the DisplayPort/HDMI FW was loaded and activated by
SOC's ROM code. Bootload binary incl
Add bindings for Cadence MHDP8501 DisplayPort/HDMI bridge.
Signed-off-by: Sandor Yu
---
v18->v19:
- move data-lanes property to endpoint of port@1
v17->v18:
- remove lane-mapping and replace it with data-lanes
- remove r-b tag as property changed.
v16->v17:
- Add lane-mapping property
v9->v16:
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
Signed-off-by: Sandor Yu
Reviewed-by: D
Mailbox access functions in MHDP8546 will be share to other MHDP driver
and Cadence HDP-TX HDMI/DP PHY drivers.
Create a new MHDP helper driver and move all mailbox access functions into.
According the mailbox access sequence and type of security.
Six mailbox access API functions are introduced.
T
The patch set initial support Cadence MHDP8501(HDMI/DP) DRM bridge
driver and Cadence HDP-TX PHY(HDMI/DP) driver for Freescale i.MX8MQ.
The patch set compose of DRM bridge drivers and PHY driver.
Both of them need by patch #1 and #2 to pass build.
DRM bridges driver patches:
#1: drm: bridge: C
>
> On Tue, Nov 05, 2024 at 02:05:51PM +, Sandor Yu wrote:
> > >
> > > On Tue, Oct 29, 2024 at 02:02:14PM +0800, Sandor Yu wrote:
> > > > Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ.
> > > >
> > > > Cadence HDP-TX PHY could be put in either DP mode or HDMI mode
> > > > bas
On 26/11/2024 15:06, Akhil P Oommen wrote:
> A612 GPU requires an additional smmu_vote clock. Update the bindings to
> reflect this.
>
> Signed-off-by: Akhil P Oommen
> ---
> .../devicetree/bindings/display/msm/gpu.yaml | 28
> --
> 1 file changed, 16 insertions(+), 12
>
>
> On 5 November 2024 14:05:51 GMT, Sandor Yu wrote:
> >>
> >> On Tue, Oct 29, 2024 at 02:02:14PM +0800, Sandor Yu wrote:
> >> > Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ.
> >> >
> >> > Cadence HDP-TX PHY could be put in either DP mode or HDMI mode
> base
> >> > on the co
From: Jie Zhang
Enable GPU for qcs615-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
b/arch
From: Jie Zhang
Add gpu and gmu nodes for qcs615 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 86
1 file changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi
b/arch/arm6
A612 GPU requires an additional smmu_vote clock. Update the bindings to
reflect this.
Signed-off-by: Akhil P Oommen
---
.../devicetree/bindings/display/msm/gpu.yaml | 28 --
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/binding
On 11/20/24 08:21, Pei Xiao wrote:
> Sparse complains about incorrect type in argument 1.
> expected void const volatile __iomem *ptr but got void *.
> so modify mixer_dbg_mxn's addr parameter.
>
> Reported-by: kernel test robot
> Closes:
> https://lore.kernel.org/oe-kbuild-all/202411191809.6v
Hi,
Am Mittwoch, 6. November 2024, 14:33:25 CET schrieb Diederik de Haas:
> > +#define IPI_DEPTH_5_6_5_BITS 0x02
> > +#define IPI_DEPTH_6_BITS 0x03
> > +#define IPI_DEPTH_8_BITS 0x05
> > +#define IPI_DEPTH_10_BITS 0x06
>
> Possibly dumb remark (sorry):
>
Hi Maxime,
On Tue, Nov 26, 2024 at 08:36:01AM +0100, Sean Nyekjaer wrote:
> Hi Maxime,
>
[...]
> >
> > We probably need some kunit tests here too.
>
> Good idea, will be my first :)
>
Would something like this work?
diff --git a/drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c
b/drivers
Add documentation to explain properties of the exposed hardware
1D LUT blocks, its identification and computation of the LUT samples
based on the number of samples, their distribution and precison.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
Documentation/gpu/rfc/color_p
From: Chaitanya Kumar Borah
Expose color pipeline and add ability to program it.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_uni
Extract the LUT and program plane post csc registers.
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 109 +
1 file changed, 109 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers
Add callback for programming Pre-CSC LUT for TGL and beyond
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 88 ++
1 file changed, 88 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/dr
Add macros to define Plane Post CSC registers
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
.../i915/display/skl_universal_plane_regs.h | 73 +++
1 file changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
b/dri
From: Chaitanya Kumar Borah
Add framework that will help in loading LUT to Pre/Post CSC color
blocks.
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 27 ++
drivers/gpu/drm/i915/display/intel_color.h | 2 ++
Add macros to define Plane Degamma registers
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
.../i915/display/skl_universal_plane_regs.h | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
b/driv
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