On Tue, 2024-11-19 at 14:40 +0100, Christian König wrote:
> Am 15.11.24 um 16:01 schrieb Thomas Hellström:
> > Provide a standalone shmem backup implementation.
> > Given the ttm_backup interface, this could
> > later on be extended to providing other backup
> > implementation than shmem, with one
On 20/11/2024 07:18, keith zhao wrote:
> + /* Unmute hotplug interrupt */
> + hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1));
> +
> + ret = devm_request_threaded_irq(hdmi->dev, irq, inno_hdmi_hardirq,
> + inno_hdmi_irq, IRQF_S
On Tue, Nov 19, 2024 at 10:25:10AM +0530, Ghimiray, Himal Prasad wrote:
> On 15-11-2024 10:37, Raag Jadav wrote:
> > This was previously attempted as xe specific reset uevent but dropped
> > in commit 77a0d4d1cea2 ("drm/xe/uapi: Remove reset uevent for now")
> > as part of refactoring.
> >
> > Now
> -Original Message-
> From: Intel-xe On Behalf Of Arun R
> Murthy
> Sent: Tuesday, November 19, 2024 4:15 PM
> To: intel...@lists.freedesktop.org; intel-...@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org
> Cc: Murthy, Arun R
> Subject: [PATCHv2 1/8] drm/i915/histogram: Defin
Each GPU OPP requires a specific peak DDR bandwidth, let's add
those to each OPP and also the related interconnect path.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi
b
Many a times images are blurred or upscaled content is also not as
crisp as original rendered image. Traditional sharpening techniques often
apply a uniform level of enhancement across entire image, which sometimes
result in over-sharpening of some areas and potential loss of natural detail
This commit introduces plane functions and helper functions
for the VS DRM subsystem, enhancing support for managing
display planes and their configurations.
Signed-off-by: keith zhao
---
drivers/gpu/drm/verisilicon/Makefile | 3 +-
drivers/gpu/drm/verisilicon/vs_plane.c | 358 ++
This commit adds CRTC functions and helper functions
to the VS DRM subsystem,
enhancing support for display management and configurations.
Signed-off-by: keith zhao
---
drivers/gpu/drm/verisilicon/Makefile | 3 +-
drivers/gpu/drm/verisilicon/vs_crtc.c | 241 ++
drivers
Add the display DT nodes in Starfive JH7110 soc-specific DT file.
Signed-off-by: keith zhao
---
.../boot/dts/starfive/jh7110-common.dtsi | 125 ++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 41 ++
2 files changed, 166 insertions(+)
diff --git a/arch/riscv/boot/dts
On 11/20/24, Marek Vasut wrote:
> On 11/19/24 9:18 AM, Ying Liu wrote:
>
> [...]
>
> >> The TC9595 can drive an DP output, for that the clock which have to be
> >> set on the LCDIF cannot be predicted, as that information comes from the
> >> monitor EDID/DPCD. That is why the LCDIF has to be able
move rochchip inno hdmi connector to a newly created directory named
inno-hdmi.c, and rename rockchip/inno_hdmi.c to
rockchip/inno_hdmi-rockchip.c
This patch refines the Innosilicon HDMI architecture by abstracting
the existing connector into a bridge architecture.
The drm_bridge_connector_init fu
The VS DRM master driver for the JH7110 System on Chip (SoC),
along with the addition of a DMA GEM (Graphics Execution Manager) driver
Signed-off-by: keith zhao
---
drivers/gpu/drm/verisilicon/Makefile | 3 +-
drivers/gpu/drm/verisilicon/vs_drv.c | 777 +++
2 files chan
This commit adds the Innosilicon HDMI driver,
designed to interface with the VS display controller.
The driver leverages the APIs provided by the Innosilicon HDMI bridge.
Signed-off-by: keith zhao
---
drivers/gpu/drm/verisilicon/Kconfig | 19 +
drivers/gpu/drm/verisilicon/Makefile
- Added bindings to support the display subsystem on the JH7110 SoC.
- Included the DC8200 display controller and Inno HDMI controller.
- Created innosilicon,inno-hdmi.yaml schema containing common properties
for the Inno DesignWare HDMI TX controller.
This isn't a full device tree binding sp
Verisilicon/DC8200 display controller IP has 2 display pipes and each
pipe support a primary plane and a cursor plane .
In addition, there are 4 overlay planes as 2 display pipes common resources.
The first display pipe is bound to the inno HDMI encoder.
The second display pipe is bound to Inter
This commit introduces hardware-based APIs for
the VS DRM related to the DC8200
Signed-off-by: keith zhao
---
MAINTAINERS|1 +
drivers/gpu/drm/Kconfig|2 +
drivers/gpu/drm/Makefile |1 +
drivers/gpu/drm/verisilicon/Kconfig
This commit adds a base API for configuring VS modes,
which will streamline the setup and management of display modes
in the VS DRM subsystem.
In this implementation, we are using drm_atomic_helper_commit_tail_rpm()
instead of drm_atomic_helper_commit_tail() to ensure that
we skip planes related t
Load the lut values during pipe enable.
v2: Add the display version check
v3: Fix build issue
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++
drivers/gpu/drm/i915/display/intel_display.c | 6 ++
.../gpu/drm/i915/display/intel_display_types.h
Add new registers and related bits. Compute the strength
value and tap value based on display mode.
v2: Replace i915/dev_priv with display[Jani]
v3: Create separate file for defining register[Jani]
Add display->drm in debug prints[Jani]
v4: Rebase
v5: Fix build issue
Signed-off-by: Nemesa Gar
Introduces the new crtc property "SHARPNESS_STRENGTH" that allows
the user to set the intensity so as to get the sharpness effect.
The value of this property can be set from 0-255.
It is useful in scenario when the output is blurry and user
want to sharpen the pixels. User can increase/decrease the
The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for different
tap value/win size. These values are normalized by taking the
sum of all values and then dividing each value with a sum.
As only second scaler can be used for sharpness check if it
is available and also check if panel fitting is also not enabled,
then set the sharpness. Panel fitting will have the preference
over sharpness property.
v2: Add the panel fitting check before enabling sharpness
v3: Reframe commit message
On Tue, Nov 19, 2024 at 05:45:27PM +0100, Thomas Hellström wrote:
> On Tue, 2024-10-15 at 20:25 -0700, Matthew Brost wrote:
> > Add functions which migrate to / from VRAM accepting a single DPA
> > argument (VRAM) and array of dma addresses (SRAM).
> >
> > v2:
> > - Don't unlock job_mutex in erro
The host_node pointer was assigned and freed in adv7533_parse_dt(), and
later, adv7533_attach_dsi() uses the same. Fix this use-after-free issue
by dropping of_node_put() in adv7533_parse_dt() and calling of_node_put()
in error path of probe() and also in the remove().
Fixes: 1e4d58cd7f88 ("drm/br
This patch series aims to fix 2 bugs in the ADV7535 driver
1) use-after-free bug in adv7533_attach_dsi()
2) Drop unsupported single lane.
Changes in v7:
- Dropped check for host_node as of_node_put() is a no-op when called
with a NULL pointer.
- Added Rb tag from Laurent for patch#1.
Change
mtk_crtc_finish_page_flip() is used to notify userspace that a
page flip has been completed, allowing userspace to free the frame
buffer of the last frame and commit the next frame.
In MediaTek's hardware design for configuring display hardware by using
GCE, `DRM_EVENT_FLIP_COMPLETE` should be not
On 10/16/24 6:25 AM, Matthew Brost wrote:
+/**
+ * xe_devm_add: Remap and provide memmap backing for device memory
+ * @tile: tile that the memory region belongs to
+ * @mr: memory region to remap
+ *
+ * This remap device memory to host physical address space and create
+ * struct page to bac
>> The issue of "internal display fails to resume properly (switching VT brings
>> it back)"
>> also affects sc7180 platform during some resumes. Do you see the issue
>> consistently
>> during every resume?
>
> Yes, it happens on every suspend cycle here.
>
> I didn't notice the issue initially
On 10/16/24 6:24 AM, Matthew Brost wrote:
+
+/**
+ * drm_gpusvm_get_devmem_page - Get a reference to a device memory page
+ * @page: Pointer to the page
+ * @zdd: Pointer to the GPU SVM zone device data
+ *
+ * This function associates the given page with the specified GPU SVM zone
+ * device
Most compositors are using a change in EDID as an indicator to
refresh their connector information on hotplug regardless of whether the
connector was previously connected. Originally the hotplug_mode_update
property was supposed to provide a hint to userspace to always refresh
connector info on hot
Hi all,
On Thu, 10 Oct 2024 15:38:55 +1100 Stephen Rothwell
wrote:
>
> On Tue, 1 Oct 2024 13:44:23 +1000 Stephen Rothwell
> wrote:
> >
> > After merging the random tree, today's linux-next build (x86_64
> > allmodconfig) failed like this:
> >
> >
> > Caused by commit
> >
> > 38d1a9d296c8
Quoting Dmitry Baryshkov (2024-11-15 09:17:15)
> On Mon, Nov 11, 2024 at 06:16:27PM -0800, Stephen Boyd wrote:
> > Quoting Dmitry Baryshkov (2024-11-08 23:05:18)
> > > On Thu, Nov 07, 2024 at 04:28:24PM -0800, Stephen Boyd wrote:
> > > > Quoting Dmitry Baryshkov (2024-10-31 15:54:49)
> > > > > On T
Hi Biju,
Thank you for the patch.
On Tue, Nov 19, 2024 at 01:10:03PM +, Biju Das wrote:
> The host_node pointer was assigned and freed in adv7533_parse_dt(), and
> later, adv7533_attach_dsi() uses the same. Fix this use-after-free issue
> by dropping of_node_put() in adv7533_parse_dt() and ca
On Tue, Nov 19, 2024 at 04:31:05PM +0100, Thomas Hellström wrote:
> On Tue, 2024-10-15 at 20:25 -0700, Matthew Brost wrote:
> > Add unbind to SVM garbage collector. To facilitate add unbind support
> > function to VM layer which unbinds a SVM range. Also teach PY layer
> > to
> > understand unbinds
On Tue, Nov 19, 2024 at 05:33:11PM +0100, Thomas Hellström wrote:
> On Tue, 2024-10-15 at 20:25 -0700, Matthew Brost wrote:
> > uAPI is designed with the the use case that only mapping a BO to a
> > malloc'd address will unbind a system allocator VMA. Thus it doesn't
> > make tons of sense to allow
On Fri, Aug 30, 2024 at 07:36:32PM +0200, György Kurucz wrote:
> For context, I have a Lenovo Yoga Slim 7x laptop, and was having issues
> with the display staying black after sleep. As a workaround, I could
> switch to a different VT and back.
>
> > [ 1185.831970] [dpu error]connector not conn
Commit 498893bd596e ("drm/panthor: Simplify FW fast reset path") forgot
to copy the definition of glb_iface when it move one line of code.
Fixes: Commit 498893bd596e ("drm/panthor: Simplify FW fast reset path")
Signed-off-by: Liviu Dudau
---
drivers/gpu/drm/panthor/panthor_fw.c | 1 +
1 file cha
On 11/19/24 9:18 AM, Ying Liu wrote:
[...]
The TC9595 can drive an DP output, for that the clock which have to be
set on the LCDIF cannot be predicted, as that information comes from the
monitor EDID/DPCD. That is why the LCDIF has to be able to configure the
Video PLL1 clock to accurate clock
As per [1] and [2], ADV7535/7533 supports only 2-, 3-, or 4-lane. Drop
unsupported 1-lane.
[1]
https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7535.pdf
[2]
https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7533.pdf
Fixes: 1e4d58cd7f88 ("drm/bridge: ad
On Tue, Nov 19, 2024 at 04:29:53PM +, Liviu Dudau wrote:
> On Mon, Nov 18, 2024 at 08:08:16AM -0700, Nathan Chancellor wrote:
> > On Thu, Oct 31, 2024 at 02:41:38PM +0100, Maarten Lankhorst wrote:
> > > Cristian Ciocaltea (3):
> > > drm/rockchip: Add basic RK3588 HDMI output support
> >
On Tue, 2024-10-15 at 20:25 -0700, Matthew Brost wrote:
> Add drm_gpusvm_devmem to xe_bo. Required to enable SVM migrations.
>
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/drm/xe/xe_bo_types.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_bo_types.
The Adreno GMU Management Unit (GMU) can also scale the DDR Bandwidth
along the Frequency and Power Domain level, until now we left the OPP
core scale the OPP bandwidth via the interconnect path.
In order to enable bandwidth voting via the GPU Management
Unit (GMU), when an opp is set by devfreq w
On 11/11/24 13:41, Dave Airlie wrote:
From: Dave Airlie
eb284f4b3781 drm/nouveau/dp: Honor GSP link training retry timeouts
tried to fix a problem with panel retires, however it appears
the auxch also needs the same treatment, so add the same retry
wrapper around it.
This fixes some eDP pane
The Adreno GMU Management Unit (GMU) can also scale DDR Bandwidth along
the Frequency and Power Domain level, but by default we leave the
OPP core scale the interconnect ddr path.
In order to calculate vote values used by the GPU Management
Unit (GMU), we need to parse all the possible OPP Bandwid
When requesting a DDR bandwidth level along a GPU frequency
level via the GMU, we can also specify the bus bandwidth usage in a 16bit
quantitized value.
For now simply request the maximum bus usage.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 11 +++
driver
Add and implement the dev_pm_opp_get_bw() to retrieve
the OPP's bandwidth in the same way as the dev_pm_opp_get_voltage()
helper.
Retrieving bandwidth is required in the case of the Adreno GPU
where the GPU Management Unit can handle the Bandwidth scaling.
The helper can get the peak or average b
In case of error after a amdgpu_gfx_rlc_enter_safe_mode() call, it is not
balanced by a corresponding amdgpu_gfx_rlc_exit_safe_mode() call.
Add the missing call.
Fixes: c6a6e2db9945 ("drm/amdgpu: Redo XGMI reset synchronization.")
Signed-off-by: Christophe JAILLET
---
Compile tested only.
This
In case of error after a amdgpu_gfx_rlc_enter_safe_mode() call, it is not
balanced by a corresponding amdgpu_gfx_rlc_exit_safe_mode() call.
Add the missing call.
Fixes: 9b7b8154cdb8 ("drm/amd/powerplay: added didt support for vega10")
Signed-off-by: Christophe JAILLET
---
*Not* even compile test
On 11/18/24 7:02 AM, Matt Coster wrote:
The TI k3-j721s2 platform has a bug relating to cache snooping on the AXI
Well we don't really know it is the bug on our side until we root cause it..
Anyway, why do need such a complex work around here? GEM buffer objects
only need to be coherent, cache
On Fri, Oct 18, 2024 at 5:01 PM Maaz Mombasawala
wrote:
>
> A userspace may create a userspace managed surface but not destroy it,
> add hw_destroy function for userspace surfaces so that vmwgfx records the
> destroy command and submits it when the userspace context is destroyed.
>
> Signed-off-by
On Fri, Oct 18, 2024 at 5:01 PM Maaz Mombasawala
wrote:
>
> The kernel currently exposes both mobs and surfaces to userspace through
> ioctls. We would like to move to a model where kernel would only expose
> mobs and have userspace manage surfaces. This would simplify kernel paths
> for surfaces
Hi Laurent,
Thank you for the feedback.
> -Original Message-
> From: Laurent Pinchart
> Sent: 19 November 2024 19:03
> Subject: Re: [PATCH v6 1/3] drm: adv7511: Fix use-after-free in
> adv7533_attach_dsi()
>
> Hi Biju,
>
> Thank you for the patch.
>
> On Tue, Nov 19, 2024 at 06:44:14
Hi Biju,
Thank you for the patch.
On Tue, Nov 19, 2024 at 06:44:14PM +, Biju Das wrote:
> The host_node pointer was assigned and freed in adv7533_parse_dt(), and
> later, adv7533_attach_dsi() uses the same. Fix this use-after-free issue
> by dropping of_node_put() in adv7533_parse_dt() and ca
On Tue, Nov 19, 2024 at 7:50 AM Biju Das wrote:
>
> As per [1] and [2], ADV7535/7533 supports only 2-, 3-, or 4-lane. Drop
> unsupported 1-lane.
>
> [1]
> https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7535.pdf
> [2]
> https://www.analog.com/media/en/technical-documentati
On Tue, 2024-10-15 at 20:25 -0700, Matthew Brost wrote:
> uAPI is designed with the the use case that only mapping a BO to a
> malloc'd address will unbind a system allocator VMA. Thus it doesn't
> make tons of sense to allow a system allocator VMA unbind if the GPU
> has
> bindings in the range be
As per [1] and [2], ADV7535/7533 supports only 2-, 3-, or 4-lane. Drop
unsupported 1-lane.
[1]
https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7535.pdf
[2]
https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7533.pdf
Fixes: 1e4d58cd7f88 ("drm/bridge: ad
The host_node pointer was assigned and freed in adv7533_parse_dt(), and
later, adv7533_attach_dsi() uses the same. Fix this use-after-free issue
by dropping of_node_put() in adv7533_parse_dt() and calling of_node_put()
in error path of probe() and also in the remove().
Fixes: 1e4d58cd7f88 ("drm/br
As per [1] and [2], ADV7535/7533 supports only 2-, 3-, or 4-lane. Drop
unsupported 1-lane from bindings.
[1]
https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7535.pdf
[2]
https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7533.pdf
Fixes: 1e4d58cd7f88 ("
This patch series aims to fix 2 bugs in the ADV7535 driver
1) use-after-free bug in adv7533_attach_dsi()
2) Drop unsupported single lane.
Changes in v6:
- Fixed memory leak by adding goto stattement in error path of
adv7511_init_regulators().
- Added Rb tag from Adam for patch#3.
Changes in
Hi Laurent,
> -Original Message-
> From: Laurent Pinchart
> Sent: 19 November 2024 16:28
> Subject: Re: [PATCH v5 1/3] drm: adv7511: Fix use-after-free in
> adv7533_attach_dsi()
>
> Hi Biju,
>
> Thank you for the patch.
>
> On Tue, Nov 19, 2024 at 01:10:03PM +, Biju Das wrote:
> >
Now all the DDR bandwidth voting via the GPU Management Unit (GMU)
is in place, declare the Bus Control Modules (BCMs) and the
corresponding parameters in the GPU info struct and add the
GMU_BW_VOTE feature bit to enable it.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/adreno/a6xx_catal
The Adreno GMU Management Unit (GMU) can also vote for DDR Bandwidth
along the Frequency and Power Domain level, but by default we leave the
OPP core scale the interconnect ddr path.
While scaling the interconnect path was sufficient, newer GPUs
like the A750 requires specific vote parameters and
Each GPU OPP requires a specific peak DDR bandwidth, let's add
those to each OPP and also the related interconnect path.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi
The Adreno GPU Management Unit (GMU) can also scale the ddr
bandwidth along the frequency and power domain level, but for
now we statically fill the bw_table with values from the
downstream driver.
Only the first entry is used, which is a disable vote, so we
currently rely on scaling via the linux
Now the features defines have the right name, introduce a features
bitfield and move the features defines in it, fixing all code checking
for them.
No functional changes intended.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 34 +++---
d
Half of the current "Quirks" are in fact features, so rename
the defines with FEAT instead of QUIRK.
They will be moved in a separate bitfield in a second time.
No functional changes.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 62 +++-
The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
along the Frequency and Power Domain level, but by default we leave the
OPP core vote for the interconnect ddr path.
While scaling via the interconnect path was sufficient, newer GPUs
like the A750 requires specific vote paremet
Hi Arun,
On Tue, 19 Nov 2024 at 14:39, Murthy, Arun R wrote:
> > On Tue, 19 Nov 2024 at 10:55, Arun R Murthy
> > wrote:
> > > The corresponding mutter changes to enable/disable histogram, read the
> > > histogram data, communicate with the library and write the enhanced
> > > data back to the KM
On Sat, 16 Nov 2024 20:22:32 +0200, Cristian Ciocaltea wrote:
> On RK3588, HDMI PHY PLL can be used as an alternative and more accurate
> pixel clock source for VOP2 video ports 0, 1 and 2.
>
> Document the optional PLL clock properties corresponding to the two HDMI
> PHYs available on the SoC.
On Tue, 2024-10-15 at 20:25 -0700, Matthew Brost wrote:
> Add SVM device memory mirroring which enables device pages for
> migration.
>
> TODO: Hide this behind Kconfig
>
> Signed-off-by: Niranjana Vishwanathapura
> Signed-off-by: Oak Zeng
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/dr
On Tue, 2024-10-15 at 20:25 -0700, Matthew Brost wrote:
> Add functions which migrate to / from VRAM accepting a single DPA
> argument (VRAM) and array of dma addresses (SRAM).
>
> v2:
> - Don't unlock job_mutex in error path of xe_migrate_vram
>
> Signed-off-by: Oak Zeng
> Signed-off-by: Matth
On Mon, Nov 18, 2024 at 08:08:16AM -0700, Nathan Chancellor wrote:
> On Thu, Oct 31, 2024 at 02:41:38PM +0100, Maarten Lankhorst wrote:
> > Cristian Ciocaltea (3):
> > drm/rockchip: Add basic RK3588 HDMI output support
>
> Can someone please apply [1] to resolve a link time failure seen with
On Tue, 2024-10-15 at 20:25 -0700, Matthew Brost wrote:
> Support for system allocator bindings in SRAM fully in place, enable
> the
> implementation.
>
> Signed-off-by: Matthew Brost
Reviewed-by: Thomas Hellström
> ---
> drivers/gpu/drm/xe/xe_vm.c | 6 --
> 1 file changed, 6 deletions(-)
On Tue, Nov 12, 2024 at 3:15 PM Akhil P Oommen wrote:
>
> On 11/11/2024 8:38 PM, Rob Clark wrote:
> > On Sun, Nov 10, 2024 at 9:31 AM Bjorn Andersson
> > wrote:
> >>
> >> Support for per-process page tables requires the SMMU aparture to be
> >> setup such that the GPU can make updates with the SM
On Tue, 2024-10-15 at 20:24 -0700, Matthew Brost wrote:
> Add DRM_GPUVA_OP_USER which allows driver to define their own gpuvm
> ops.
>
> Cc: Danilo Krummrich
> Signed-off-by: Matthew Brost
> ---
> include/drm/drm_gpuvm.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/drm
On Tue, Nov 19, 2024 at 02:57:56PM +0100, Thomas Hellström wrote:
> On Tue, 2024-10-15 at 20:24 -0700, Matthew Brost wrote:
> > Add DRM_GPUVA_OP_USER which allows driver to define their own gpuvm
> > ops.
> >
> > Cc: Danilo Krummrich
> > Signed-off-by: Matthew Brost
> > ---
> > include/drm/drm_
On Tue, Nov 19, 2024 at 01:15:12PM +0100, Thomas Hellström wrote:
> On Tue, 2024-10-15 at 20:24 -0700, Matthew Brost wrote:
> > From: Thomas Hellström
> >
> > Useful for SVM ranges in SRAM and programing page tables.
>
> We should look at providing a better commit message.
>
Yes, this is prett
The documentation of drm_sched_entity_flush() states that the function
shall - always - return the remaining timeout time in jiffies.
However, that is not what the function actually does; in one of its if
branches it simply returns the unchanged timeout value.
Furthermore, the used function wait_
On 19/11/2024 13:39, Pierre-Eric Pelloux-Prayer wrote:
Le 14/11/2024 à 13:01, Tvrtko Ursulin a écrit :
On 14/11/2024 10:01, Pierre-Eric Pelloux-Prayer wrote:
This will be used in a later commit to trace the drm client_id in
some of the gpu_scheduler trace events.
I wonder if it would be
On Mon, Nov 18, 2024 at 02:44:58PM +0100, Thomas Hellström wrote:
> On Tue, 2024-10-15 at 20:24 -0700, Matthew Brost wrote:
> > Add the DRM_XE_VM_BIND_FLAG_SYSTEM_ALLOCATOR flag, which is used to
> > create unpopulated virtual memory areas (VMAs) without memory backing
> > or
> > GPU page tables. T
On Tue, 2024-11-19 at 15:27 +0100, Christian König wrote:
> Am 19.11.24 um 14:41 schrieb Philipp Stanner:
> > drm_sched_entity_flush()'s documentation states that an error is
> > being
> > returned when "the process was killed". That is not what the
> > function
> > actually does.
> >
> > Furtherm
On Tue, 2024-10-15 at 20:25 -0700, Matthew Brost wrote:
> Add unbind to SVM garbage collector. To facilitate add unbind support
> function to VM layer which unbinds a SVM range. Also teach PY layer
> to
> understand unbinds of SVM ranges.
>
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/drm/
On Mon, Nov 18, 2024 at 06:35:30PM +0100, Louis Chauvet wrote:
> On 18/11/24 - 18:24, José Expósito wrote:
> > On Mon, Nov 18, 2024 at 06:17:11PM +0100, Louis Chauvet wrote:
> > > On 18/11/24 - 18:10, José Expósito wrote:
> > > > > Introduce the usage of block_h/block_w to compute the offset and th
Hi Johan,
> I'm seeing the same issue as György on the x1e80100 CRD and Lenovo
> ThinkPad T14s. Without this patch, the internal display fails to resume
> properly (switching VT brings it back) and the following errors are
> logged:
>
> [dpu error]connector not connected 3
> [drm:drm_
On Tue, Nov 19, 2024 at 02:56:57PM +0100, Louis Chauvet wrote:
> On 19/11/24 - 14:34, Louis Chauvet wrote:
> > VKMS currently supports only one CRTC, so it make no sense to have this
> > index configurable. To avoid issues, replace this hardcoded index by
> > drm_crtc_mask when applicable.
> >
> >
On Tue, 2024-10-15 at 20:25 -0700, Matthew Brost wrote:
> Add basic SVM garbage collector which can destroy an SVM range upon
> an
> MMU UNMAP event.
>
> v2:
> - Flush garbage collector in xe_svm_close
>
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/drm/xe/xe_svm.c | 87
> +++
> On Tue, 19 Nov 2024 at 10:55, Arun R Murthy
> wrote:
> > The corresponding mutter changes to enable/disable histogram, read the
> > histogram data, communicate with the library and write the enhanced
> > data back to the KMD is also pushed for review at
> > https://gitlab.gnome.org/GNOME/mutter/
Am 19.11.24 um 14:41 schrieb Philipp Stanner:
drm_sched_entity_flush()'s documentation states that an error is being
returned when "the process was killed". That is not what the function
actually does.
Furthermore, it contains an inprecise statement about how the function
is part of a convenienc
On Tue, 2024-10-15 at 20:25 -0700, Matthew Brost wrote:
> Add (re)bind to SVM page fault handler. To facilitate add support
> function to VM layer which (re)binds a SVM range. Also teach PT layer
> to
> understand (re)binds of SVM ranges.
>
> v2:
> - Don't assert BO lock held for range binds
> -
Enable access to internal non-volatile memory on
DGFX devices via a child device.
The nvm child device is exposed via auxiliary bus.
CC: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Co-developed-by: Tomas Winkler
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/
Enable access to internal non-volatile memory on DGFX
with GSC/CSC devices via a child device.
The nvm child device is exposed via auxiliary bus.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_device.c |
Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +
drivers/gpu/drm/x
Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/intel_nvm.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
di
Enable runtime PM in mtd driver to notify graphics driver that
whole card should be kept awake while nvm operations are
performed through this driver.
CC: Lucas De Marchi
Acked-by: Miquel Raynal
Signed-off-by: Alexander Usyskin
---
drivers/mtd/devices/mtd-intel-dg.c | 70 ++
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