If an error occurs after allocating resources based on which
"sharp,vcom-mode" is used, then these resources must be released, as
already done in the .remove() function.
Use 2 new devm_add_action_or_reset() for that and simplify code
accordingly.
Fixes: b8f9f21716fe ("drm/tiny: Add driver for Sha
Hi Raag,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-xe/drm-xe-next]
[also build test ERROR on drm-intel/for-linux-next
drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.12-rc4
next-20241025]
[If your patch is applied to the wrong git tree
Hi,
On 2024/10/7 18:17, Lucas Stach wrote:
@@ -104,21 +108,7 @@ static int etnaviv_iommu_map(struct etnaviv_iommu_context *context, u32 iova,
static void etnaviv_iommu_unmap(struct etnaviv_iommu_context *context, u32
iova,
struct sg_table *sgt, unsigned len)
In attempting to optimize fw_devlink runtime, I introduced numerous cycle
detection bugs by foregoing cycle detection logic under specific
conditions. Each fix has further narrowed the conditions for optimization.
It's time to give up on these optimization attempts and just run the cycle
detection
Horizontal Timing Control0 Register 1/2 (HTIM01/HTIM02) Register
bitfields description state "These bits must be multiple of even
pixel". It is not possible to simply align every bitfield to the
nearest even pixel, because that would unalign the line width and
cause visible distortion. Instead, att
On 10/24/24 11:55 AM, Herve Codina wrote:
In some cases observed during ESD tests, the TI SN65DSI83 cannot recover
from errors by itself. A full restart of the bridge is needed in those
cases to have the bridge output LVDS signals again.
I have seen the bridge being flaky sometimes, do you have
When information such as info->screen_base is not ready, calling
sh7760fb_free_mem() does not release memory correctly. Call
dma_free_coherent() instead.
Fixes: 4a25e41831ee ("video: sh7760fb: SH7760/SH7763 LCDC framebuffer driver")
Signed-off-by: Zhen Lei
---
drivers/video/fbdev/sh7760fb.c | 3
The Pixel PLL is not very capable and may come up with wildly inaccurate
clock. Since DPI panels are often tolerant to slightly higher pixel clock
without being operated outside of specification, calculate two Pixel PLL
settings for DPI output, one for desired output pixel clock and one for
output
The driver configures mostly Pixel PLL from the clock cached in
local copy of the mode. Make sure the driver uses adjusted mode
which contains the updated Pixel PLL settings negotiated in
tc_dpi_atomic_check()/tc_edp_atomic_check().
Signed-off-by: Marek Vasut
---
Cc: Andrzej Hajda
Cc: David Airl
Changes the leadtek-ltk050h3146w panel to use multi style functions for
improved error handling.
Signed-off-by: Tejas Vipin
---
.../drm/panel/panel-leadtek-ltk050h3146w.c| 345 +++---
1 file changed, 134 insertions(+), 211 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-le
Hello,
Unfortunately, I've found that the recent Anbernic RG35XX Plus uses a new
panel labeled `YLM-LBV0345001H-V2`, which is not compatible with the
`WL-355608-A8` in its initialization sequence.
Thus, the name `rg35xx-plus-panel` is no longer a unique identifier for the
panel.
I think it should
From: "Dr. David Alan Gilbert"
drm_i2c_encoder_commit(), drm_i2c_encoder_mode_set() and
drm_i2c_encoder_prepare() have been unused since 2016's
commit 7bc61cc5df80 ("drm/arcpgu: Accommodate adv7511 switch to DRM
bridge").
Remove them.
That change makes drm_i2c_encoder_dpms() unused.
Remove it.
modprobe ttm_device_test and then rmmod ttm_device_test, the following
memory leaks occurs:
The ttm->pages allocated in ttm_tt_init() is not freed after calling
ttm_tt_simple_create(), which cause the memory leak:
unreferenced object 0xff80caf27750 (size 8):
comm "kunit_try_
On 2024/10/25 22:33, Maxime Ripard wrote:
> On Wed, Oct 23, 2024 at 09:35:59AM +0800, Jinjie Ruan wrote:
>>
>>
>> On 2024/10/18 16:12, Jinjie Ruan wrote:
>>>
>>>
>>> On 2024/10/18 15:55, Maxime Ripard wrote:
Hi,
On Thu, Oct 17, 2024 at 02:31:21PM GMT, Jinjie Ruan wrote:
> Fix
On 25/10/2024 16:37, Zaeem Mohamed wrote:
[why]
Prevent index-out-of-bounds due to requiring cursor overlay when
plane_count is MAX_SURFACES.
Hi Zaeem,
Thanks for working on this fix.
[how]
Bounds check on plane_count when requiring overlay cursor.
I agree. Atomic check makes sense.
1)
Hi,
In v4, the approach to extending the BAR was changed to follow the
suggestion from Christian.
The control is now entirely on the driver side, with PCI subsystem
checking whether the resource fits during VF enabling.
I also added helpers to move between IOV / BAR # (suggested by Ilpo),
since th
From: Maxime Ripard
The new writeback controllers that can be found on the BCM2712 require
to have their horizontal and vertical size reduced by one.
Let's tie that behaviour to the compatible so we can support both the
new and old controllers.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave
On 10/24/2024 5:20 PM, Dmitry Baryshkov wrote:
Max upscale / downscale factors are constant between platforms. In
preparation to adding support for virtual planes and allocating SSPP
blocks on demand move max scaling factors out of the HW catalog and
handle them in the dpu_plane directly. If a
On 10/24/2024 5:20 PM, Dmitry Baryshkov wrote:
Split dpu_plane_atomic_check() function into two pieces:
dpu_plane_atomic_check_nosspp() performing generic checks on the pstate,
without touching the associated SSPP blocks,
and
dpu_plane_atomic_check_sspp(), which takes into account used SSPP
Current patch to prevent index-out-of-bounds when cursor plane is
required and plane_count is MAX_SURFACES. This check needs to occur in
dm_atomic_check where failing is safe. Need help with finding a better
location for the bounds check within dm_atomic_commit
Zaeem Mohamed (1):
SWDEV476969 - d
On Thu, Oct 24, 2024 at 3:55 PM Saravana Kannan wrote:
>
> On Wed, Oct 23, 2024 at 1:52 AM Tomi Valkeinen
> wrote:
> >
> > Hi,
> >
> > On 22/10/2024 19:07, Saravana Kannan wrote:
> > > On Tue, Oct 22, 2024 at 12:51 AM Tomi Valkeinen
> > > wrote:
> > >>
> > >> Hi,
> > >>
> > >> On 22/10/2024 02:2
On Fri, Oct 25, 2024 at 12:45:26PM +0200, Thomas Hellström wrote:
> On Fri, 2024-10-25 at 12:34 +0300, Jani Nikula wrote:
> > On Fri, 25 Oct 2024, Thomas Hellström
> > wrote:
> > > On Thu, 2024-10-24 at 19:22 +, Matthew Brost wrote:
> > > > On Thu, Oct 24, 2024 at 07:52:11PM +0200, Thomas Hell
On 10/24/24 08:49, Kasireddy, Vivek wrote:
> Hi Dmitry,
>
>> Subject: Re: [PATCH v2 2/5] drm/virtio: Add a helper to map and note the
>> dma addrs and lengths
>>
>> On 10/22/24 07:51, Kasireddy, Vivek wrote:
>>> Hi Dmitry,
>>>
On 8/13/24 06:49, Vivek Kasireddy wrote:
> +long virtgpu_
There are multiple places where special handling is required for IOV
resources.
Extract it to pci_resource_is_iov() helper and drop a few ifdefs.
Signed-off-by: Michał Winiarski
Reviewed-by: Ilpo Järvinen
---
drivers/pci/pci.h | 19 +++
drivers/pci/setup-bus.c | 7 +++---
On 10/25/2024 3:28 PM, Lizhi Hou wrote:
On 10/25/24 10:55, Jeffrey Hugo wrote:
On 10/21/2024 10:19 AM, Lizhi Hou wrote:
This patchset introduces a new Linux Kernel Driver, amdxdna for AMD
NPUs.
The driver is based on Linux accel subsystem.
NPU (Neural Processing Unit) is an AI inference acce
There are multiple places where conversions between IOV resources and
standard resources are done.
Extract the logic to pci_resource_to_iov() and pci_resource_from_iov()
helpers.
Suggested-by: Ilpo Järvinen
Signed-off-by: Michał Winiarski
---
drivers/pci/iov.c | 20 ++--
LMEM is partitioned between multiple VFs and we expect that the more
VFs we have, the less LMEM is assigned to each VF.
This means that we can achieve full LMEM BAR access without the need to
attempt full VF LMEM BAR resize via pci_resize_resource().
Always set the largest possible BAR size that a
Similar to regular resizable BAR, VF BAR can also be resized.
The structures are very similar, which means we can reuse most of the
implementation.
Extend the pci_resize_resource() function to accept IOV resources.
See PCIe r4.0, sec 9.3.7.4.
Signed-off-by: Michał Winiarski
---
drivers/pci/io
Drivers could leverage the fact that the VF BAR MMIO reservation is
created for total number of VFs supported by the device by resizing the
BAR to larger size when smaller number of VFs is enabled.
Add a pci_iov_vf_bar_set_size() function to control the size and a
pci_iov_vf_bar_get_sizes() helper
VF MMIO resource reservation, either created by system firmware and
inherited by Linux PCI subsystem or created by the subsystem itself,
should contain enough space to fit the BAR of all SR-IOV Virtual
Functions that can potentially be created (total VFs supported by the
device).
However, that ass
Similar to regular resizable BAR, VF BAR can also be resized, e.g. by
the system firmware or the PCI subsystem itself.
Add the capability ID and restore it as a part of IOV state.
See PCIe r4.0, sec 9.3.7.4.
Signed-off-by: Michał Winiarski
Reviewed-by: Ilpo Järvinen
---
drivers/pci/iov.c
On 10/25/24 10:55, Jeffrey Hugo wrote:
On 10/21/2024 10:19 AM, Lizhi Hou wrote:
This patchset introduces a new Linux Kernel Driver, amdxdna for AMD
NPUs.
The driver is based on Linux accel subsystem.
NPU (Neural Processing Unit) is an AI inference accelerator integrated
into AMD client CPUs.
Etnaviv assumes that GPU page size is 4KiB, however, GPUVA ranges collision
when using softpin capable GPUs on a non 4KiB CPU page size configuration.
The root cause is that kernel side BO takes up bigger address space than
userspace expect, the size of backing memory of GEM buffer objects are
requ
Etnaviv assumes that GPU page size is 4KiB, however, when using
softpin capable GPUs on a different CPU page size configuration.
The userspace allocated GPUVA ranges collision, unable to be
inserted to the specified address hole exactly.
For example, when running glmark2-drm:
[kernel space debug
The GPU visible size of a GEM BO is not necessarily PAGE_SIZE aligned,
which happens when CPU page size is not equal to GPU page size. Extra
precious resources such as GPU page tables and GPU TLBs may being paid
because of this but never get used.
Track the size of GPU visible part of GEM BO separ
On Fri, 25 Oct 2024 at 12:36, Helge Deller wrote:
>
> Do you want me to send a revert for this specific patch?
No, it's in now, more churn this time around just makes it worse. I
just don't want to see these kinds of non-fixes in the future.
Linus
[why]
Prevent index-out-of-bounds due to requiring cursor overlay when
plane_count is MAX_SURFACES.
[how]
Bounds check on plane_count when requiring overlay cursor.
Co-developed-by: Melissa Wen
Signed-off-by: Zaeem Mohamed
---
amdgpu_dm/amdgpu_dm.c | 16 +++-
1 file changed, 15 ins
Hi Linus,
On 10/25/24 20:31, Linus Torvalds wrote:
On Fri, 25 Oct 2024 at 09:04, Helge Deller wrote:
It's mostly about build warning fixes with cornercase CONFIG settings
and one big patch which removes the now unused da8xx fbdev driver.
So I pulled this, but only later noticed that some of
Hi Jakob,
thanks for your patch!
On Thu, Oct 24, 2024 at 5:18 AM Jakob Hauser wrote:
> The way of implementing a flip option follows the existing
> panel-samsung-s6e8aa0.c [1][2][3].
That driver is notoriously hard to read because it uses so much
magic numbers so please don't copy that aspect
Hi Jakob,
thanks for your patch!
On Thu, Oct 24, 2024 at 5:18 AM Jakob Hauser wrote:
> +static const int s6e88a0_ams427ap24_br_to_cd[NUM_STEPS_CANDELA] = {
(...)
> + /* brightness till, candela */
Brightness to candela conversion table? Edit comment?
> +static const u8 s6e88a0_ams427ap2
On 10/24/2024 5:20 PM, Dmitry Baryshkov wrote:
In preparation for virtualized planes support, move pstate->pipe
initialization from dpu_plane_reset() to dpu_plane_atomic_check(). In
case of virtual planes the plane's pipe will not be known up to the
point of atomic_check() callback.
I had R
Right now every time the fdinfo is read, we go through the vm lists and
lock all the BOs to calcuate the statistics. This causes a lot of lock
contention when the VM is actively used. It gets worse if there is a lot
of shared BOs or if there's a lot of submissions. We have seen
submissions lock-up
On 10/16/2024 8:36 PM, Andi Shyti wrote:
Hi Jyothi,
...
@@ -523,26 +576,49 @@ static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct
i2c_msg *msg,
enum dma_transfer_direction dma_dirn;
struct dma_async_tx_descriptor *desc;
int ret;
+ struct gpi_multi_xfer *gi
There are a few minor changes in the display list generation
for the D-step of the chip, so add them.
Signed-off-by: Dave Stevenson
Reviewed-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_plane.c | 72 ++---
drivers/gpu/drm/vc4/vc4_regs.h | 9 --
2 files
On Fri, 25 Oct 2024 at 09:04, Helge Deller wrote:
>
> It's mostly about build warning fixes with cornercase CONFIG settings
> and one big patch which removes the now unused da8xx fbdev driver.
So I pulled this, but only later noticed that some of the Kconfig
"fixes" are anything but.
At least co
On 10/16/2024 10:24 AM, Vinod Koul wrote:
On 15-10-24, 17:37, Jyothi Kumar Seerapu wrote:
When high performance with multiple i2c messages in a single transfer
is required, employ Block Event Interrupt (BEI) to trigger interrupts
after specific messages transfer and the last message transfer,
On 10/15/2024 7:31 PM, Rob Herring wrote:
On Tue, Oct 15, 2024 at 05:37:46PM +0530, Jyothi Kumar Seerapu wrote:
When high performance with multiple i2c messages in a single transfer
is required, employ Block Event Interrupt (BEI) to trigger interrupts
after specific messages transfer and the la
The pull request you sent on Fri, 25 Oct 2024 17:10:25 +1000:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-fixes-2024-10-25
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/fd143856b094b1798318d6816f37ea7380668c4c
Thank you!
--
Deet-doot-dot, I am a bot.
h
On 15.10.2024 2:07 PM, Jyothi Kumar Seerapu wrote:
> The current GPI driver hardcodes the channel TRE (Transfer Ring Element)
> size to 64. For scenarios requiring high performance with multiple
> messages in a transfer, use Block Event Interrupt (BEI).
> This method triggers interrupt after specif
On 10/15/2024 7:01 PM, Krzysztof Kozlowski wrote:
On 15/10/2024 14:07, Jyothi Kumar Seerapu wrote:
When high performance with multiple i2c messages in a single transfer
is required, employ Block Event Interrupt (BEI) to trigger interrupts
after specific messages transfer and the last message t
GSI hardware generates an interrupt for each transfer completion.
For multiple messages within a single transfer, this results
in receiving N interrupts for N messages, which can introduce
significant software interrupt latency. To mitigate this latency,
utilize Block Event Interrupt (BEI) only whe
The I2C driver gets an interrupt upon transfer completion.
For multiple messages in a single transfer, N interrupts will be
received for N messages, leading to significant software interrupt
latency. To mitigate this latency, utilize Block Event Interrupt (BEI)
only when an interrupt is necessary.
I2C_QCOM_GENI is having compile dependencies on QCOM_GPI_DMA and
so update I2C_QCOM_GENI to depends on QCOM_GPI_DMA.
Signed-off-by: Jyothi Kumar Seerapu
---
v1 -> v2:
This patch is added in v2 to address the kernel test robot
reported compilation error.
ERROR: modpost: "
The I2C driver gets an interrupt upon transfer completion.
For multiple messages in a single transfer, N interrupts will be
received for N messages, leading to significant software interrupt
latency. To mitigate this latency, utilize Block Event Interrupt (BEI)
only when an interrupt is necessary.
The pull request you sent on Fri, 25 Oct 2024 18:04:12 +0200:
> http://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev.git
> tags/fbdev-for-6.12-rc5
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/86d6688e6099594e732841ddad69fad196e95245
Thank you!
--
Dee
On 10/21/2024 10:19 AM, Lizhi Hou wrote:
This patchset introduces a new Linux Kernel Driver, amdxdna for AMD NPUs.
The driver is based on Linux accel subsystem.
NPU (Neural Processing Unit) is an AI inference accelerator integrated
into AMD client CPUs. NPU enables efficient execution of Machine
On 10/22/24 07:44, Kasireddy, Vivek wrote:
>> virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle,
>> x, y,
>> - width, height, objs, vgfb->fence);
>> + width, height, objs,
>> +
> Thanks a lot for helping. The revert is at
>
> https://lore.kernel.org/dri-devel/20241015063932.8620-1-tzimmerm...@suse.de/T/#u
Thomas,
Final closure. That patch was pulled by Linus into v6.12-rc4. I just built and
booted with no problems.
Thanks
-Tony
The registers have been moved around, and a couple of minor changes
made, so adapt for this.
Signed-off-by: Dave Stevenson
Reviewed-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.h | 6 ++
drivers/gpu/drm/vc4/vc4_hvs.c | 154 +
drivers/gpu/drm/vc4/
The etnaviv_cmdbuf.c doesn't reference any functions or data members
defined in drm_mm.h, remove unneeded headers may reduce kernel compile
times.
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv
On 10/21/2024 10:19 AM, Lizhi Hou wrote:
diff --git a/include/uapi/drm/amdxdna_accel.h b/include/uapi/drm/amdxdna_accel.h
index 3792750834b2..08f3ec7146ab 100644
--- a/include/uapi/drm/amdxdna_accel.h
+++ b/include/uapi/drm/amdxdna_accel.h
@@ -13,6 +13,7 @@
extern "C" {
#endif
+#define AMD
From: Maxime Ripard
The BCM2712 SoC comes with a new variation of the videocore display
pipeline. Let's create a new compatible for it.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
Acked-by: Rob Herring (Arm)
---
Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml |
Because it is not get used, drop it.
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/etnaviv/etnaviv_mmu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_mmu.h
b/drivers/gpu/drm/etnaviv/etnaviv_mmu.h
index c01a147f0dfd..7f8ac0178547 100644
--- a/drivers/gpu/d
On 10/21/2024 10:19 AM, Lizhi Hou wrote:
When there is a hardware error, the NPU firmware notifies the host through
a mailbox message. The message includes details of the error, such as the
tile and column indexes where the error occurred.
The driver starts a thread to handle the NPU error messa
Hi,
On 2024/10/7 18:12, Lucas Stach wrote:
Am Samstag, dem 05.10.2024 um 03:42 +0800 schrieb Sui Jingfeng:
Etnaviv assumes that GPU page size is 4KiB, yet on some systems, the CPU
page size is 16KiB. The size of etnaviv buffer objects will be aligned
to CPU page size on kernel side, however, us
amdgpu_vm_bo_invalidate doesn't use the adev parameter and not all
callers have a reference to adev handy, so remove it for cleanliness.
Signed-off-by: Yunxiang Li
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
Add a helper to check if the memory stats is zero, this will be used to
check for memory accounting errors.
Signed-off-by: Yunxiang Li
---
drivers/gpu/drm/drm_file.c | 9 +
include/drm/drm_file.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/drm_file.c b/driv
Before, every time fdinfo is queried we try to lock all the BOs in the
VM and calculate memory usage from scratch. This works okay if the
fdinfo is rarely read and the VMs don't have a ton of BOs. If either of
these conditions is not true, we get a massive performance hit.
In this new revision, we
Since on modern systems all of vram can be made visible anyways, to
simplify the new implementation, drops tracking how much memory is
visible for now. If this is really needed we can add it back on top of
the new implementation.
Signed-off-by: Yunxiang Li
Reviewed-by: Christian König
---
drive
The old behavior reports the resident memory usage for this key and the
documentation say so as well. However this was accidentally changed to
include buffers that was evicted.
Fixes: a2529f67e2ed ("drm/amdgpu: Use drm_print_memory_stats helper from
fdinfo")
Signed-off-by: Yunxiang Li
Reviewed-b
Hi Dave,
Am 25.10.24 um 18:56 schrieb Dave Stevenson:
On Fri, 25 Oct 2024 at 17:31, Stefan Wahren wrote:
Hi Dave,
Am 25.10.24 um 16:38 schrieb Dave Stevenson:
Hi Stefan
On Fri, 25 Oct 2024 at 14:36, Stefan Wahren wrote:
...
Based on that log I think your force_turbo=1 is a red-herring, o
From: Maxime Ripard
The BCM2712 has a MOPLET controller which is basically a TXP without the
transpose feature.
Express that by adding a new compatible for it.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
Acked-by: Rob Herring (Arm)
---
Documentation/devicetree/bindings/displa
The default was to have enable_bg_fill disabled and the first
plane set it if it wasn't opaque and covering the whole screen.
However that meant that if no planes were enabled, then the
background fill wasn't enabled, and would give a striped
output from the uninitialised output buffer.
Initialise
From: Maxime Ripard
The BCM2712 has an evolution of what used to be called TXP in the
earlier SoCs, but is now called MOP.
There's a few differences still, so we can add a new compatible to deal
with them easily.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/
From: Dom Cobley
There isn't a reason not to minimise the clocks, and it saves
some power.
Signed-off-by: Dom Cobley
Signed-off-by: Dave Stevenson
---
drivers/clk/bcm/clk-raspberrypi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c
b/drivers/clk/b
From: Dom Cobley
The ISP clock can be controlled by the driver, so register it
with the clock subsystem.
Signed-off-by: Dom Cobley
Signed-off-by: Dave Stevenson
---
drivers/clk/bcm/clk-raspberrypi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c
b/dr
Hi,
On 2024/10/7 18:17, Lucas Stach wrote:
Am Samstag, dem 05.10.2024 um 03:42 +0800 schrieb Sui Jingfeng:
Since the GPU VA space is compact in terms of 4KiB unit, map and/or unmap
the area that doesn't belong to a context breaks the philosophy of PPAS.
That results in severe errors: GPU hang
BCM2712 still uses the firmware clocks and power drivers, so add
them to the base device tree.
Signed-off-by: Dave Stevenson
---
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi
On 10/21/2024 2:03 PM, Jeffrey Hugo wrote:
The Sahara protocol has a crashdump functionality. In the hello
exchange, the device can advertise it has a memory dump available for
the host to collect. Instead of the device making requests of the host,
the host requests data from the device which can
From: Maxime Ripard
The RaspberryPi firmware clocks driver uses in several instances a
container_of to retrieve the struct raspberrypi_clk_data from a pointer
to struct clk_hw. Let's create a small function to avoid duplicating it
all over the place.
Signed-off-by: Maxime Ripard
Signed-off-by:
From: Maxime Ripard
The BCM2712 MOP and MOPLET can handle addresses larger than 32bits
through an extra register. We can easily support it and make it
conditional based on the compatible through a boolean in our variant
structure.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
Adds the HVS and associated hardware blocks to support the HDMI
and writeback connectors on BCM2712 / Pi5.
Signed-off-by: Dave Stevenson
---
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 14 ++
arch/arm64/boot/dts/broadcom/bcm2712.dtsi| 188 +++
2 files changed,
From: Maxime Ripard
We'll have multiple TXP instances in the BCM2712, so we can't use a
single encoder type anymore. Let's tie the encoder type to the
compatible.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_drv.h | 1 +
drivers/gpu/drm/vc4/vc4_txp.c
The D-step has increased FIFO sizes of the MAI_THR blocks,
resulting in changes to the register masking. Add support for
it.
Signed-off-by: Dave Stevenson
Reviewed-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 19 +--
drivers/gpu/drm/vc4/vc4_regs.h | 9 +
2 fil
It is permitted for a plane to be configured such that none
of it is on-screen via either negative dest rectangle X,Y
offset, or an offset that is greater than the crtc dimensions.
These planes were resized via drm_atomic_helper_check_plane_state
such that the source rectangle had a zero width or
From: Maxime Ripard
Starting with BCM2712, we'll have a two TXP. Let's follow the HDMI
example and add two encoder types for TXP: TXP0 and TXP1.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/tests/vc4_mock.c | 4 +-
drivers/gpu/drm/vc4/tests/vc
From: Maxime Ripard
Some code path in vc4 are conditional to a generation and cannot be
executed on others. Let's put a WARN_ON if that ever happens.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_hvs.c | 30 --
drivers/gpu
Add in the compatible string and VC4_GEN_ enum for the D-step
Signed-off-by: Dave Stevenson
Reviewed-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.c | 1 +
drivers/gpu/drm/vc4/vc4_drv.h | 1 +
drivers/gpu/drm/vc4/vc4_hvs.c | 4
drivers/gpu/drm/vc4/vc4_regs.h | 3 +++
4 files changed
From: Maxime Ripard
The BCM2712 will have several TXP with small differences. Let's add a
structure tied to the compatible to deal with those differences.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/tests/vc4_mock.c | 4 ++--
drivers/gpu/drm/vc4/vc4_drv
From: Maxime Ripard
The BCM2712 features a simpler TXP called MOPLET. Let's add support for
it.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_txp.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_txp.c b/driv
The D-Step has some minor variations in the hardware, so needs
matching changes to DT.
Add a new DTS file that modifies the existing (C-step) devicetree.
Signed-off-by: Dave Stevenson
---
arch/arm64/boot/dts/broadcom/Makefile | 1 +
arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.d
From: Maxime Ripard
The BCM2712 has an improved display pipeline, most notably with a
different HVS and only HDMI and writeback outputs.
Let's introduce it as a new VideoCore generation and compatible.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_drv
From: Maxime Ripard
The BCM2712 has 3 different pixelvalves that are similar to the ones
found in the previous generations but with slightly different
capabilities.
Express that using a new set of compatibles.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
Acked-by: Rob Herring (A
From: Maxime Ripard
The MOPLET doesn't have the BYTE_ENABLE field to set, but the TXP and
MOP do, so let's add a boolean to control whether or not we need to set
it.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_drv.h | 1 +
drivers/gpu/drm/vc4/vc4_txp
From: Maxime Ripard
BCM2712 has an extra clock exposed by the firmware called DISP, and used
by (at least) the HVS. Let's add it to the list of clocks to register in
Linux.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/clk/bcm/clk-raspberrypi.c | 5 +
inc
From: Dom Cobley
For performance/power it is beneficial to adjust gpu clocks with arm clock.
This is how the downstream cpufreq driver works
Signed-off-by: Dom Cobley
Signed-off-by: Dave Stevenson
---
drivers/clk/bcm/clk-raspberrypi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers
From: Maxime Ripard
The TXP data structure has a name too generic for the multiple variants
we'll have to support. Let's rename it to mention the SoC it applies to.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenson
---
drivers/gpu/drm/vc4/tests/vc4_mock.c | 4 ++--
drivers/gpu/drm/vc
Use of_device_get_match_data to retrieve the generation value
as set in the struct of_device_id, rather than manually comparing
compatible strings.
Signed-off-by: Dave Stevenson
Reviewed-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.c | 11 ---
1 file changed, 4 insertions(+), 7 del
From: Maxime Ripard
The HDMI controllers found in the BCM2712 are largely the ones found in
the BCM2711 with a different PHY.
There's some difference with how timings are split between registers,
and HDMI1 is now able to run at 4k/60Hz.
Signed-off-by: Maxime Ripard
Signed-off-by: Dave Stevenso
1 - 100 of 259 matches
Mail list logo
