On Sat, Aug 31, 2024 at 12:55:29AM +0300, Cristian Ciocaltea wrote:
> Add dt-binding schema containing the common properties for the Synopsys
> DesignWare HDMI QP TX controller.
>
> Note this is not a full dt-binding specification, but is meant to be
> referenced by platform-specific bindings for
On Sat, Aug 31, 2024 at 12:55:31AM +0300, Cristian Ciocaltea wrote:
> Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI 2.1
> Quad-Pixel (QP) TX controller IP.
>
> Since this is a new IP block, quite different from those used in the
> previous generations of Rockchip SoCs, add a dedicate
sizeof(unsigned long) * 8 is the number of bits in an unsigned long
variable, replace it with BITS_PER_LONG macro to make them simpler.
And fix the warning:
WARNING: Comparisons should place the constant on the right side of the
test
#23: FILE: drivers/gpu/drm/panthor/panthor_mmu.
Add an interface for the user to notify the kernel that it is done
reading the devmem dmabuf frags returned as cmsg. The kernel will
drop the reference on the frags to make them available for reuse.
Signed-off-by: Willem de Bruijn
Signed-off-by: Kaiyuan Zhang
Signed-off-by: Mina Almasry
Reviewe
Make skb_frag_page() fail in the case where the frag is not backed
by a page, and fix its relevant callers to handle this case.
Signed-off-by: Mina Almasry
Reviewed-by: Eric Dumazet
---
v10:
- Fixed newly generated kdoc warnings found by patchwork. While we're
at it, fix the Return section
Implement a memory provider that allocates dmabuf devmem in the form of
net_iov.
The provider receives a reference to the struct netdev_dmabuf_binding
via the pool->mp_priv pointer. The driver needs to set this pointer for
the provider in the net_iov.
The provider obtains a reference on the netde
ncdevmem is a devmem TCP netcat. It works similarly to netcat, but it
sends and receives data using the devmem TCP APIs. It uses udmabuf as
the dmabuf provider. It is compatible with a regular netcat running on
a peer, or a ncdevmem running on a peer.
In addition to normal netcat support, ncdevmem
Add documentation outlining the usage and details of devmem TCP.
Signed-off-by: Mina Almasry
Reviewed-by: Bagas Sanjaya
Reviewed-by: Donald Hunter
---
v16:
- Add documentation on unbinding the NIC from dmabuf (Donald).
- Add note that any dmabuf should work (Donald).
v9:
https://lore.kernel
In tcp_recvmsg_locked(), detect if the skb being received by the user
is a devmem skb. In this case - if the user provided the MSG_SOCK_DEVMEM
flag - pass it to tcp_recvmsg_devmem() for custom handling.
tcp_recvmsg_devmem() copies any data in the skb header to the linear
buffer, and returns a cmsg
Add dmabuf information to page_pool stats:
$ ./cli.py --spec ../netlink/specs/netdev.yaml --dump page-pool-get
...
{'dmabuf': 10,
'id': 456,
'ifindex': 3,
'inflight': 1023,
'inflight-mem': 4190208},
{'dmabuf': 10,
'id': 455,
'ifindex': 3,
'inflight': 1023,
'inflight-mem': 4190208
For device memory TCP, we expect the skb headers to be available in host
memory for access, and we expect the skb frags to be in device memory
and unaccessible to the host. We expect there to be no mixing and
matching of device memory frags (unaccessible) with host memory frags
(accessible) in the
Convert netmem to be a union of struct page and struct netmem. Overload
the LSB of struct netmem* to indicate that it's a net_iov, otherwise
it's a page.
Currently these entries in struct page are rented by the page_pool and
used exclusively by the net stack:
struct {
unsigned long pp_mag
Add netdev_rx_queue_restart(), which resets an rx queue using the
queue API recently merged[1].
The queue API was merged to enable the core net stack to reset individual
rx queues to actuate changes in the rx queue's configuration. In later
patches in this series, we will use netdev_rx_queue_resta
Add a netdev_dmabuf_binding struct which represents the
dma-buf-to-netdevice binding. The netlink API will bind the dma-buf to
rx queues on the netdevice. On the binding, the dma_buf_attach
& dma_buf_map_attachment will occur. The entries in the sg_table from
mapping will be inserted into a genpool
Implement netdev devmem allocator. The allocator takes a given struct
netdev_dmabuf_binding as input and allocates net_iov from that
binding.
The allocation simply delegates to the binding's genpool for the
allocation logic and wraps the returned memory region in a net_iov
struct.
Signed-off-by:
API takes the dma-buf fd as input, and binds it to the netdevice. The
user can specify the rx queues to bind the dma-buf to.
Suggested-by: Stanislav Fomichev
Signed-off-by: Mina Almasry
Reviewed-by: Donald Hunter
Reviewed-by: Jakub Kicinski
---
v16:
- Use subset-of: queue queue-id instead of
v24: https://patchwork.kernel.org/project/netdevbpf/list/?series=884556&state=*
Changes:
- Fix failing ynl regen error.
- Error path fixes & extack error messages in dmabuf binding.
Full devmem TCP changes including the full GVE driver implementation is
here:
https://github.com/mina/linux/c
Hi Louis,
kernel test robot noticed the following build errors:
[auto build test ERROR on 071d583e01c88272f6ff216d4f867f8f35e94d7d]
url:
https://github.com/intel-lab-lkp/linux/commits/Louis-Chauvet/drm-vkms-Switch-to-managed-for-connector/20240827-180427
base: 071d583e01c88272f6ff216d4f867
On Fri, 30 Aug 2024 at 23:28, Jessica Zhang wrote:
>
>
>
> On 8/30/2024 10:47 AM, Dmitry Baryshkov wrote:
> > On Thu, Aug 29, 2024 at 01:48:36PM GMT, Jessica Zhang wrote:
> >> Cache the CWB block mask in the DPU virtual encoder and configure CWB
> >> according to the CWB block mask within the writ
On Fri, Aug 30, 2024 at 12:40:57PM +0200, Boris Brezillon wrote:
> dma_fence objects created by drm_sched might hit other subsystems, which
> means the fence object might potentially outlive the drm_sched module
> lifetime, and at this point the dma_fence::ops points to a memory region
> that no lo
On Fri, 30 Aug 2024 at 23:28, Jessica Zhang wrote:
> On 8/30/2024 10:25 AM, Dmitry Baryshkov wrote:
> > On Thu, Aug 29, 2024 at 01:48:35PM GMT, Jessica Zhang wrote:
> >> Reserve dedicated pingpong blocks for CWB
> >
> > Please explain design ideas. Having just a single phrase is usually not
> > en
On Fri, Aug 30, 2024 at 03:36:54PM +0800, Jinjie Ruan wrote:
> Avoids the need for manual cleanup of_node_put() in early exits
> from the loop.
>
> Signed-off-by: Jinjie Ruan
Applied to drm-misc-next, thanks!
On 8/27/24 11:58 AM, Maxime Ripard wrote:
> On Mon, Aug 19, 2024 at 01:29:29AM GMT, Cristian Ciocaltea wrote:
>> +static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id)
>> +{
>> +struct dw_hdmi_qp *hdmi = dev_id;
>> +struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
>> +u32 stat;
>> +
On Fri, 30 Aug 2024 at 22:28, Jessica Zhang wrote:
>
>
>
> On 8/30/2024 10:18 AM, Dmitry Baryshkov wrote:
> > On Thu, Aug 29, 2024 at 01:48:32PM GMT, Jessica Zhang wrote:
> >> Add support for allocating the concurrent writeback mux as part of the
> >> WB allocation
> >>
> >> Signed-off-by: Jessica
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 78c6d5b64..8fd539125 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -31,7 +31,
diff --git
a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml
b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml
new file mode 100644
index 0..e71544ced
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/rock
Dear Dmitry,
For context, I have a Lenovo Yoga Slim 7x laptop, and was having issues
with the display staying black after sleep. As a workaround, I could
switch to a different VT and back.
[ 1185.831970] [dpu error]connector not connected 3
I can confirm that I was seeing this exact error
diff --git
a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml
b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml
new file mode 100644
index 0..141899ba2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-
Geez, my email system seems to have screwed up this submission by
duplicate-sending messages for some reason. Just FYI.
Shimrra
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 7df875e38..1cd8a3774 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -8,6 +8,7 @@ config DRM_ROCKCHIP
select VIDEOMODE_HELPERS
select DRM_ANALOGIX_DP if ROC
Cristian Ciocaltea wrote:
> Please stop doing this!
>
> I appreciate your intention to help, but this is not the proper way of
> doing it. This is a work-in-progress series and you should have asked
> before taking over. Please do not interfere with other people's work
> without having a prelimin
Hi,
I saw Cristian Ciocaltea's proposed basic driver for the Synopsys DW
HDMI QP transmit (TX) facility on the Rockchip RK3588 and noticed that
it had seen some critique and thought I'd help it along a little by
making some of the changes that others had suggested in the discussion
thread. This pa
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index b6e4df180..76cb0f7f7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -582,13 +582,13 @@ vop_grf: syscon@fd5a4000 {
diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig
b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 15fc182d0..58b42a2b9 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -7,6 +7,14 @@ config DRM_DW_HDMI
select REGMAP_MMIO
select
The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX Controller IP
supports the following features, among others:
* Fixed Rate Link (FRL)
* Display Stream Compression (DSC)
* 4K@120Hz and 8K@60Hz video modes
* Variable Refresh Rate (VRR) including Quick Media Switching (QMS), aka
Cinema VRR
* Fas
The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1
Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a
Samsung IP block.
Add just the basic support for now, i.e. RGB output up to 4K@60Hz,
without audio, CEC or any of the HDMI 2.1 specific features.
Co-deve
Add dt-binding schema containing the common properties for the Synopsys
DesignWare HDMI QP TX controller.
Note this is not a full dt-binding specification, but is meant to be
referenced by platform-specific bindings for this IP core.
Signed-off-by: Cristian Ciocaltea
---
.../display/bridge/syno
The Rockchip RK3588 SoC family integrates the Synopsys DesignWare HDMI
2.1 Quad-Pixel (QP) TX controller, which is a new IP block, quite
different from those used in the previous generations of Rockchip SoCs.
The controller supports the following features, among others:
* Fixed Rate Link (FRL)
*
Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI 2.1
Quad-Pixel (QP) TX controller IP.
Since this is a new IP block, quite different from those used in the
previous generations of Rockchip SoCs, add a dedicated binding file.
Signed-off-by: Cristian Ciocaltea
---
.../rockchip/rockchip
On Fri, Aug 30, 2024 at 12:26 PM T.J. Mercier wrote:
>
> Until VM_DONTEXPAND was added in commit 1c1914d6e8c6 ("dma-buf: heaps:
> Don't track CMA dma-buf pages under RssFile") it was possible to obtain
> a mapping larger than the buffer size via mremap and bypass the overflow
> check in dma_buf_mm
On Fri, Aug 30, 2024 at 10:14:18AM +0200, Christian König wrote:
> Am 29.08.24 um 19:12 schrieb Boris Brezillon:
> > dma_fence objects created by an entity might outlive the
> > drm_gpu_scheduler this entity was bound to if those fences are retained
> > by other other objects, like a dma_buf resv.
Hi Louis,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 071d583e01c88272f6ff216d4f867f8f35e94d7d]
url:
https://github.com/intel-lab-lkp/linux/commits/Louis-Chauvet/drm-vkms-Switch-to-managed-for-connector/20240827-180427
base: 071d583e01c88272f6ff216d4
On 8/30/2024 1:40 AM, Thomas Zimmermann wrote:
Call drm_client_setup() to run the kernel's default client setup
for DRM. Set fbdev_probe in struct drm_driver, so that the client
setup can start the common fbdev client.
Signed-off-by: Thomas Zimmermann
Cc: Neil Armstrong
Cc: Jessica Zhang
R
On Fri, Aug 30, 2024 at 10:39:55AM +0200, Thomas Zimmermann wrote:
> Call drm_client_setup_with_fourcc() to run the kernel's default client
> setup for DRM. Set fbdev_probe in struct drm_driver, so that the client
> setup can start the common fbdev client.
>
> v3:
> - add DRM_FBDEV_DMA_DRIVER_OPS
Hi, Xiaolei
Thanks for your nice catch! I have more to say.
On 2024/8/16 09:55, Wang, Xiaolei wrote:
Ping ...
32 address -> 32-bit address,
Perhaps, we could improve the commit title a little bit
by writing a more accurate sentence if possible, say:
drm/etnaviv: Properly request pages from
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
On Sat, Aug 10, 2024 at 09:09:18AM +, Chun-Kuang Hu wrote:
> In order to have fine-grained control, use cmdq_pkt_eoc() and
> cmdq_pkt_jump_rel() to replace cmdq_pkt_finalize().
This commit description doesn't match what you're doing. What about
Now that all occurrences of cmdq_pkt_finalize()
On 8/30/2024 10:47 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:36PM GMT, Jessica Zhang wrote:
Cache the CWB block mask in the DPU virtual encoder and configure CWB
according to the CWB block mask within the writeback phys encoder
Signed-off-by: Jessica Zhang
---
drivers/gpu/
On 8/30/2024 10:25 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:35PM GMT, Jessica Zhang wrote:
Reserve dedicated pingpong blocks for CWB
Please explain design ideas. Having just a single phrase is usually not
enough.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/di
On Sat, Aug 10, 2024 at 09:09:17AM +, Chun-Kuang Hu wrote:
> Use cmdq_pkt_create() and cmdq_pkt_destroy() common function
> instead of implementing mdp3 version.
>
> Signed-off-by: Chun-Kuang Hu
> ---
> .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c| 45 ++-
> 1 file changed,
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
As long as you make sure to fix the patch name from drm/amdgpu to drm/nouveau
like Alex mentioned:
Reviewed-by: Lyude Paul
On Fri, 2024-08-30 at 09:22 +0800, Li Zetao wrote:
> When it needs to get a value within a certain interval, using clamp()
> makes the code easier to understand than min(max
On Fri, Aug 30, 2024 at 12:09 PM Connor Abbott wrote:
>
> On Fri, Aug 30, 2024 at 8:00 PM Rob Clark wrote:
> >
> > On Fri, Aug 30, 2024 at 11:54 AM Connor Abbott wrote:
> > >
> > > On Fri, Aug 30, 2024 at 7:08 PM Rob Clark wrote:
> > > >
> > > > On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscal
On Sat, Aug 24, 2024 at 12:54:50AM +0200 Daniel Gomez wrote:
> On Wed, Aug 07, 2024 at 05:46:03PM +0200, Nicolas Schier wrote:
> > On Wed, Aug 07, 2024 at 04:18:54PM +0200, Greg Kroah-Hartman wrote:
> > > On Wed, Aug 07, 2024 at 02:13:57PM +, Daniel Gomez wrote:
> > > > > Also, as this is not i
Hi Shimrra,
On 8/30/24 8:54 PM, Shimrra Shai wrote:
> Cristian Ciocaltea wrote:
>> Please stop doing this!
>>
>> I appreciate your intention to help, but this is not the proper way of
>> doing it. This is a work-in-progress series and you should have asked
>> before taking over. Please do not in
On 2024/8/31 03:40, Sui Jingfeng wrote:
Hi, Xiaolei
On 2024/8/16 09:55, Wang, Xiaolei wrote:
Ping ...
I think, the more proper fix that Lucas hint
is to modify the 'priv->shm_gfp_mask' variable
in the|etnaviv_bind() function|. Say:
|Use "priv->shm_gfp_mask = GFP_USER | __GFP_RETRY_MAYFAIL |
On 8/30/2024 9:38 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:23PM GMT, Jessica Zhang wrote:
Add clone mode status to the DRM atomic print state
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm
Hi, Xiaolei
On 2024/8/16 09:55, Wang, Xiaolei wrote:
Ping ...
I think, the more proper fix that Lucas hint
is to modify the 'priv->shm_gfp_mask' variable
in the|etnaviv_bind() function|. Say:
|Use "priv->shm_gfp_mask = GFP_USER | __GFP_RETRY_MAYFAIL | __GFP_NOWARN;"|
instead of
|"priv->shm_
On 8/30/2024 10:18 AM, Dmitry Baryshkov wrote:
On Thu, Aug 29, 2024 at 01:48:32PM GMT, Jessica Zhang wrote:
Add support for allocating the concurrent writeback mux as part of the
WB allocation
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 5 -
driver
Until VM_DONTEXPAND was added in commit 1c1914d6e8c6 ("dma-buf: heaps:
Don't track CMA dma-buf pages under RssFile") it was possible to obtain
a mapping larger than the buffer size via mremap and bypass the overflow
check in dma_buf_mmap_internal. When using such a mapping to attempt to
fault past
On Fri, Aug 30, 2024 at 8:00 PM Rob Clark wrote:
>
> On Fri, Aug 30, 2024 at 11:54 AM Connor Abbott wrote:
> >
> > On Fri, Aug 30, 2024 at 7:08 PM Rob Clark wrote:
> > >
> > > On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
> > > wrote:
> > > >
> > > > This patch implements preemption featu
On Fri, Aug 30, 2024 at 08:45:44AM +, Rohit Agarwal wrote:
> Add clock/irq/efuse setting in svs nodes for mt8186 SoC.
>
> Signed-off-by: Rohit Agarwal
Reviewed-by: Nícolas F. R. A. Prado
Although FWIW the SVS driver fails to probe as is, as for MT8186 it expects
"cpu-big", "cpu-little" and
On Fri, Aug 30, 2024 at 11:54 AM Connor Abbott wrote:
>
> On Fri, Aug 30, 2024 at 7:08 PM Rob Clark wrote:
> >
> > On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
> > wrote:
> > >
> > > This patch implements preemption feature for A6xx targets, this allows
> > > the GPU to switch to a higher
On Fri, Aug 30, 2024 at 7:08 PM Rob Clark wrote:
>
> On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
> wrote:
> >
> > This patch implements preemption feature for A6xx targets, this allows
> > the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> > hardware as such support
On Tue, Aug 27, 2024 at 04:10:31PM +, Matthew Brost wrote:
> On Tue, Aug 27, 2024 at 08:37:56AM +0200, Christian König wrote:
> > Am 26.08.24 um 21:23 schrieb Matthew Brost:
> > > On Mon, Aug 26, 2024 at 07:57:07PM +0200, Christian König wrote:
> > > > Am 26.08.24 um 19:01 schrieb Matthew Brost
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> Use the postamble to reset perf counters when switching between rings,
> except when sysprof is enabled, analogously to how they are reset
> between submissions when switching pagetables.
>
> Signed-off-by: Antonino Maniscalco
> ---
>
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> Initialize with 4 rings to enable preemption.
>
> For now only on A750 as other targets require testing.
>
> Signed-off-by: Antonino Maniscalco
> Tested-by: Neil Armstrong # on SM8650-QRD
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.
On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from co
On Thu, 29 Aug 2024 22:41:17 -0700 Mina Almasry wrote:
> Thank you, I think the right fix here is to reacquire rtnl_lock before
> the `goto err_unbind;`, since err_unbind expects rtnl to be locked at
> this point.
FWIW it's best to keep the error path a mirror image of the success
path, so I'd add
On Thu, Aug 29, 2024 at 01:48:36PM GMT, Jessica Zhang wrote:
> Cache the CWB block mask in the DPU virtual encoder and configure CWB
> according to the CWB block mask within the writeback phys encoder
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2
On Thu, Aug 29, 2024 at 01:48:31PM GMT, Jessica Zhang wrote:
> From: Esha Bharadwaj
>
> Add function ops to allow hw_wb to configure CWB registers and adjust
> the WB_MUX configuration to account for using dedicated CWB pingpong
> blocks.
>
> Signed-off-by: Esha Bharadwaj
> Signed-off-by: Jessi
On Thu, Aug 29, 2024 at 01:48:42PM GMT, Jessica Zhang wrote:
> Set writeback encoders as possible clones for non-writeback encoders and
> vice versa.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 27 +++
> drivers/gpu/drm/msm/disp/
On Thu, Aug 29, 2024 at 01:48:41PM GMT, Jessica Zhang wrote:
> Add a helper that will handle the correct order of the encoder kickoffs
> for concurrent writeback.
>
> For concurrent writeback, the realtime encoder must always kickoff last
> as it will call the trigger flush and start.
>
> This av
On Thu, Aug 29, 2024 at 01:48:40PM GMT, Jessica Zhang wrote:
> For concurrent writeback, the real time encoder is responsible for
> trigger flush and trigger start. Return early for trigger start and
> trigger flush for the concurrent writeback encoders.
>
> Signed-off-by: Jessica Zhang
> ---
>
On Thu, Aug 29, 2024 at 01:48:39PM GMT, Jessica Zhang wrote:
> Create a separate API for starting the encoder frame done timer and call
> it after the encoder kickoff is finished
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 +++-
> drivers/gpu/drm/msm
On Thu, Aug 29, 2024 at 01:48:38PM GMT, Jessica Zhang wrote:
> Adjust QoS remapper, OT limit, and CDP parameters to account for
> concurrent writeback
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 ---
> 1 file changed, 8 insertions(+),
On Thu, Aug 29, 2024 at 01:48:37PM GMT, Jessica Zhang wrote:
> Add support for configuring the CWB pending flush and active bits
Details are appreciated.
Other than that:
Reviewed-by: Dmitry Baryshkov
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
On Thu, Aug 29, 2024 at 01:48:35PM GMT, Jessica Zhang wrote:
> Reserve dedicated pingpong blocks for CWB
Please explain design ideas. Having just a single phrase is usually not
enough.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 ++--
> drivers
On Thu, Aug 29, 2024 at 01:48:34PM GMT, Jessica Zhang wrote:
> If the clone mode enabled status is changing, a modeset needs to happen
> so that the resources can be reassigned
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 ++
> 1 file changed, 6 inser
On Thu, Aug 29, 2024 at 01:48:33PM GMT, Jessica Zhang wrote:
> Add the cwb_enabled flag to msm_display topology and adjust the toplogy
> to account for concurrent writeback
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 --
> drivers/gpu/drm/msm/disp/d
On Thu, Aug 29, 2024 at 01:48:32PM GMT, Jessica Zhang wrote:
> Add support for allocating the concurrent writeback mux as part of the
> WB allocation
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 5 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 3
On 8/30/2024 9:58 AM, john.c.harri...@intel.com wrote:
From: John Harrison
To aid debug of sporadic issues, include the requested frequency in
the debug message as well as the actual frequency. That way we know
for certain that the clamping is not because the driver forgot to ask.
Signed-off
On Fri, 30 Aug 2024 07:35:12 -0700, Douglas Anderson wrote:
> When adding devm_regulator_bulk_get_const() I missed adding a stub for
> when CONFIG_REGULATOR is not enabled. Under certain conditions (like
> randconfig testing) this can cause the compiler to reports errors
> like:
>
> error: impli
On Thu, Aug 29, 2024 at 01:48:29PM GMT, Jessica Zhang wrote:
> From: Esha Bharadwaj
>
> Add new block for concurrent writeback mux to HW catalog and change
> pingpong index names to distinguish between general use pingpong blocks
> and pingpong blocks dedicated for concurrent writeback
Please sp
Hi Shimrra,
On 8/30/24 6:21 PM, Shimrra Shai wrote:
> Hi,
>
> I saw Cristian Ciocaltea's proposed basic driver for the Synopsys DW
> HDMI QP transmit (TX) facility on the Rockchip RK3588 and noticed that
> it had seen some critique and thought I'd help it along a little by
> making some of the ch
On Thu, Aug 29, 2024 at 01:48:30PM GMT, Jessica Zhang wrote:
> From: Esha Bharadwaj
>
> Implement instance of snapshot function to dump new registers used
> for cwb
>
> Signed-off-by: Esha Bharadwaj
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +
> 1
On Fri, Aug 30, 2024 at 07:42:52PM GMT, Dmitry Baryshkov wrote:
> On Thu, Aug 29, 2024 at 01:48:26PM GMT, Jessica Zhang wrote:
> > From: Dmitry Baryshkov
> >
> > All resource allocation is centered around the LMs. Then other blocks
> > (except DSCs) are allocated basing on the LMs that was select
On Thu, Aug 29, 2024 at 01:48:28PM GMT, Jessica Zhang wrote:
> Check that each encoder in the CRTC state's encoder_mask is marked as a
> possible clone for all other encoders in the encoder_mask and that only
> one CRTC is in clone mode at a time
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/
From: John Harrison
To aid debug of sporadic issues, include the requested frequency in
the debug message as well as the actual frequency. That way we know
for certain that the clamping is not because the driver forgot to ask.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_g
On Thu, Aug 29, 2024 at 01:48:26PM GMT, Jessica Zhang wrote:
> From: Dmitry Baryshkov
>
> All resource allocation is centered around the LMs. Then other blocks
> (except DSCs) are allocated basing on the LMs that was selected, and LM
> powers up the CRTC rather than the encoder.
>
> Moreover if
On Thu, Aug 29, 2024 at 01:48:23PM GMT, Jessica Zhang wrote:
> Add clone mode status to the DRM atomic print state
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/drm_atomic.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_at
Initialize with 4 rings to enable preemption.
For now only on A750 as other targets require testing.
Signed-off-by: Antonino Maniscalco
Tested-by: Neil Armstrong # on SM8650-QRD
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/dri
Use the postamble to reset perf counters when switching between rings,
except when sysprof is enabled, analogously to how they are reset
between submissions when switching pagetables.
Signed-off-by: Antonino Maniscalco
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +-
drivers/gp
Add trace points corresponding to preemption being triggered and being
completed for latency measurement purposes.
Signed-off-by: Antonino Maniscalco
Tested-by: Neil Armstrong # on SM8650-QRD
---
drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 7 +++
drivers/gpu/drm/msm/msm_gpu_trace.h |
This patch implements preemption feature for A6xx targets, this allows
the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
hardware as such supports multiple levels of preemption granularities,
ranging from coarse grained(ringbuffer level) to a more fine grained
such as draw-cal
Some userspace changes are necessary so add a flag for userspace to
advertise support for preemption when creating the submitqueue.
When this flag is not set preemption will not be allowed in the middle
of the submitted IBs therefore mantaining compatibility with older
userspace.
The flag is reje
In mesa CP_SET_CTXSWITCH_IB is renamed to CP_SET_AMBLE and some other
names are changed to match KGSL. Import those changes.
The changes have not been merged yet in mesa but are necessary for this
series.
Signed-off-by: Antonino Maniscalco
---
.../gpu/drm/msm/registers/adreno/adreno_pm4.xml
This patch adds a bit of infrastructure to give the different Adreno
targets the flexibility to setup the submitqueues per their needs.
Signed-off-by: Sharat Masetty
Signed-off-by: Antonino Maniscalco
Reviewed-by: Akhil P Oommen
Tested-by: Neil Armstrong # on SM8650-QRD
---
drivers/gpu/drm/ms
The bv_fence field of rbmemptrs was being used incorrectly as the BV
rptr shadow pointer in some places.
Add a bv_rptr field and change the code to use that instead.
Signed-off-by: Antonino Maniscalco
Reviewed-by: Akhil P Oommen
Tested-by: Neil Armstrong # on SM8650-QRD
---
drivers/gpu/drm/ms
Adds a field to `adreno_info` to store the GPU specific preempt record
size.
Signed-off-by: Antonino Maniscalco
Reviewed-by: Akhil P Oommen
Tested-by: Neil Armstrong # on SM8650-QRD
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 4
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
2 files
1 - 100 of 270 matches
Mail list logo
